Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17918867	1			T4	1296		T5	3454		T6	2156
all_pins[1]	17918867	1			T4	1296		T5	3454		T6	2156
all_pins[2]	17918867	1			T4	1296		T5	3454		T6	2156

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	45812754	1			T4	3587		T5	9058		T6	5734
values[0x1]	7943847	1			T4	301		T5	1304		T6	734
transitions[0x0=>0x1]	7943713	1			T4	301		T5	1304		T6	734
transitions[0x1=>0x0]	7943723	1			T4	301		T5	1304		T6	734

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17898911	1			T4	1275		T5	3450		T6	2128
all_pins[0]	values[0x1]	19956	1			T4	21		T5	4		T6	28
all_pins[0]	transitions[0x0=>0x1]	19895	1			T4	21		T5	4		T6	28
all_pins[0]	transitions[0x1=>0x0]	7923550	1			T4	280		T5	1300		T6	706
all_pins[1]	values[0x0]	17918577	1			T4	1296		T5	3454		T6	2156
all_pins[1]	values[0x1]	290	1			T28	1		T24	1		T143	8
all_pins[1]	transitions[0x0=>0x1]	249	1			T24	1		T143	8		T103	3
all_pins[1]	transitions[0x1=>0x0]	19915	1			T4	21		T5	4		T6	28
all_pins[2]	values[0x0]	9995266	1			T4	1016		T5	2154		T6	1450
all_pins[2]	values[0x1]	7923601	1			T4	280		T5	1300		T6	706
all_pins[2]	transitions[0x0=>0x1]	7923569	1			T4	280		T5	1300		T6	706
all_pins[2]	transitions[0x1=>0x0]	258	1			T28	1		T24	1		T143	8