Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 773 1 T28 7 T19 4 T73 7
all_values[1] 773 1 T28 7 T19 4 T73 7
all_values[2] 773 1 T28 7 T19 4 T73 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1172 1 T28 13 T19 6 T73 8
auto[1] 1147 1 T28 8 T19 6 T73 13


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 843 1 T28 10 T19 3 T73 4
auto[1] 1476 1 T28 11 T19 9 T73 17


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1296 1 T28 16 T19 5 T73 12
auto[1] 1023 1 T28 5 T19 7 T73 9


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 154 1 T28 3 T73 1 T142 1
all_values[0] auto[0] auto[0] auto[1] 50 1 T28 2 T73 1 T144 1
all_values[0] auto[0] auto[1] auto[0] 145 1 T19 2 T144 1 T142 1
all_values[0] auto[0] auto[1] auto[1] 68 1 T73 3 T142 1 T80 1
all_values[0] auto[1] auto[0] auto[1] 182 1 T28 1 T19 1 T73 1
all_values[0] auto[1] auto[1] auto[1] 174 1 T28 1 T19 1 T73 1
all_values[1] auto[0] auto[0] auto[0] 120 1 T28 4 T73 1 T142 2
all_values[1] auto[0] auto[0] auto[1] 94 1 T19 1 T142 1 T80 2
all_values[1] auto[0] auto[1] auto[0] 125 1 T28 1 T144 2 T142 3
all_values[1] auto[0] auto[1] auto[1] 100 1 T28 1 T73 2 T144 1
all_values[1] auto[1] auto[0] auto[1] 181 1 T19 2 T73 1 T142 1
all_values[1] auto[1] auto[1] auto[1] 153 1 T28 1 T19 1 T73 3
all_values[2] auto[0] auto[0] auto[0] 154 1 T28 1 T73 1 T145 2
all_values[2] auto[0] auto[0] auto[1] 63 1 T28 1 T19 1 T73 1
all_values[2] auto[0] auto[1] auto[0] 145 1 T28 1 T19 1 T73 1
all_values[2] auto[0] auto[1] auto[1] 78 1 T28 2 T73 1 T144 1
all_values[2] auto[1] auto[0] auto[1] 174 1 T28 1 T19 1 T73 1
all_values[2] auto[1] auto[1] auto[1] 159 1 T28 1 T19 1 T73 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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