Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	3937	1			T4	2		T5	2		T6	7
sha2_none	3924	1			T4	4		T5	2		T6	7
sha2_512	7377	1			T4	2		T5	1		T6	15
sha2_384	7249	1			T4	4		T5	2		T6	5
sha2_256	5981	1			T4	11		T6	14		T7	2

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18180

1

T4

9

T5

4

T6

29

auto[1]

10651

1

T4

14

T5

3

T6

19

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10581

1

T4

13

T5

2

T6

25

auto[1]

18250

1

T4

10

T5

5

T6

23

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

14930

1

T4

12

T5

2

T6

23

disabled

13901

1

T4

11

T5

5

T6

25

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4355	1			T4	1		T5	1		T6	6
key_none	7603	1			T4	2		T6	6		T7	1
key_1024	4239	1			T4	2		T5	1		T6	2
key_512	3614	1			T4	4		T5	1		T6	8
key_384	3249	1			T4	3		T5	2		T6	10
key_256	2876	1			T4	4		T5	1		T6	11
key_128	2825	1			T4	7		T5	1		T6	5

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18124

1

T4

11

T5

2

T6

21

auto[1]

10707

1

T4

12

T5

5

T6

27

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

28648

1

T4

23

T5

7

T6

48

disabled

183

1

T61

1

T62

2

T63

5

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1546

1

T4

2

T6

3

T8

4

enabled

auto[0]

auto[0]

auto[1]

1440

1

T4

3

T5

1

T6

6

enabled

auto[0]

auto[1]

auto[0]

1528

1

T4

1

T6

3

T7

1

enabled

auto[0]

auto[1]

auto[1]

1540

1

T6

2

T7

1

T8

2

enabled

auto[1]

auto[0]

auto[0]

4216

1

T6

2

T8

3

T9

1

enabled

auto[1]

auto[0]

auto[1]

1532

1

T4

1

T5

1

T6

1

enabled

auto[1]

auto[1]

auto[0]

1561

1

T4

3

T6

3

T8

2

enabled

auto[1]

auto[1]

auto[1]

1567

1

T4

2

T6

3

T8

3

disabled

auto[0]

auto[0]

auto[0]

1123

1

T4

1

T6

6

T9

1

disabled

auto[0]

auto[0]

auto[1]

1164

1

T6

2

T7

1

T8

5

disabled

auto[0]

auto[1]

auto[0]

1099

1

T4

2

T6

1

T7

2

disabled

auto[0]

auto[1]

auto[1]

1141

1

T4

4

T5

1

T6

2

disabled

auto[1]

auto[0]

auto[0]

5965

1

T4

1

T5

2

T6

3

disabled

auto[1]

auto[0]

auto[1]

1194

1

T4

1

T6

6

T8

2

disabled

auto[1]

auto[1]

auto[0]

1086

1

T4

1

T7

2

T8

6

disabled

auto[1]

auto[1]

auto[1]

1129

1

T4

1

T5

2

T6

5

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

14852

1

T4

12

T5

2

T6

23

enabled

disabled

78

1

T61

1

T62

1

T63

3

disabled

disabled

105

1

T62

1

T63

2

T154

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

13796

1

T4

11

T5

5

T6

25

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1006	1			T5	1		T7	1		T8	1
key_invalid	sha2_none	792	1			T8	1		T11	4		T13	1
key_invalid	sha2_512	817	1			T6	2		T7	1		T8	4
key_invalid	sha2_384	847	1			T6	1		T8	3		T10	2
key_invalid	sha2_256	799	1			T4	1		T6	3		T7	1
key_none	sha2_invalid	523	1			T6	2		T8	1		T26	2
key_none	sha2_none	482	1			T8	2		T27	1		T12	1
key_none	sha2_512	2492	1			T6	1		T8	2		T27	1
key_none	sha2_384	2545	1			T4	1		T6	1		T7	1
key_none	sha2_256	1513	1			T4	1		T6	2		T8	2
key_1024	sha2_invalid	474	1			T9	1		T27	1		T10	1
key_1024	sha2_none	514	1			T7	1		T8	1		T9	1
key_1024	sha2_512	1722	1			T8	2		T9	2		T10	2
key_1024	sha2_384	902	1			T5	1		T8	2		T12	1
key_512	sha2_invalid	436	1			T5	1		T6	1		T8	1
key_512	sha2_none	537	1			T4	1		T6	2		T7	1
key_512	sha2_512	570	1			T4	1		T6	1		T11	1
key_512	sha2_384	1207	1			T6	1		T8	3		T9	1
key_512	sha2_256	818	1			T4	2		T6	3		T8	2
key_384	sha2_invalid	487	1			T4	1		T6	1		T8	1
key_384	sha2_none	539	1			T5	1		T6	1		T9	1
key_384	sha2_512	579	1			T6	6		T8	1		T9	1
key_384	sha2_384	591	1			T4	1		T5	1		T6	1
key_384	sha2_256	1006	1			T4	1		T6	1		T8	1
key_256	sha2_invalid	520	1			T4	1		T6	3		T8	1
key_256	sha2_none	526	1			T4	2		T6	3		T8	3
key_256	sha2_512	583	1			T5	1		T6	4		T7	1
key_256	sha2_384	577	1			T7	1		T8	1		T10	1
key_256	sha2_256	636	1			T4	1		T6	1		T7	1
key_128	sha2_invalid	483	1			T27	1		T155	1		T54	1
key_128	sha2_none	520	1			T4	1		T5	1		T6	1
key_128	sha2_512	599	1			T4	1		T6	1		T9	1
key_128	sha2_384	564	1			T4	2		T6	1		T8	1
key_128	sha2_256	617	1			T4	3		T6	2		T9	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

575

1

T4

2

T6

2

T8

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1006	1			T5	1		T7	1		T8	1
key_invalid	sha2_none	792	1			T8	1		T11	4		T13	1
key_invalid	sha2_512	817	1			T6	2		T7	1		T8	4
key_invalid	sha2_384	847	1			T6	1		T8	3		T10	2
key_invalid	sha2_256	799	1			T4	1		T6	3		T7	1
key_none	sha2_invalid	523	1			T6	2		T8	1		T26	2
key_none	sha2_none	482	1			T8	2		T27	1		T12	1
key_none	sha2_512	2492	1			T6	1		T8	2		T27	1
key_none	sha2_384	2545	1			T4	1		T6	1		T7	1
key_none	sha2_256	1513	1			T4	1		T6	2		T8	2
key_1024	sha2_invalid	474	1			T9	1		T27	1		T10	1
key_1024	sha2_none	514	1			T7	1		T8	1		T9	1
key_1024	sha2_512	1722	1			T8	2		T9	2		T10	2
key_1024	sha2_384	902	1			T5	1		T8	2		T12	1
key_1024	sha2_256	575	1			T4	2		T6	2		T8	2
key_512	sha2_invalid	436	1			T5	1		T6	1		T8	1
key_512	sha2_none	537	1			T4	1		T6	2		T7	1
key_512	sha2_512	570	1			T4	1		T6	1		T11	1
key_512	sha2_384	1207	1			T6	1		T8	3		T9	1
key_512	sha2_256	818	1			T4	2		T6	3		T8	2
key_384	sha2_invalid	487	1			T4	1		T6	1		T8	1
key_384	sha2_none	539	1			T5	1		T6	1		T9	1
key_384	sha2_512	579	1			T6	6		T8	1		T9	1
key_384	sha2_384	591	1			T4	1		T5	1		T6	1
key_384	sha2_256	1006	1			T4	1		T6	1		T8	1
key_256	sha2_invalid	520	1			T4	1		T6	3		T8	1
key_256	sha2_none	526	1			T4	2		T6	3		T8	3
key_256	sha2_512	583	1			T5	1		T6	4		T7	1
key_256	sha2_384	577	1			T7	1		T8	1		T10	1
key_256	sha2_256	636	1			T4	1		T6	1		T7	1
key_128	sha2_invalid	483	1			T27	1		T155	1		T54	1
key_128	sha2_none	520	1			T4	1		T5	1		T6	1
key_128	sha2_512	599	1			T4	1		T6	1		T9	1
key_128	sha2_384	564	1			T4	2		T6	1		T8	1
key_128	sha2_256	617	1			T4	3		T6	2		T9	1