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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.77 95.37 97.17 100.00 88.24 98.25 98.52 99.85


Total test records in report: 651
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T76 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2264545736 Oct 02 07:04:56 PM UTC 24 Oct 02 07:05:01 PM UTC 24 64315799 ps
T532 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.1227197896 Oct 02 07:04:59 PM UTC 24 Oct 02 07:05:01 PM UTC 24 29300726 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.1057104700 Oct 02 07:04:59 PM UTC 24 Oct 02 07:05:01 PM UTC 24 14759494 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.3981722715 Oct 02 07:04:59 PM UTC 24 Oct 02 07:05:01 PM UTC 24 15082473 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3796886732 Oct 02 07:04:56 PM UTC 24 Oct 02 07:05:02 PM UTC 24 93455963 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.3097911520 Oct 02 07:04:56 PM UTC 24 Oct 02 07:05:02 PM UTC 24 231329224 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.1562308389 Oct 02 07:04:58 PM UTC 24 Oct 02 07:05:03 PM UTC 24 146643910 ps
T533 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.3806856339 Oct 02 07:05:01 PM UTC 24 Oct 02 07:05:03 PM UTC 24 20961286 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.2949572782 Oct 02 07:05:01 PM UTC 24 Oct 02 07:05:04 PM UTC 24 33197023 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.1010321870 Oct 02 07:05:01 PM UTC 24 Oct 02 07:05:04 PM UTC 24 35069286 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1866693211 Oct 02 07:05:01 PM UTC 24 Oct 02 07:05:04 PM UTC 24 114257163 ps
T534 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.4109225833 Oct 02 07:04:56 PM UTC 24 Oct 02 07:05:04 PM UTC 24 314518346 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.666059037 Oct 02 07:05:01 PM UTC 24 Oct 02 07:05:05 PM UTC 24 127744335 ps
T535 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.3164615907 Oct 02 07:05:03 PM UTC 24 Oct 02 07:05:05 PM UTC 24 11859652 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2926725966 Oct 02 07:05:01 PM UTC 24 Oct 02 07:05:05 PM UTC 24 73206760 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4028659135 Oct 02 07:05:03 PM UTC 24 Oct 02 07:05:06 PM UTC 24 36250735 ps
T119 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.2470769964 Oct 02 07:05:04 PM UTC 24 Oct 02 07:05:06 PM UTC 24 21112775 ps
T133 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.658527479 Oct 02 07:05:04 PM UTC 24 Oct 02 07:05:06 PM UTC 24 65007214 ps
T536 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.274140414 Oct 02 07:05:03 PM UTC 24 Oct 02 07:05:07 PM UTC 24 86156315 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.2663584060 Oct 02 07:05:03 PM UTC 24 Oct 02 07:05:07 PM UTC 24 301168520 ps
T537 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.542531202 Oct 02 07:05:01 PM UTC 24 Oct 02 07:05:07 PM UTC 24 2802269439 ps
T538 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.1306339763 Oct 02 07:05:03 PM UTC 24 Oct 02 07:05:07 PM UTC 24 410552146 ps
T539 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.284739834 Oct 02 07:05:06 PM UTC 24 Oct 02 07:05:08 PM UTC 24 18120281 ps
T120 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.2717225924 Oct 02 07:05:06 PM UTC 24 Oct 02 07:05:08 PM UTC 24 46825108 ps
T134 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1739913823 Oct 02 07:05:06 PM UTC 24 Oct 02 07:05:09 PM UTC 24 102763262 ps
T540 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.2591648518 Oct 02 07:05:07 PM UTC 24 Oct 02 07:05:10 PM UTC 24 86907424 ps
T541 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.1179928835 Oct 02 07:05:08 PM UTC 24 Oct 02 07:05:10 PM UTC 24 15344970 ps
T121 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.68677933 Oct 02 07:05:08 PM UTC 24 Oct 02 07:05:11 PM UTC 24 19827131 ps
T542 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4206882271 Oct 02 07:05:07 PM UTC 24 Oct 02 07:05:11 PM UTC 24 137512585 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.4113782860 Oct 02 07:05:07 PM UTC 24 Oct 02 07:05:11 PM UTC 24 82723360 ps
T543 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1186550383 Oct 02 07:05:07 PM UTC 24 Oct 02 07:05:11 PM UTC 24 158587337 ps
T544 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.3452906747 Oct 02 07:05:06 PM UTC 24 Oct 02 07:05:12 PM UTC 24 170240391 ps
T545 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3080124585 Oct 02 07:05:09 PM UTC 24 Oct 02 07:05:12 PM UTC 24 55894936 ps
T546 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.217780062 Oct 02 07:05:08 PM UTC 24 Oct 02 07:05:12 PM UTC 24 432645721 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.2240977847 Oct 02 07:04:56 PM UTC 24 Oct 02 07:05:12 PM UTC 24 1220856742 ps
T547 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.3886982144 Oct 02 07:05:11 PM UTC 24 Oct 02 07:05:13 PM UTC 24 11994716 ps
T548 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.169649972 Oct 02 07:05:22 PM UTC 24 Oct 02 07:05:24 PM UTC 24 43743839 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.3110924215 Oct 02 07:05:01 PM UTC 24 Oct 02 07:05:13 PM UTC 24 313494134 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.2654493342 Oct 02 07:05:01 PM UTC 24 Oct 02 07:05:13 PM UTC 24 603986578 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.387195133 Oct 02 07:05:06 PM UTC 24 Oct 02 07:05:13 PM UTC 24 482633239 ps
T549 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.1065222629 Oct 02 07:05:06 PM UTC 24 Oct 02 07:05:13 PM UTC 24 112982403 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.606778588 Oct 02 07:05:11 PM UTC 24 Oct 02 07:05:13 PM UTC 24 326303119 ps
T550 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.2184135158 Oct 02 07:05:10 PM UTC 24 Oct 02 07:05:13 PM UTC 24 1173479406 ps
T551 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.972616051 Oct 02 07:05:13 PM UTC 24 Oct 02 07:05:15 PM UTC 24 45803706 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.407753413 Oct 02 07:05:12 PM UTC 24 Oct 02 07:05:15 PM UTC 24 86770021 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.1348421025 Oct 02 07:05:01 PM UTC 24 Oct 02 07:05:15 PM UTC 24 1862494817 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.2462581682 Oct 02 07:05:06 PM UTC 24 Oct 02 07:05:15 PM UTC 24 543171398 ps
T552 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.607698185 Oct 02 07:05:12 PM UTC 24 Oct 02 07:05:15 PM UTC 24 200019061 ps
T553 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.390145504 Oct 02 07:05:10 PM UTC 24 Oct 02 07:05:15 PM UTC 24 196448705 ps
T554 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.1816964614 Oct 02 07:05:12 PM UTC 24 Oct 02 07:05:16 PM UTC 24 34736761 ps
T555 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.2958950094 Oct 02 07:05:13 PM UTC 24 Oct 02 07:05:16 PM UTC 24 13332534 ps
T556 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.1411463287 Oct 02 07:05:13 PM UTC 24 Oct 02 07:05:16 PM UTC 24 96205952 ps
T557 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.805692097 Oct 02 07:05:13 PM UTC 24 Oct 02 07:05:16 PM UTC 24 33271040 ps
T558 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3399772692 Oct 02 07:05:13 PM UTC 24 Oct 02 07:05:16 PM UTC 24 45749391 ps
T559 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2339034245 Oct 02 07:05:13 PM UTC 24 Oct 02 07:05:16 PM UTC 24 139059872 ps
T560 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.162152905 Oct 02 07:05:13 PM UTC 24 Oct 02 07:05:17 PM UTC 24 796963950 ps
T561 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.361228732 Oct 02 07:05:13 PM UTC 24 Oct 02 07:05:19 PM UTC 24 714966902 ps
T562 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2006856632 Oct 02 07:05:17 PM UTC 24 Oct 02 07:05:20 PM UTC 24 169598365 ps
T563 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3865515909 Oct 02 07:05:17 PM UTC 24 Oct 02 07:05:20 PM UTC 24 73978487 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.2096857850 Oct 02 07:05:01 PM UTC 24 Oct 02 07:05:20 PM UTC 24 3142145774 ps
T564 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.1116980282 Oct 02 07:05:17 PM UTC 24 Oct 02 07:05:20 PM UTC 24 25854656 ps
T565 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.530043130 Oct 02 07:05:17 PM UTC 24 Oct 02 07:05:20 PM UTC 24 111375936 ps
T566 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.2603943924 Oct 02 07:05:19 PM UTC 24 Oct 02 07:05:21 PM UTC 24 100237224 ps
T567 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.3455842769 Oct 02 07:05:19 PM UTC 24 Oct 02 07:05:21 PM UTC 24 43489567 ps
T568 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4039706103 Oct 02 07:05:19 PM UTC 24 Oct 02 07:05:22 PM UTC 24 66842456 ps
T569 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.2288834111 Oct 02 07:05:19 PM UTC 24 Oct 02 07:05:24 PM UTC 24 847629871 ps
T570 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.4063768374 Oct 02 07:05:19 PM UTC 24 Oct 02 07:05:21 PM UTC 24 13837080 ps
T571 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.890508494 Oct 02 07:05:19 PM UTC 24 Oct 02 07:05:21 PM UTC 24 37823308 ps
T572 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.480505574 Oct 02 07:05:19 PM UTC 24 Oct 02 07:05:22 PM UTC 24 46866580 ps
T573 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.2121875489 Oct 02 07:05:19 PM UTC 24 Oct 02 07:05:22 PM UTC 24 58562383 ps
T574 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1002522929 Oct 02 07:05:19 PM UTC 24 Oct 02 07:05:22 PM UTC 24 105873771 ps
T575 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1252647194 Oct 02 07:05:19 PM UTC 24 Oct 02 07:05:22 PM UTC 24 43544200 ps
T576 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.2994744567 Oct 02 07:05:22 PM UTC 24 Oct 02 07:05:24 PM UTC 24 34746307 ps
T577 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1753375242 Oct 02 07:05:19 PM UTC 24 Oct 02 07:05:23 PM UTC 24 26115769 ps
T578 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.612494009 Oct 02 07:05:19 PM UTC 24 Oct 02 07:05:23 PM UTC 24 368731310 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.2724894516 Oct 02 07:05:19 PM UTC 24 Oct 02 07:05:24 PM UTC 24 83485335 ps
T579 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.118018673 Oct 02 07:05:19 PM UTC 24 Oct 02 07:05:25 PM UTC 24 706077429 ps
T580 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.1147292863 Oct 02 07:05:19 PM UTC 24 Oct 02 07:05:25 PM UTC 24 998315531 ps
T581 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.3497757414 Oct 02 07:05:22 PM UTC 24 Oct 02 07:05:25 PM UTC 24 101122872 ps
T582 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.2751154345 Oct 02 07:05:22 PM UTC 24 Oct 02 07:05:26 PM UTC 24 250169213 ps
T583 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.568255905 Oct 02 07:05:22 PM UTC 24 Oct 02 07:05:26 PM UTC 24 217332307 ps
T584 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.2362754856 Oct 02 07:05:22 PM UTC 24 Oct 02 07:05:26 PM UTC 24 59486295 ps
T585 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.440375957 Oct 02 07:05:25 PM UTC 24 Oct 02 07:05:27 PM UTC 24 16605417 ps
T586 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.2887993271 Oct 02 07:05:25 PM UTC 24 Oct 02 07:05:27 PM UTC 24 41094095 ps
T587 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.2758989154 Oct 02 07:05:25 PM UTC 24 Oct 02 07:05:27 PM UTC 24 83816928 ps
T588 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2539698956 Oct 02 07:05:22 PM UTC 24 Oct 02 07:05:27 PM UTC 24 232218207 ps
T589 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.279647358 Oct 02 07:05:26 PM UTC 24 Oct 02 07:05:27 PM UTC 24 24184740 ps
T590 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.2020205086 Oct 02 07:05:25 PM UTC 24 Oct 02 07:05:27 PM UTC 24 29552475 ps
T591 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.486675613 Oct 02 07:05:25 PM UTC 24 Oct 02 07:05:27 PM UTC 24 102177685 ps
T592 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.4081218373 Oct 02 07:05:25 PM UTC 24 Oct 02 07:05:28 PM UTC 24 43228183 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.3418968498 Oct 02 07:05:22 PM UTC 24 Oct 02 07:05:28 PM UTC 24 1710370955 ps
T593 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.2007521273 Oct 02 07:05:25 PM UTC 24 Oct 02 07:05:29 PM UTC 24 106165227 ps
T594 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4262329505 Oct 02 07:05:25 PM UTC 24 Oct 02 07:05:29 PM UTC 24 727502979 ps
T595 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1996780390 Oct 02 07:05:25 PM UTC 24 Oct 02 07:05:29 PM UTC 24 178241439 ps
T596 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.2087737566 Oct 02 07:05:28 PM UTC 24 Oct 02 07:05:30 PM UTC 24 33122217 ps
T597 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.4087264793 Oct 02 07:05:29 PM UTC 24 Oct 02 07:05:31 PM UTC 24 222413843 ps
T598 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.2092813344 Oct 02 07:05:29 PM UTC 24 Oct 02 07:05:31 PM UTC 24 52072985 ps
T599 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.2541502670 Oct 02 07:05:28 PM UTC 24 Oct 02 07:05:31 PM UTC 24 48115390 ps
T600 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1545492104 Oct 02 07:05:29 PM UTC 24 Oct 02 07:05:31 PM UTC 24 40148302 ps
T601 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.3868209647 Oct 02 07:05:29 PM UTC 24 Oct 02 07:05:31 PM UTC 24 14256438 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.3217374579 Oct 02 07:05:25 PM UTC 24 Oct 02 07:05:31 PM UTC 24 890186775 ps
T602 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.1539050111 Oct 02 07:05:25 PM UTC 24 Oct 02 07:05:31 PM UTC 24 1349613470 ps
T603 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.2260583948 Oct 02 07:05:29 PM UTC 24 Oct 02 07:05:31 PM UTC 24 29448157 ps
T604 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2404674367 Oct 02 07:05:29 PM UTC 24 Oct 02 07:05:31 PM UTC 24 22351555 ps
T605 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.2257109299 Oct 02 07:05:25 PM UTC 24 Oct 02 07:05:31 PM UTC 24 279162492 ps
T606 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.3554383134 Oct 02 07:05:29 PM UTC 24 Oct 02 07:05:32 PM UTC 24 52643964 ps
T607 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.2566748552 Oct 02 07:05:29 PM UTC 24 Oct 02 07:05:32 PM UTC 24 65067682 ps
T608 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2828306466 Oct 02 07:05:29 PM UTC 24 Oct 02 07:05:33 PM UTC 24 51918805 ps
T609 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2282022981 Oct 02 07:05:28 PM UTC 24 Oct 02 07:05:33 PM UTC 24 45068632 ps
T610 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2366051929 Oct 02 07:05:29 PM UTC 24 Oct 02 07:05:33 PM UTC 24 142388620 ps
T611 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2186615107 Oct 02 07:05:28 PM UTC 24 Oct 02 07:05:33 PM UTC 24 475631372 ps
T612 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.4205600778 Oct 02 07:05:29 PM UTC 24 Oct 02 07:05:33 PM UTC 24 127327669 ps
T613 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.2503148066 Oct 02 07:05:32 PM UTC 24 Oct 02 07:05:33 PM UTC 24 14160682 ps
T614 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.3962757922 Oct 02 07:05:31 PM UTC 24 Oct 02 07:05:33 PM UTC 24 71388201 ps
T615 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.2123608959 Oct 02 07:05:32 PM UTC 24 Oct 02 07:05:34 PM UTC 24 24982887 ps
T616 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.3698711975 Oct 02 07:05:32 PM UTC 24 Oct 02 07:05:34 PM UTC 24 67441048 ps
T617 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.3694442324 Oct 02 07:05:32 PM UTC 24 Oct 02 07:05:34 PM UTC 24 61951816 ps
T618 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.861774887 Oct 02 07:05:32 PM UTC 24 Oct 02 07:05:34 PM UTC 24 12121871 ps
T619 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.1642056396 Oct 02 07:05:32 PM UTC 24 Oct 02 07:05:34 PM UTC 24 39777716 ps
T620 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.932532644 Oct 02 07:05:32 PM UTC 24 Oct 02 07:05:34 PM UTC 24 31822218 ps
T621 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.1244968204 Oct 02 07:05:32 PM UTC 24 Oct 02 07:05:34 PM UTC 24 15143037 ps
T622 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.870170133 Oct 02 07:05:32 PM UTC 24 Oct 02 07:05:34 PM UTC 24 22081223 ps
T623 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.343607199 Oct 02 07:05:31 PM UTC 24 Oct 02 07:05:35 PM UTC 24 868633244 ps
T624 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.161516618 Oct 02 07:05:29 PM UTC 24 Oct 02 07:05:35 PM UTC 24 744490757 ps
T625 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.3581365936 Oct 02 07:05:28 PM UTC 24 Oct 02 07:05:35 PM UTC 24 533148344 ps
T626 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1435407017 Oct 02 07:05:32 PM UTC 24 Oct 02 07:05:35 PM UTC 24 43053949 ps
T627 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.2537113977 Oct 02 07:05:34 PM UTC 24 Oct 02 07:05:36 PM UTC 24 13048126 ps
T628 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.1501594324 Oct 02 07:05:34 PM UTC 24 Oct 02 07:05:36 PM UTC 24 28756831 ps
T629 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.664855455 Oct 02 07:05:34 PM UTC 24 Oct 02 07:05:36 PM UTC 24 29793379 ps
T630 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.324052986 Oct 02 07:05:34 PM UTC 24 Oct 02 07:05:36 PM UTC 24 54763018 ps
T631 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.2466436630 Oct 02 07:05:34 PM UTC 24 Oct 02 07:05:36 PM UTC 24 41069432 ps
T632 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.902877332 Oct 02 07:05:34 PM UTC 24 Oct 02 07:05:36 PM UTC 24 83980810 ps
T633 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.1838565892 Oct 02 07:05:34 PM UTC 24 Oct 02 07:05:36 PM UTC 24 26228010 ps
T634 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.2781858616 Oct 02 07:05:34 PM UTC 24 Oct 02 07:05:36 PM UTC 24 28457357 ps
T635 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.3906879048 Oct 02 07:05:34 PM UTC 24 Oct 02 07:05:36 PM UTC 24 11511915 ps
T636 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.3111646583 Oct 02 07:05:34 PM UTC 24 Oct 02 07:05:36 PM UTC 24 26433096 ps
T637 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.1065321656 Oct 02 07:05:34 PM UTC 24 Oct 02 07:05:36 PM UTC 24 31848366 ps
T638 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.3592249034 Oct 02 07:05:35 PM UTC 24 Oct 02 07:05:36 PM UTC 24 20625050 ps
T639 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.3972670161 Oct 02 07:05:35 PM UTC 24 Oct 02 07:05:36 PM UTC 24 17834610 ps
T640 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.2028263300 Oct 02 07:05:35 PM UTC 24 Oct 02 07:05:36 PM UTC 24 15845672 ps
T641 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.1628503377 Oct 02 07:05:35 PM UTC 24 Oct 02 07:05:36 PM UTC 24 11100959 ps
T642 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.3114640603 Oct 02 07:05:35 PM UTC 24 Oct 02 07:05:36 PM UTC 24 40588141 ps
T643 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.3449193712 Oct 02 07:05:35 PM UTC 24 Oct 02 07:05:37 PM UTC 24 13225975 ps
T644 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.1280724313 Oct 02 07:05:35 PM UTC 24 Oct 02 07:05:37 PM UTC 24 18580597 ps
T645 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.1739463324 Oct 02 07:05:35 PM UTC 24 Oct 02 07:05:37 PM UTC 24 40154827 ps
T646 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.1142181558 Oct 02 07:05:38 PM UTC 24 Oct 02 07:05:39 PM UTC 24 15761729 ps
T647 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.1660659099 Oct 02 07:05:37 PM UTC 24 Oct 02 07:05:39 PM UTC 24 11828249 ps
T648 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.667159854 Oct 02 07:05:22 PM UTC 24 Oct 02 07:13:17 PM UTC 24 55427708035 ps
T649 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4116673384 Oct 02 07:05:12 PM UTC 24 Oct 02 07:14:18 PM UTC 24 38887498963 ps
T650 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.171830953 Oct 02 07:05:06 PM UTC 24 Oct 02 07:21:42 PM UTC 24 360652514692 ps
T651 /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2672202915 Oct 02 07:05:25 PM UTC 24 Oct 02 07:24:15 PM UTC 24 775490109246 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/0.hmac_smoke.2664157330
Short name T4
Test name
Test status
Simulation time 787843889 ps
CPU time 8.41 seconds
Started Oct 02 07:44:05 PM UTC 24
Finished Oct 02 07:44:14 PM UTC 24
Peak memory 210380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664157330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2664157330
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/0.hmac_stress_all_with_rand_reset.1947923051
Short name T18
Test name
Test status
Simulation time 8712803702 ps
CPU time 100.13 seconds
Started Oct 02 07:44:05 PM UTC 24
Finished Oct 02 07:45:48 PM UTC 24
Peak memory 219080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19479230
51 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.1947923051
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/1.hmac_back_pressure.3171192906
Short name T9
Test name
Test status
Simulation time 532493167 ps
CPU time 32.85 seconds
Started Oct 02 07:44:06 PM UTC 24
Finished Oct 02 07:44:40 PM UTC 24
Peak memory 210336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171192906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3171192906
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/18.hmac_stress_all.695143862
Short name T33
Test name
Test status
Simulation time 80486693098 ps
CPU time 1095.35 seconds
Started Oct 02 07:52:40 PM UTC 24
Finished Oct 02 08:11:10 PM UTC 24
Peak memory 210516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695143862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.695143862
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/18.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/3.hmac_smoke.2562076433
Short name T156
Test name
Test status
Simulation time 256301966 ps
CPU time 15.8 seconds
Started Oct 02 07:44:51 PM UTC 24
Finished Oct 02 07:45:08 PM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562076433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2562076433
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.3097911520
Short name T69
Test name
Test status
Simulation time 231329224 ps
CPU time 4.67 seconds
Started Oct 02 07:04:56 PM UTC 24
Finished Oct 02 07:05:02 PM UTC 24
Peak memory 206848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097911520 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3097911520
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/0.hmac_sec_cm.1001965884
Short name T2
Test name
Test status
Simulation time 533761150 ps
CPU time 1.05 seconds
Started Oct 02 07:44:05 PM UTC 24
Finished Oct 02 07:44:08 PM UTC 24
Peak memory 238204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001965884 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1001965884
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/6.hmac_wipe_secret.2800271842
Short name T51
Test name
Test status
Simulation time 1622551724 ps
CPU time 90.2 seconds
Started Oct 02 07:46:24 PM UTC 24
Finished Oct 02 07:47:57 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800271842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2800271842
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/6.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/5.hmac_error.3430326892
Short name T63
Test name
Test status
Simulation time 10464928571 ps
CPU time 172.89 seconds
Started Oct 02 07:46:01 PM UTC 24
Finished Oct 02 07:48:57 PM UTC 24
Peak memory 210432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430326892 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3430326892
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/5.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/4.hmac_burst_wr.4121920553
Short name T16
Test name
Test status
Simulation time 1026935410 ps
CPU time 52.06 seconds
Started Oct 02 07:45:23 PM UTC 24
Finished Oct 02 07:46:17 PM UTC 24
Peak memory 210476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121920553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.4121920553
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.3110924215
Short name T123
Test name
Test status
Simulation time 313494134 ps
CPU time 10.4 seconds
Started Oct 02 07:05:01 PM UTC 24
Finished Oct 02 07:05:13 PM UTC 24
Peak memory 206856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110924215 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3110924215
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/7.hmac_stress_all.495731102
Short name T168
Test name
Test status
Simulation time 24972907714 ps
CPU time 371.22 seconds
Started Oct 02 07:46:56 PM UTC 24
Finished Oct 02 07:53:13 PM UTC 24
Peak memory 219028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495731102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.495731102
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/7.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/12.hmac_back_pressure.1632176767
Short name T23
Test name
Test status
Simulation time 8928785633 ps
CPU time 64.16 seconds
Started Oct 02 07:49:02 PM UTC 24
Finished Oct 02 07:50:08 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632176767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1632176767
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/12.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/13.hmac_stress_all.715385319
Short name T142
Test name
Test status
Simulation time 14054319312 ps
CPU time 906.24 seconds
Started Oct 02 07:49:28 PM UTC 24
Finished Oct 02 08:04:46 PM UTC 24
Peak memory 226908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715385319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.715385319
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/13.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/41.hmac_stress_all.19137019
Short name T450
Test name
Test status
Simulation time 9150712078 ps
CPU time 343.87 seconds
Started Oct 02 08:09:56 PM UTC 24
Finished Oct 02 08:15:45 PM UTC 24
Peak memory 638348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19137019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.19137019
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/41.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/0.hmac_error.2819504751
Short name T27
Test name
Test status
Simulation time 16313082225 ps
CPU time 46.76 seconds
Started Oct 02 07:44:05 PM UTC 24
Finished Oct 02 07:44:53 PM UTC 24
Peak memory 210484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819504751 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2819504751
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/7.hmac_stress_all_with_rand_reset.2788041708
Short name T20
Test name
Test status
Simulation time 7335028628 ps
CPU time 212.25 seconds
Started Oct 02 07:47:15 PM UTC 24
Finished Oct 02 07:50:51 PM UTC 24
Peak memory 394572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27880417
08 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.2788041708
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.2663584060
Short name T148
Test name
Test status
Simulation time 301168520 ps
CPU time 3.19 seconds
Started Oct 02 07:05:03 PM UTC 24
Finished Oct 02 07:05:07 PM UTC 24
Peak memory 206784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663584060 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2663584060
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/0.hmac_alert_test.2494091842
Short name T1
Test name
Test status
Simulation time 52871808 ps
CPU time 0.58 seconds
Started Oct 02 07:44:06 PM UTC 24
Finished Oct 02 07:44:07 PM UTC 24
Peak memory 207396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494091842 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2494091842
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/13.hmac_burst_wr.3647940572
Short name T57
Test name
Test status
Simulation time 4106747411 ps
CPU time 66.64 seconds
Started Oct 02 07:49:22 PM UTC 24
Finished Oct 02 07:50:31 PM UTC 24
Peak memory 210800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647940572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3647940572
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/13.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_same_csr_outstanding.4260878249
Short name T130
Test name
Test status
Simulation time 1608222083 ps
CPU time 3.05 seconds
Started Oct 02 07:04:56 PM UTC 24
Finished Oct 02 07:05:00 PM UTC 24
Peak memory 206520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260878249 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_outstanding.4260878249
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.3217374579
Short name T152
Test name
Test status
Simulation time 890186775 ps
CPU time 4.72 seconds
Started Oct 02 07:05:25 PM UTC 24
Finished Oct 02 07:05:31 PM UTC 24
Peak memory 207176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217374579 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3217374579
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/16.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/1.hmac_burst_wr.700256931
Short name T13
Test name
Test status
Simulation time 9812569838 ps
CPU time 56.23 seconds
Started Oct 02 07:44:06 PM UTC 24
Finished Oct 02 07:45:04 PM UTC 24
Peak memory 219272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700256931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.700256931
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.2051125050
Short name T528
Test name
Test status
Simulation time 157782690 ps
CPU time 3.15 seconds
Started Oct 02 07:04:52 PM UTC 24
Finished Oct 02 07:04:56 PM UTC 24
Peak memory 206860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051125050 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2051125050
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.443207725
Short name T530
Test name
Test status
Simulation time 1965607184 ps
CPU time 5.72 seconds
Started Oct 02 07:04:52 PM UTC 24
Finished Oct 02 07:04:58 PM UTC 24
Peak memory 206648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443207725 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.443207725
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_hw_reset.3758788275
Short name T527
Test name
Test status
Simulation time 66184255 ps
CPU time 1.16 seconds
Started Oct 02 07:04:52 PM UTC 24
Finished Oct 02 07:04:54 PM UTC 24
Peak memory 205020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758788275 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3758788275
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3796886732
Short name T77
Test name
Test status
Simulation time 93455963 ps
CPU time 4.66 seconds
Started Oct 02 07:04:56 PM UTC 24
Finished Oct 02 07:05:02 PM UTC 24
Peak memory 215004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3796886732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_r
eset.3796886732
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_rw.675874118
Short name T526
Test name
Test status
Simulation time 27945867 ps
CPU time 1.12 seconds
Started Oct 02 07:04:52 PM UTC 24
Finished Oct 02 07:04:54 PM UTC 24
Peak memory 206100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675874118 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.675874118
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_intr_test.330151999
Short name T525
Test name
Test status
Simulation time 18072466 ps
CPU time 0.95 seconds
Started Oct 02 07:04:49 PM UTC 24
Finished Oct 02 07:04:51 PM UTC 24
Peak memory 203972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330151999 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.330151999
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_errors.1994037327
Short name T72
Test name
Test status
Simulation time 290591840 ps
CPU time 3.29 seconds
Started Oct 02 07:04:48 PM UTC 24
Finished Oct 02 07:04:52 PM UTC 24
Peak memory 206844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994037327 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1994037327
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_intg_err.3291473757
Short name T68
Test name
Test status
Simulation time 86127402 ps
CPU time 2.7 seconds
Started Oct 02 07:04:48 PM UTC 24
Finished Oct 02 07:04:52 PM UTC 24
Peak memory 207124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291473757 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3291473757
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.4109225833
Short name T534
Test name
Test status
Simulation time 314518346 ps
CPU time 6.57 seconds
Started Oct 02 07:04:56 PM UTC 24
Finished Oct 02 07:05:04 PM UTC 24
Peak memory 207112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109225833 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.4109225833
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.2240977847
Short name T122
Test name
Test status
Simulation time 1220856742 ps
CPU time 14.38 seconds
Started Oct 02 07:04:56 PM UTC 24
Finished Oct 02 07:05:12 PM UTC 24
Peak memory 207124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240977847 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2240977847
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.2505801910
Short name T531
Test name
Test status
Simulation time 115400270 ps
CPU time 1.36 seconds
Started Oct 02 07:04:56 PM UTC 24
Finished Oct 02 07:04:59 PM UTC 24
Peak memory 206044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505801910 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2505801910
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2264545736
Short name T76
Test name
Test status
Simulation time 64315799 ps
CPU time 2.63 seconds
Started Oct 02 07:04:56 PM UTC 24
Finished Oct 02 07:05:01 PM UTC 24
Peak memory 215304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2264545736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_r
eset.2264545736
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.2990911201
Short name T114
Test name
Test status
Simulation time 96078375 ps
CPU time 1.3 seconds
Started Oct 02 07:04:56 PM UTC 24
Finished Oct 02 07:04:59 PM UTC 24
Peak memory 206520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990911201 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2990911201
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_intr_test.1119041872
Short name T529
Test name
Test status
Simulation time 49115688 ps
CPU time 0.95 seconds
Started Oct 02 07:04:56 PM UTC 24
Finished Oct 02 07:04:58 PM UTC 24
Peak memory 203048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119041872 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1119041872
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3101291440
Short name T129
Test name
Test status
Simulation time 273926260 ps
CPU time 2 seconds
Started Oct 02 07:04:56 PM UTC 24
Finished Oct 02 07:05:00 PM UTC 24
Peak memory 205996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101291440 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_outstanding.3101291440
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.190058842
Short name T74
Test name
Test status
Simulation time 210514843 ps
CPU time 2.42 seconds
Started Oct 02 07:04:56 PM UTC 24
Finished Oct 02 07:05:00 PM UTC 24
Peak memory 206600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190058842 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.190058842
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1002522929
Short name T574
Test name
Test status
Simulation time 105873771 ps
CPU time 1.95 seconds
Started Oct 02 07:05:19 PM UTC 24
Finished Oct 02 07:05:22 PM UTC 24
Peak memory 206056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1002522929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_
reset.1002522929
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.3455842769
Short name T567
Test name
Test status
Simulation time 43489567 ps
CPU time 0.79 seconds
Started Oct 02 07:05:19 PM UTC 24
Finished Oct 02 07:05:21 PM UTC 24
Peak memory 206252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455842769 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3455842769
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/10.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.2603943924
Short name T566
Test name
Test status
Simulation time 100237224 ps
CPU time 0.73 seconds
Started Oct 02 07:05:19 PM UTC 24
Finished Oct 02 07:05:21 PM UTC 24
Peak memory 202396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603943924 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2603943924
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/10.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4039706103
Short name T568
Test name
Test status
Simulation time 66842456 ps
CPU time 2.09 seconds
Started Oct 02 07:05:19 PM UTC 24
Finished Oct 02 07:05:22 PM UTC 24
Peak memory 206784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039706103 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr_outstanding.4039706103
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/10.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.1116980282
Short name T564
Test name
Test status
Simulation time 25854656 ps
CPU time 1.67 seconds
Started Oct 02 07:05:17 PM UTC 24
Finished Oct 02 07:05:20 PM UTC 24
Peak memory 205932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116980282 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1116980282
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/10.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.530043130
Short name T565
Test name
Test status
Simulation time 111375936 ps
CPU time 1.95 seconds
Started Oct 02 07:05:17 PM UTC 24
Finished Oct 02 07:05:20 PM UTC 24
Peak memory 205896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530043130 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.530043130
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/10.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1753375242
Short name T577
Test name
Test status
Simulation time 26115769 ps
CPU time 2.14 seconds
Started Oct 02 07:05:19 PM UTC 24
Finished Oct 02 07:05:23 PM UTC 24
Peak memory 206840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1753375242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_
reset.1753375242
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.2121875489
Short name T573
Test name
Test status
Simulation time 58562383 ps
CPU time 1.51 seconds
Started Oct 02 07:05:19 PM UTC 24
Finished Oct 02 07:05:22 PM UTC 24
Peak memory 205992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121875489 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2121875489
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/11.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.4063768374
Short name T570
Test name
Test status
Simulation time 13837080 ps
CPU time 0.77 seconds
Started Oct 02 07:05:19 PM UTC 24
Finished Oct 02 07:05:21 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063768374 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.4063768374
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/11.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.612494009
Short name T578
Test name
Test status
Simulation time 368731310 ps
CPU time 2.35 seconds
Started Oct 02 07:05:19 PM UTC 24
Finished Oct 02 07:05:23 PM UTC 24
Peak memory 206848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612494009 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr_outstanding.612494009
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/11.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.118018673
Short name T579
Test name
Test status
Simulation time 706077429 ps
CPU time 4.3 seconds
Started Oct 02 07:05:19 PM UTC 24
Finished Oct 02 07:05:25 PM UTC 24
Peak memory 206924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118018673 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.118018673
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/11.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.1147292863
Short name T580
Test name
Test status
Simulation time 998315531 ps
CPU time 4.6 seconds
Started Oct 02 07:05:19 PM UTC 24
Finished Oct 02 07:05:25 PM UTC 24
Peak memory 206784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147292863 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1147292863
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/11.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2539698956
Short name T588
Test name
Test status
Simulation time 232218207 ps
CPU time 4.47 seconds
Started Oct 02 07:05:22 PM UTC 24
Finished Oct 02 07:05:27 PM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2539698956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_
reset.2539698956
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.480505574
Short name T572
Test name
Test status
Simulation time 46866580 ps
CPU time 0.93 seconds
Started Oct 02 07:05:19 PM UTC 24
Finished Oct 02 07:05:22 PM UTC 24
Peak memory 205104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480505574 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.480505574
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/12.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.890508494
Short name T571
Test name
Test status
Simulation time 37823308 ps
CPU time 0.85 seconds
Started Oct 02 07:05:19 PM UTC 24
Finished Oct 02 07:05:21 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890508494 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.890508494
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/12.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1252647194
Short name T575
Test name
Test status
Simulation time 43544200 ps
CPU time 1.68 seconds
Started Oct 02 07:05:19 PM UTC 24
Finished Oct 02 07:05:22 PM UTC 24
Peak memory 205952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252647194 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr_outstanding.1252647194
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/12.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.2288834111
Short name T569
Test name
Test status
Simulation time 847629871 ps
CPU time 3.59 seconds
Started Oct 02 07:05:19 PM UTC 24
Finished Oct 02 07:05:24 PM UTC 24
Peak memory 206840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288834111 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2288834111
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/12.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.2724894516
Short name T147
Test name
Test status
Simulation time 83485335 ps
CPU time 3.15 seconds
Started Oct 02 07:05:19 PM UTC 24
Finished Oct 02 07:05:24 PM UTC 24
Peak memory 206996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724894516 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2724894516
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/12.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.667159854
Short name T648
Test name
Test status
Simulation time 55427708035 ps
CPU time 469.26 seconds
Started Oct 02 07:05:22 PM UTC 24
Finished Oct 02 07:13:17 PM UTC 24
Peak memory 221224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=667159854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_r
eset.667159854
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.2994744567
Short name T576
Test name
Test status
Simulation time 34746307 ps
CPU time 1.11 seconds
Started Oct 02 07:05:22 PM UTC 24
Finished Oct 02 07:05:24 PM UTC 24
Peak memory 206044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994744567 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2994744567
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/13.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.169649972
Short name T548
Test name
Test status
Simulation time 43743839 ps
CPU time 0.84 seconds
Started Oct 02 07:05:22 PM UTC 24
Finished Oct 02 07:05:24 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169649972 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.169649972
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/13.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.568255905
Short name T583
Test name
Test status
Simulation time 217332307 ps
CPU time 3.15 seconds
Started Oct 02 07:05:22 PM UTC 24
Finished Oct 02 07:05:26 PM UTC 24
Peak memory 206832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568255905 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_outstanding.568255905
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/13.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.3497757414
Short name T581
Test name
Test status
Simulation time 101122872 ps
CPU time 2.85 seconds
Started Oct 02 07:05:22 PM UTC 24
Finished Oct 02 07:05:25 PM UTC 24
Peak memory 207168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497757414 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3497757414
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/13.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.2751154345
Short name T582
Test name
Test status
Simulation time 250169213 ps
CPU time 3.09 seconds
Started Oct 02 07:05:22 PM UTC 24
Finished Oct 02 07:05:26 PM UTC 24
Peak memory 207180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751154345 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2751154345
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/13.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2672202915
Short name T651
Test name
Test status
Simulation time 775490109246 ps
CPU time 1115.9 seconds
Started Oct 02 07:05:25 PM UTC 24
Finished Oct 02 07:24:15 PM UTC 24
Peak memory 237276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2672202915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_
reset.2672202915
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.2887993271
Short name T586
Test name
Test status
Simulation time 41094095 ps
CPU time 0.95 seconds
Started Oct 02 07:05:25 PM UTC 24
Finished Oct 02 07:05:27 PM UTC 24
Peak memory 205992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887993271 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2887993271
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/14.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.440375957
Short name T585
Test name
Test status
Simulation time 16605417 ps
CPU time 0.91 seconds
Started Oct 02 07:05:25 PM UTC 24
Finished Oct 02 07:05:27 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440375957 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.440375957
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/14.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.4081218373
Short name T592
Test name
Test status
Simulation time 43228183 ps
CPU time 1.73 seconds
Started Oct 02 07:05:25 PM UTC 24
Finished Oct 02 07:05:28 PM UTC 24
Peak memory 205976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081218373 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr_outstanding.4081218373
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/14.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.2362754856
Short name T584
Test name
Test status
Simulation time 59486295 ps
CPU time 3.21 seconds
Started Oct 02 07:05:22 PM UTC 24
Finished Oct 02 07:05:26 PM UTC 24
Peak memory 206840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362754856 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2362754856
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/14.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.3418968498
Short name T153
Test name
Test status
Simulation time 1710370955 ps
CPU time 4.68 seconds
Started Oct 02 07:05:22 PM UTC 24
Finished Oct 02 07:05:28 PM UTC 24
Peak memory 206876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418968498 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3418968498
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/14.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1996780390
Short name T595
Test name
Test status
Simulation time 178241439 ps
CPU time 3.16 seconds
Started Oct 02 07:05:25 PM UTC 24
Finished Oct 02 07:05:29 PM UTC 24
Peak memory 215052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1996780390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_
reset.1996780390
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.486675613
Short name T591
Test name
Test status
Simulation time 102177685 ps
CPU time 1.19 seconds
Started Oct 02 07:05:25 PM UTC 24
Finished Oct 02 07:05:27 PM UTC 24
Peak memory 205868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486675613 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.486675613
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/15.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.2758989154
Short name T587
Test name
Test status
Simulation time 83816928 ps
CPU time 0.81 seconds
Started Oct 02 07:05:25 PM UTC 24
Finished Oct 02 07:05:27 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758989154 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2758989154
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/15.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4262329505
Short name T594
Test name
Test status
Simulation time 727502979 ps
CPU time 3 seconds
Started Oct 02 07:05:25 PM UTC 24
Finished Oct 02 07:05:29 PM UTC 24
Peak memory 206856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262329505 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr_outstanding.4262329505
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/15.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.1539050111
Short name T602
Test name
Test status
Simulation time 1349613470 ps
CPU time 5.08 seconds
Started Oct 02 07:05:25 PM UTC 24
Finished Oct 02 07:05:31 PM UTC 24
Peak memory 207064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539050111 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1539050111
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/15.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.2257109299
Short name T605
Test name
Test status
Simulation time 279162492 ps
CPU time 5.3 seconds
Started Oct 02 07:05:25 PM UTC 24
Finished Oct 02 07:05:31 PM UTC 24
Peak memory 206856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257109299 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2257109299
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/15.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2282022981
Short name T609
Test name
Test status
Simulation time 45068632 ps
CPU time 3.4 seconds
Started Oct 02 07:05:28 PM UTC 24
Finished Oct 02 07:05:33 PM UTC 24
Peak memory 215044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2282022981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_
reset.2282022981
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.279647358
Short name T589
Test name
Test status
Simulation time 24184740 ps
CPU time 0.79 seconds
Started Oct 02 07:05:26 PM UTC 24
Finished Oct 02 07:05:27 PM UTC 24
Peak memory 205868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279647358 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.279647358
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/16.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.2020205086
Short name T590
Test name
Test status
Simulation time 29552475 ps
CPU time 0.79 seconds
Started Oct 02 07:05:25 PM UTC 24
Finished Oct 02 07:05:27 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020205086 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2020205086
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/16.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2186615107
Short name T611
Test name
Test status
Simulation time 475631372 ps
CPU time 2.75 seconds
Started Oct 02 07:05:28 PM UTC 24
Finished Oct 02 07:05:33 PM UTC 24
Peak memory 206776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186615107 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr_outstanding.2186615107
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/16.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.2007521273
Short name T593
Test name
Test status
Simulation time 106165227 ps
CPU time 2.79 seconds
Started Oct 02 07:05:25 PM UTC 24
Finished Oct 02 07:05:29 PM UTC 24
Peak memory 206916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007521273 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2007521273
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/16.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2366051929
Short name T610
Test name
Test status
Simulation time 142388620 ps
CPU time 3.33 seconds
Started Oct 02 07:05:29 PM UTC 24
Finished Oct 02 07:05:33 PM UTC 24
Peak memory 215132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2366051929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_
reset.2366051929
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.2092813344
Short name T598
Test name
Test status
Simulation time 52072985 ps
CPU time 1.32 seconds
Started Oct 02 07:05:29 PM UTC 24
Finished Oct 02 07:05:31 PM UTC 24
Peak memory 205992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092813344 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2092813344
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/17.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.2087737566
Short name T596
Test name
Test status
Simulation time 33122217 ps
CPU time 0.87 seconds
Started Oct 02 07:05:28 PM UTC 24
Finished Oct 02 07:05:30 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087737566 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2087737566
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/17.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1545492104
Short name T600
Test name
Test status
Simulation time 40148302 ps
CPU time 1.44 seconds
Started Oct 02 07:05:29 PM UTC 24
Finished Oct 02 07:05:31 PM UTC 24
Peak memory 206004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545492104 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr_outstanding.1545492104
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/17.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.2541502670
Short name T599
Test name
Test status
Simulation time 48115390 ps
CPU time 1.63 seconds
Started Oct 02 07:05:28 PM UTC 24
Finished Oct 02 07:05:31 PM UTC 24
Peak memory 205880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541502670 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2541502670
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/17.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.3581365936
Short name T625
Test name
Test status
Simulation time 533148344 ps
CPU time 5.61 seconds
Started Oct 02 07:05:28 PM UTC 24
Finished Oct 02 07:05:35 PM UTC 24
Peak memory 206852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581365936 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3581365936
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/17.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2404674367
Short name T604
Test name
Test status
Simulation time 22351555 ps
CPU time 1.33 seconds
Started Oct 02 07:05:29 PM UTC 24
Finished Oct 02 07:05:31 PM UTC 24
Peak memory 206048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2404674367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_
reset.2404674367
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.2260583948
Short name T603
Test name
Test status
Simulation time 29448157 ps
CPU time 1.42 seconds
Started Oct 02 07:05:29 PM UTC 24
Finished Oct 02 07:05:31 PM UTC 24
Peak memory 205992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260583948 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2260583948
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/18.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.4087264793
Short name T597
Test name
Test status
Simulation time 222413843 ps
CPU time 0.88 seconds
Started Oct 02 07:05:29 PM UTC 24
Finished Oct 02 07:05:31 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087264793 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.4087264793
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/18.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2828306466
Short name T608
Test name
Test status
Simulation time 51918805 ps
CPU time 2.74 seconds
Started Oct 02 07:05:29 PM UTC 24
Finished Oct 02 07:05:33 PM UTC 24
Peak memory 206784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828306466 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr_outstanding.2828306466
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/18.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.4205600778
Short name T612
Test name
Test status
Simulation time 127327669 ps
CPU time 3.49 seconds
Started Oct 02 07:05:29 PM UTC 24
Finished Oct 02 07:05:33 PM UTC 24
Peak memory 206848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205600778 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.4205600778
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/18.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.3554383134
Short name T606
Test name
Test status
Simulation time 52643964 ps
CPU time 1.96 seconds
Started Oct 02 07:05:29 PM UTC 24
Finished Oct 02 07:05:32 PM UTC 24
Peak memory 205876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554383134 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3554383134
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/18.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1435407017
Short name T626
Test name
Test status
Simulation time 43053949 ps
CPU time 2.68 seconds
Started Oct 02 07:05:32 PM UTC 24
Finished Oct 02 07:05:35 PM UTC 24
Peak memory 206928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1435407017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_
reset.1435407017
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.3962757922
Short name T614
Test name
Test status
Simulation time 71388201 ps
CPU time 1.06 seconds
Started Oct 02 07:05:31 PM UTC 24
Finished Oct 02 07:05:33 PM UTC 24
Peak memory 206044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962757922 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3962757922
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/19.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.3868209647
Short name T601
Test name
Test status
Simulation time 14256438 ps
CPU time 0.9 seconds
Started Oct 02 07:05:29 PM UTC 24
Finished Oct 02 07:05:31 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868209647 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3868209647
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/19.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.343607199
Short name T623
Test name
Test status
Simulation time 868633244 ps
CPU time 2.24 seconds
Started Oct 02 07:05:31 PM UTC 24
Finished Oct 02 07:05:35 PM UTC 24
Peak memory 207100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343607199 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_outstanding.343607199
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/19.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.2566748552
Short name T607
Test name
Test status
Simulation time 65067682 ps
CPU time 1.9 seconds
Started Oct 02 07:05:29 PM UTC 24
Finished Oct 02 07:05:32 PM UTC 24
Peak memory 205876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566748552 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2566748552
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/19.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.161516618
Short name T624
Test name
Test status
Simulation time 744490757 ps
CPU time 4.76 seconds
Started Oct 02 07:05:29 PM UTC 24
Finished Oct 02 07:05:35 PM UTC 24
Peak memory 207112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161516618 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.161516618
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/19.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.1348421025
Short name T126
Test name
Test status
Simulation time 1862494817 ps
CPU time 12.82 seconds
Started Oct 02 07:05:01 PM UTC 24
Finished Oct 02 07:05:15 PM UTC 24
Peak memory 207188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348421025 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1348421025
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.1057104700
Short name T115
Test name
Test status
Simulation time 14759494 ps
CPU time 1.14 seconds
Started Oct 02 07:04:59 PM UTC 24
Finished Oct 02 07:05:01 PM UTC 24
Peak memory 205452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057104700 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1057104700
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1866693211
Short name T97
Test name
Test status
Simulation time 114257163 ps
CPU time 2.19 seconds
Started Oct 02 07:05:01 PM UTC 24
Finished Oct 02 07:05:04 PM UTC 24
Peak memory 207172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1866693211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_r
eset.1866693211
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.3981722715
Short name T116
Test name
Test status
Simulation time 15082473 ps
CPU time 1.09 seconds
Started Oct 02 07:04:59 PM UTC 24
Finished Oct 02 07:05:01 PM UTC 24
Peak memory 205736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981722715 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3981722715
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.1227197896
Short name T532
Test name
Test status
Simulation time 29300726 ps
CPU time 0.95 seconds
Started Oct 02 07:04:59 PM UTC 24
Finished Oct 02 07:05:01 PM UTC 24
Peak memory 203048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227197896 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1227197896
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2926725966
Short name T131
Test name
Test status
Simulation time 73206760 ps
CPU time 3.06 seconds
Started Oct 02 07:05:01 PM UTC 24
Finished Oct 02 07:05:05 PM UTC 24
Peak memory 207116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926725966 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_outstanding.2926725966
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.2049055285
Short name T75
Test name
Test status
Simulation time 272507554 ps
CPU time 2.44 seconds
Started Oct 02 07:04:57 PM UTC 24
Finished Oct 02 07:05:00 PM UTC 24
Peak memory 206856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049055285 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2049055285
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.1562308389
Short name T70
Test name
Test status
Simulation time 146643910 ps
CPU time 2.79 seconds
Started Oct 02 07:04:58 PM UTC 24
Finished Oct 02 07:05:03 PM UTC 24
Peak memory 207112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562308389 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.1562308389
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.2503148066
Short name T613
Test name
Test status
Simulation time 14160682 ps
CPU time 0.77 seconds
Started Oct 02 07:05:32 PM UTC 24
Finished Oct 02 07:05:33 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503148066 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2503148066
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/20.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.2123608959
Short name T615
Test name
Test status
Simulation time 24982887 ps
CPU time 0.95 seconds
Started Oct 02 07:05:32 PM UTC 24
Finished Oct 02 07:05:34 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123608959 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2123608959
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/21.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.1642056396
Short name T619
Test name
Test status
Simulation time 39777716 ps
CPU time 0.93 seconds
Started Oct 02 07:05:32 PM UTC 24
Finished Oct 02 07:05:34 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642056396 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1642056396
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/22.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.861774887
Short name T618
Test name
Test status
Simulation time 12121871 ps
CPU time 0.88 seconds
Started Oct 02 07:05:32 PM UTC 24
Finished Oct 02 07:05:34 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861774887 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.861774887
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/23.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.932532644
Short name T620
Test name
Test status
Simulation time 31822218 ps
CPU time 0.98 seconds
Started Oct 02 07:05:32 PM UTC 24
Finished Oct 02 07:05:34 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932532644 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.932532644
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/24.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.1244968204
Short name T621
Test name
Test status
Simulation time 15143037 ps
CPU time 0.9 seconds
Started Oct 02 07:05:32 PM UTC 24
Finished Oct 02 07:05:34 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244968204 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1244968204
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/25.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.870170133
Short name T622
Test name
Test status
Simulation time 22081223 ps
CPU time 0.92 seconds
Started Oct 02 07:05:32 PM UTC 24
Finished Oct 02 07:05:34 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870170133 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.870170133
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/26.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.3698711975
Short name T616
Test name
Test status
Simulation time 67441048 ps
CPU time 0.7 seconds
Started Oct 02 07:05:32 PM UTC 24
Finished Oct 02 07:05:34 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698711975 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3698711975
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/27.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.3694442324
Short name T617
Test name
Test status
Simulation time 61951816 ps
CPU time 0.72 seconds
Started Oct 02 07:05:32 PM UTC 24
Finished Oct 02 07:05:34 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694442324 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3694442324
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/28.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.2537113977
Short name T627
Test name
Test status
Simulation time 13048126 ps
CPU time 0.71 seconds
Started Oct 02 07:05:34 PM UTC 24
Finished Oct 02 07:05:36 PM UTC 24
Peak memory 202516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537113977 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2537113977
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/29.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.2654493342
Short name T124
Test name
Test status
Simulation time 603986578 ps
CPU time 9.84 seconds
Started Oct 02 07:05:01 PM UTC 24
Finished Oct 02 07:05:13 PM UTC 24
Peak memory 206868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654493342 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2654493342
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.2096857850
Short name T128
Test name
Test status
Simulation time 3142145774 ps
CPU time 17.25 seconds
Started Oct 02 07:05:01 PM UTC 24
Finished Oct 02 07:05:20 PM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096857850 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2096857850
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.2949572782
Short name T117
Test name
Test status
Simulation time 33197023 ps
CPU time 1.23 seconds
Started Oct 02 07:05:01 PM UTC 24
Finished Oct 02 07:05:04 PM UTC 24
Peak memory 206196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949572782 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2949572782
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.274140414
Short name T536
Test name
Test status
Simulation time 86156315 ps
CPU time 2.11 seconds
Started Oct 02 07:05:03 PM UTC 24
Finished Oct 02 07:05:07 PM UTC 24
Peak memory 207160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=274140414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_re
set.274140414
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.1010321870
Short name T118
Test name
Test status
Simulation time 35069286 ps
CPU time 1.21 seconds
Started Oct 02 07:05:01 PM UTC 24
Finished Oct 02 07:05:04 PM UTC 24
Peak memory 205988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010321870 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1010321870
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.3806856339
Short name T533
Test name
Test status
Simulation time 20961286 ps
CPU time 0.9 seconds
Started Oct 02 07:05:01 PM UTC 24
Finished Oct 02 07:05:03 PM UTC 24
Peak memory 202988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806856339 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3806856339
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4028659135
Short name T132
Test name
Test status
Simulation time 36250735 ps
CPU time 1.83 seconds
Started Oct 02 07:05:03 PM UTC 24
Finished Oct 02 07:05:06 PM UTC 24
Peak memory 205932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028659135 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_outstanding.4028659135
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.542531202
Short name T537
Test name
Test status
Simulation time 2802269439 ps
CPU time 4.85 seconds
Started Oct 02 07:05:01 PM UTC 24
Finished Oct 02 07:05:07 PM UTC 24
Peak memory 206960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542531202 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.542531202
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.666059037
Short name T149
Test name
Test status
Simulation time 127744335 ps
CPU time 2.45 seconds
Started Oct 02 07:05:01 PM UTC 24
Finished Oct 02 07:05:05 PM UTC 24
Peak memory 207112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666059037 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.666059037
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.1501594324
Short name T628
Test name
Test status
Simulation time 28756831 ps
CPU time 0.7 seconds
Started Oct 02 07:05:34 PM UTC 24
Finished Oct 02 07:05:36 PM UTC 24
Peak memory 202552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501594324 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1501594324
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/30.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.324052986
Short name T630
Test name
Test status
Simulation time 54763018 ps
CPU time 0.78 seconds
Started Oct 02 07:05:34 PM UTC 24
Finished Oct 02 07:05:36 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324052986 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.324052986
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/31.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.664855455
Short name T629
Test name
Test status
Simulation time 29793379 ps
CPU time 0.67 seconds
Started Oct 02 07:05:34 PM UTC 24
Finished Oct 02 07:05:36 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664855455 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.664855455
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/32.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.902877332
Short name T632
Test name
Test status
Simulation time 83980810 ps
CPU time 0.85 seconds
Started Oct 02 07:05:34 PM UTC 24
Finished Oct 02 07:05:36 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902877332 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.902877332
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/33.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.2466436630
Short name T631
Test name
Test status
Simulation time 41069432 ps
CPU time 0.73 seconds
Started Oct 02 07:05:34 PM UTC 24
Finished Oct 02 07:05:36 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466436630 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2466436630
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/34.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.2781858616
Short name T634
Test name
Test status
Simulation time 28457357 ps
CPU time 0.8 seconds
Started Oct 02 07:05:34 PM UTC 24
Finished Oct 02 07:05:36 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781858616 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2781858616
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/35.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.3906879048
Short name T635
Test name
Test status
Simulation time 11511915 ps
CPU time 0.74 seconds
Started Oct 02 07:05:34 PM UTC 24
Finished Oct 02 07:05:36 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906879048 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3906879048
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/36.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.1065321656
Short name T637
Test name
Test status
Simulation time 31848366 ps
CPU time 0.81 seconds
Started Oct 02 07:05:34 PM UTC 24
Finished Oct 02 07:05:36 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065321656 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1065321656
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/37.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.3111646583
Short name T636
Test name
Test status
Simulation time 26433096 ps
CPU time 0.71 seconds
Started Oct 02 07:05:34 PM UTC 24
Finished Oct 02 07:05:36 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111646583 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3111646583
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/38.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.1838565892
Short name T633
Test name
Test status
Simulation time 26228010 ps
CPU time 0.69 seconds
Started Oct 02 07:05:34 PM UTC 24
Finished Oct 02 07:05:36 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838565892 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1838565892
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/39.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.2462581682
Short name T127
Test name
Test status
Simulation time 543171398 ps
CPU time 8.32 seconds
Started Oct 02 07:05:06 PM UTC 24
Finished Oct 02 07:05:15 PM UTC 24
Peak memory 207188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462581682 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2462581682
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.1065222629
Short name T549
Test name
Test status
Simulation time 112982403 ps
CPU time 6.16 seconds
Started Oct 02 07:05:06 PM UTC 24
Finished Oct 02 07:05:13 PM UTC 24
Peak memory 207128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065222629 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1065222629
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.2470769964
Short name T119
Test name
Test status
Simulation time 21112775 ps
CPU time 1.19 seconds
Started Oct 02 07:05:04 PM UTC 24
Finished Oct 02 07:05:06 PM UTC 24
Peak memory 204760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470769964 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2470769964
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.171830953
Short name T650
Test name
Test status
Simulation time 360652514692 ps
CPU time 984.68 seconds
Started Oct 02 07:05:06 PM UTC 24
Finished Oct 02 07:21:42 PM UTC 24
Peak memory 227108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=171830953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_re
set.171830953
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.658527479
Short name T133
Test name
Test status
Simulation time 65007214 ps
CPU time 1.33 seconds
Started Oct 02 07:05:04 PM UTC 24
Finished Oct 02 07:05:06 PM UTC 24
Peak memory 205672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658527479 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.658527479
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.3164615907
Short name T535
Test name
Test status
Simulation time 11859652 ps
CPU time 0.95 seconds
Started Oct 02 07:05:03 PM UTC 24
Finished Oct 02 07:05:05 PM UTC 24
Peak memory 203048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164615907 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3164615907
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1739913823
Short name T134
Test name
Test status
Simulation time 102763262 ps
CPU time 2.52 seconds
Started Oct 02 07:05:06 PM UTC 24
Finished Oct 02 07:05:09 PM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739913823 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_outstanding.1739913823
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.1306339763
Short name T538
Test name
Test status
Simulation time 410552146 ps
CPU time 3.74 seconds
Started Oct 02 07:05:03 PM UTC 24
Finished Oct 02 07:05:07 PM UTC 24
Peak memory 207232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306339763 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1306339763
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.3972670161
Short name T639
Test name
Test status
Simulation time 17834610 ps
CPU time 0.88 seconds
Started Oct 02 07:05:35 PM UTC 24
Finished Oct 02 07:05:36 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972670161 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3972670161
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/40.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.3592249034
Short name T638
Test name
Test status
Simulation time 20625050 ps
CPU time 0.76 seconds
Started Oct 02 07:05:35 PM UTC 24
Finished Oct 02 07:05:36 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592249034 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3592249034
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/41.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.3114640603
Short name T642
Test name
Test status
Simulation time 40588141 ps
CPU time 0.81 seconds
Started Oct 02 07:05:35 PM UTC 24
Finished Oct 02 07:05:36 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114640603 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3114640603
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/42.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.3449193712
Short name T643
Test name
Test status
Simulation time 13225975 ps
CPU time 0.86 seconds
Started Oct 02 07:05:35 PM UTC 24
Finished Oct 02 07:05:37 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449193712 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3449193712
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/43.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.1280724313
Short name T644
Test name
Test status
Simulation time 18580597 ps
CPU time 0.78 seconds
Started Oct 02 07:05:35 PM UTC 24
Finished Oct 02 07:05:37 PM UTC 24
Peak memory 202784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280724313 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1280724313
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/44.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.1628503377
Short name T641
Test name
Test status
Simulation time 11100959 ps
CPU time 0.64 seconds
Started Oct 02 07:05:35 PM UTC 24
Finished Oct 02 07:05:36 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628503377 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1628503377
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/45.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.2028263300
Short name T640
Test name
Test status
Simulation time 15845672 ps
CPU time 0.71 seconds
Started Oct 02 07:05:35 PM UTC 24
Finished Oct 02 07:05:36 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028263300 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2028263300
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/46.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.1739463324
Short name T645
Test name
Test status
Simulation time 40154827 ps
CPU time 0.7 seconds
Started Oct 02 07:05:35 PM UTC 24
Finished Oct 02 07:05:37 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739463324 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1739463324
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/47.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.1660659099
Short name T647
Test name
Test status
Simulation time 11828249 ps
CPU time 0.75 seconds
Started Oct 02 07:05:37 PM UTC 24
Finished Oct 02 07:05:39 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660659099 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1660659099
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/48.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.1142181558
Short name T646
Test name
Test status
Simulation time 15761729 ps
CPU time 0.63 seconds
Started Oct 02 07:05:38 PM UTC 24
Finished Oct 02 07:05:39 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142181558 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1142181558
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/49.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4206882271
Short name T542
Test name
Test status
Simulation time 137512585 ps
CPU time 2.6 seconds
Started Oct 02 07:05:07 PM UTC 24
Finished Oct 02 07:05:11 PM UTC 24
Peak memory 222540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4206882271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_r
eset.4206882271
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.2717225924
Short name T120
Test name
Test status
Simulation time 46825108 ps
CPU time 1.21 seconds
Started Oct 02 07:05:06 PM UTC 24
Finished Oct 02 07:05:08 PM UTC 24
Peak memory 205988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717225924 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2717225924
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/5.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.284739834
Short name T539
Test name
Test status
Simulation time 18120281 ps
CPU time 0.91 seconds
Started Oct 02 07:05:06 PM UTC 24
Finished Oct 02 07:05:08 PM UTC 24
Peak memory 202860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284739834 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.284739834
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/5.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1186550383
Short name T543
Test name
Test status
Simulation time 158587337 ps
CPU time 3.28 seconds
Started Oct 02 07:05:07 PM UTC 24
Finished Oct 02 07:05:11 PM UTC 24
Peak memory 206796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186550383 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_outstanding.1186550383
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/5.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.3452906747
Short name T544
Test name
Test status
Simulation time 170240391 ps
CPU time 4.75 seconds
Started Oct 02 07:05:06 PM UTC 24
Finished Oct 02 07:05:12 PM UTC 24
Peak memory 206988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452906747 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3452906747
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/5.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.387195133
Short name T151
Test name
Test status
Simulation time 482633239 ps
CPU time 5.82 seconds
Started Oct 02 07:05:06 PM UTC 24
Finished Oct 02 07:05:13 PM UTC 24
Peak memory 206852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387195133 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.387195133
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/5.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3080124585
Short name T545
Test name
Test status
Simulation time 55894936 ps
CPU time 2.27 seconds
Started Oct 02 07:05:09 PM UTC 24
Finished Oct 02 07:05:12 PM UTC 24
Peak memory 206860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3080124585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_r
eset.3080124585
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.68677933
Short name T121
Test name
Test status
Simulation time 19827131 ps
CPU time 1.16 seconds
Started Oct 02 07:05:08 PM UTC 24
Finished Oct 02 07:05:11 PM UTC 24
Peak memory 205984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68677933 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.68677933
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/6.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.1179928835
Short name T541
Test name
Test status
Simulation time 15344970 ps
CPU time 0.95 seconds
Started Oct 02 07:05:08 PM UTC 24
Finished Oct 02 07:05:10 PM UTC 24
Peak memory 203048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179928835 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1179928835
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/6.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.217780062
Short name T546
Test name
Test status
Simulation time 432645721 ps
CPU time 2.78 seconds
Started Oct 02 07:05:08 PM UTC 24
Finished Oct 02 07:05:12 PM UTC 24
Peak memory 206788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217780062 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_outstanding.217780062
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/6.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.2591648518
Short name T540
Test name
Test status
Simulation time 86907424 ps
CPU time 1.96 seconds
Started Oct 02 07:05:07 PM UTC 24
Finished Oct 02 07:05:10 PM UTC 24
Peak memory 206004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591648518 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2591648518
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/6.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.4113782860
Short name T150
Test name
Test status
Simulation time 82723360 ps
CPU time 2.63 seconds
Started Oct 02 07:05:07 PM UTC 24
Finished Oct 02 07:05:11 PM UTC 24
Peak memory 207112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113782860 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.4113782860
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/6.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4116673384
Short name T649
Test name
Test status
Simulation time 38887498963 ps
CPU time 538.71 seconds
Started Oct 02 07:05:12 PM UTC 24
Finished Oct 02 07:14:18 PM UTC 24
Peak memory 221228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4116673384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_r
eset.4116673384
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.606778588
Short name T125
Test name
Test status
Simulation time 326303119 ps
CPU time 1.24 seconds
Started Oct 02 07:05:11 PM UTC 24
Finished Oct 02 07:05:13 PM UTC 24
Peak memory 205988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606778588 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.606778588
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/7.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.3886982144
Short name T547
Test name
Test status
Simulation time 11994716 ps
CPU time 0.83 seconds
Started Oct 02 07:05:11 PM UTC 24
Finished Oct 02 07:05:13 PM UTC 24
Peak memory 203048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886982144 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3886982144
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/7.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.607698185
Short name T552
Test name
Test status
Simulation time 200019061 ps
CPU time 2.04 seconds
Started Oct 02 07:05:12 PM UTC 24
Finished Oct 02 07:05:15 PM UTC 24
Peak memory 206848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607698185 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_outstanding.607698185
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/7.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.390145504
Short name T553
Test name
Test status
Simulation time 196448705 ps
CPU time 4.82 seconds
Started Oct 02 07:05:10 PM UTC 24
Finished Oct 02 07:05:15 PM UTC 24
Peak memory 206724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390145504 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.390145504
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/7.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.2184135158
Short name T550
Test name
Test status
Simulation time 1173479406 ps
CPU time 2.7 seconds
Started Oct 02 07:05:10 PM UTC 24
Finished Oct 02 07:05:13 PM UTC 24
Peak memory 206720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184135158 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2184135158
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/7.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2339034245
Short name T559
Test name
Test status
Simulation time 139059872 ps
CPU time 1.85 seconds
Started Oct 02 07:05:13 PM UTC 24
Finished Oct 02 07:05:16 PM UTC 24
Peak memory 223372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2339034245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_r
eset.2339034245
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.1411463287
Short name T556
Test name
Test status
Simulation time 96205952 ps
CPU time 1.12 seconds
Started Oct 02 07:05:13 PM UTC 24
Finished Oct 02 07:05:16 PM UTC 24
Peak memory 206520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411463287 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1411463287
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/8.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.972616051
Short name T551
Test name
Test status
Simulation time 45803706 ps
CPU time 0.7 seconds
Started Oct 02 07:05:13 PM UTC 24
Finished Oct 02 07:05:15 PM UTC 24
Peak memory 202860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972616051 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.972616051
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/8.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3399772692
Short name T558
Test name
Test status
Simulation time 45749391 ps
CPU time 1.45 seconds
Started Oct 02 07:05:13 PM UTC 24
Finished Oct 02 07:05:16 PM UTC 24
Peak memory 205884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399772692 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_outstanding.3399772692
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/8.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.1816964614
Short name T554
Test name
Test status
Simulation time 34736761 ps
CPU time 2.47 seconds
Started Oct 02 07:05:12 PM UTC 24
Finished Oct 02 07:05:16 PM UTC 24
Peak memory 206836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816964614 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1816964614
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/8.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.407753413
Short name T146
Test name
Test status
Simulation time 86770021 ps
CPU time 1.97 seconds
Started Oct 02 07:05:12 PM UTC 24
Finished Oct 02 07:05:15 PM UTC 24
Peak memory 205896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407753413 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.407753413
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/8.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3865515909
Short name T563
Test name
Test status
Simulation time 73978487 ps
CPU time 1.76 seconds
Started Oct 02 07:05:17 PM UTC 24
Finished Oct 02 07:05:20 PM UTC 24
Peak memory 206120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3865515909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_r
eset.3865515909
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.805692097
Short name T557
Test name
Test status
Simulation time 33271040 ps
CPU time 1.08 seconds
Started Oct 02 07:05:13 PM UTC 24
Finished Oct 02 07:05:16 PM UTC 24
Peak memory 205784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805692097 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.805692097
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/9.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.2958950094
Short name T555
Test name
Test status
Simulation time 13332534 ps
CPU time 0.84 seconds
Started Oct 02 07:05:13 PM UTC 24
Finished Oct 02 07:05:16 PM UTC 24
Peak memory 203048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958950094 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2958950094
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/9.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2006856632
Short name T562
Test name
Test status
Simulation time 169598365 ps
CPU time 1.41 seconds
Started Oct 02 07:05:17 PM UTC 24
Finished Oct 02 07:05:20 PM UTC 24
Peak memory 206164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006856632 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_outstanding.2006856632
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/9.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.162152905
Short name T560
Test name
Test status
Simulation time 796963950 ps
CPU time 2.17 seconds
Started Oct 02 07:05:13 PM UTC 24
Finished Oct 02 07:05:17 PM UTC 24
Peak memory 206840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162152905 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.162152905
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/9.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.361228732
Short name T561
Test name
Test status
Simulation time 714966902 ps
CPU time 3.91 seconds
Started Oct 02 07:05:13 PM UTC 24
Finished Oct 02 07:05:19 PM UTC 24
Peak memory 207124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361228732 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.361228732
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/9.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/0.hmac_back_pressure.1087684531
Short name T54
Test name
Test status
Simulation time 16140343082 ps
CPU time 76.53 seconds
Started Oct 02 07:44:05 PM UTC 24
Finished Oct 02 07:45:24 PM UTC 24
Peak memory 210568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087684531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1087684531
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/0.hmac_burst_wr.1673914728
Short name T12
Test name
Test status
Simulation time 5460031695 ps
CPU time 51.37 seconds
Started Oct 02 07:44:05 PM UTC 24
Finished Oct 02 07:44:58 PM UTC 24
Peak memory 210752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673914728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1673914728
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/0.hmac_datapath_stress.3138070808
Short name T157
Test name
Test status
Simulation time 14161379093 ps
CPU time 266.78 seconds
Started Oct 02 07:44:05 PM UTC 24
Finished Oct 02 07:48:35 PM UTC 24
Peak memory 683308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138070808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3138070808
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/0.hmac_long_msg.4086050020
Short name T47
Test name
Test status
Simulation time 23960772477 ps
CPU time 218.98 seconds
Started Oct 02 07:44:05 PM UTC 24
Finished Oct 02 07:47:47 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086050020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.4086050020
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/0.hmac_stress_all.4060281737
Short name T378
Test name
Test status
Simulation time 122300880413 ps
CPU time 1427.6 seconds
Started Oct 02 07:44:05 PM UTC 24
Finished Oct 02 08:08:07 PM UTC 24
Peak memory 785944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060281737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.4060281737
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/0.hmac_test_hmac256_vectors.4005299847
Short name T60
Test name
Test status
Simulation time 17217001212 ps
CPU time 78.15 seconds
Started Oct 02 07:44:05 PM UTC 24
Finished Oct 02 07:45:25 PM UTC 24
Peak memory 210752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005299847 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.4005299847
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/0.hmac_test_hmac384_vectors.240094583
Short name T173
Test name
Test status
Simulation time 3196313173 ps
CPU time 64.56 seconds
Started Oct 02 07:44:05 PM UTC 24
Finished Oct 02 07:45:12 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240094583 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.240094583
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/0.hmac_test_hmac512_vectors.3474089503
Short name T78
Test name
Test status
Simulation time 7271071360 ps
CPU time 99.94 seconds
Started Oct 02 07:44:05 PM UTC 24
Finished Oct 02 07:45:48 PM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474089503 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.3474089503
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/0.hmac_test_sha256_vectors.3657710935
Short name T160
Test name
Test status
Simulation time 55717646777 ps
CPU time 586.73 seconds
Started Oct 02 07:44:05 PM UTC 24
Finished Oct 02 07:54:00 PM UTC 24
Peak memory 214192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657710935 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3657710935
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/0.hmac_test_sha384_vectors.970556400
Short name T493
Test name
Test status
Simulation time 264299951466 ps
CPU time 2585.03 seconds
Started Oct 02 07:44:05 PM UTC 24
Finished Oct 02 08:27:40 PM UTC 24
Peak memory 224400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970556400 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.970556400
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/0.hmac_test_sha512_vectors.4230523079
Short name T495
Test name
Test status
Simulation time 260381259753 ps
CPU time 2619.6 seconds
Started Oct 02 07:44:05 PM UTC 24
Finished Oct 02 08:28:16 PM UTC 24
Peak memory 230440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230523079 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.4230523079
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/0.hmac_wipe_secret.3168812722
Short name T7
Test name
Test status
Simulation time 1973648104 ps
CPU time 29.19 seconds
Started Oct 02 07:44:05 PM UTC 24
Finished Oct 02 07:44:36 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168812722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3168812722
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/0.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/1.hmac_alert_test.2295957153
Short name T21
Test name
Test status
Simulation time 12187803 ps
CPU time 0.94 seconds
Started Oct 02 07:44:13 PM UTC 24
Finished Oct 02 07:44:15 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295957153 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2295957153
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/1.hmac_datapath_stress.1759026094
Short name T249
Test name
Test status
Simulation time 10725125702 ps
CPU time 638.15 seconds
Started Oct 02 07:44:06 PM UTC 24
Finished Oct 02 07:54:52 PM UTC 24
Peak memory 495088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759026094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1759026094
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/1.hmac_error.671844584
Short name T26
Test name
Test status
Simulation time 618015718 ps
CPU time 41.66 seconds
Started Oct 02 07:44:06 PM UTC 24
Finished Oct 02 07:44:49 PM UTC 24
Peak memory 210308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671844584 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.671844584
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/1.hmac_long_msg.2513844725
Short name T10
Test name
Test status
Simulation time 867015127 ps
CPU time 49.69 seconds
Started Oct 02 07:44:06 PM UTC 24
Finished Oct 02 07:44:57 PM UTC 24
Peak memory 210320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513844725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2513844725
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/1.hmac_sec_cm.4027322396
Short name T3
Test name
Test status
Simulation time 339273515 ps
CPU time 1.62 seconds
Started Oct 02 07:44:10 PM UTC 24
Finished Oct 02 07:44:13 PM UTC 24
Peak memory 238204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027322396 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.4027322396
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/1.hmac_smoke.3282133264
Short name T6
Test name
Test status
Simulation time 1236006245 ps
CPU time 22.93 seconds
Started Oct 02 07:44:06 PM UTC 24
Finished Oct 02 07:44:30 PM UTC 24
Peak memory 210472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282133264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3282133264
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/1.hmac_stress_all.1871813468
Short name T448
Test name
Test status
Simulation time 76714681660 ps
CPU time 1869.59 seconds
Started Oct 02 07:44:08 PM UTC 24
Finished Oct 02 08:15:38 PM UTC 24
Peak memory 769244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871813468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1871813468
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/1.hmac_test_hmac256_vectors.2843689209
Short name T71
Test name
Test status
Simulation time 2584282634 ps
CPU time 52.53 seconds
Started Oct 02 07:44:08 PM UTC 24
Finished Oct 02 07:45:02 PM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843689209 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.2843689209
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/1.hmac_test_hmac384_vectors.578752205
Short name T172
Test name
Test status
Simulation time 16916324401 ps
CPU time 61.28 seconds
Started Oct 02 07:44:08 PM UTC 24
Finished Oct 02 07:45:11 PM UTC 24
Peak memory 210768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578752205 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.578752205
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/1.hmac_test_hmac512_vectors.296946098
Short name T175
Test name
Test status
Simulation time 7179414746 ps
CPU time 84.45 seconds
Started Oct 02 07:44:08 PM UTC 24
Finished Oct 02 07:45:34 PM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296946098 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.296946098
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/1.hmac_test_sha256_vectors.1271285230
Short name T273
Test name
Test status
Simulation time 91133111320 ps
CPU time 758.03 seconds
Started Oct 02 07:44:06 PM UTC 24
Finished Oct 02 07:56:54 PM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271285230 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1271285230
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/1.hmac_test_sha384_vectors.4257362125
Short name T507
Test name
Test status
Simulation time 143795802192 ps
CPU time 2953.67 seconds
Started Oct 02 07:44:08 PM UTC 24
Finished Oct 02 08:33:56 PM UTC 24
Peak memory 224624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257362125 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.4257362125
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/1.hmac_test_sha512_vectors.3955480007
Short name T508
Test name
Test status
Simulation time 855427809025 ps
CPU time 2967.07 seconds
Started Oct 02 07:44:08 PM UTC 24
Finished Oct 02 08:34:12 PM UTC 24
Peak memory 224688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955480007 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.3955480007
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/1.hmac_wipe_secret.2466830946
Short name T5
Test name
Test status
Simulation time 3787401089 ps
CPU time 18.33 seconds
Started Oct 02 07:44:06 PM UTC 24
Finished Oct 02 07:44:25 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466830946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2466830946
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/1.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/10.hmac_alert_test.536684652
Short name T195
Test name
Test status
Simulation time 52562708 ps
CPU time 0.92 seconds
Started Oct 02 07:48:30 PM UTC 24
Finished Oct 02 07:48:32 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536684652 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.536684652
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/10.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/10.hmac_back_pressure.2549368669
Short name T200
Test name
Test status
Simulation time 590625786 ps
CPU time 47.12 seconds
Started Oct 02 07:48:13 PM UTC 24
Finished Oct 02 07:49:02 PM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549368669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2549368669
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/10.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/10.hmac_burst_wr.3458647914
Short name T103
Test name
Test status
Simulation time 1240055513 ps
CPU time 92.47 seconds
Started Oct 02 07:48:16 PM UTC 24
Finished Oct 02 07:49:51 PM UTC 24
Peak memory 218884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458647914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3458647914
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/10.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/10.hmac_datapath_stress.2320720590
Short name T383
Test name
Test status
Simulation time 32051188919 ps
CPU time 1214.38 seconds
Started Oct 02 07:48:16 PM UTC 24
Finished Oct 02 08:08:43 PM UTC 24
Peak memory 759036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320720590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2320720590
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/10.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/10.hmac_error.610689012
Short name T197
Test name
Test status
Simulation time 3341607604 ps
CPU time 18.05 seconds
Started Oct 02 07:48:17 PM UTC 24
Finished Oct 02 07:48:36 PM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610689012 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.610689012
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/10.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/10.hmac_long_msg.1812808248
Short name T213
Test name
Test status
Simulation time 11903191193 ps
CPU time 215.84 seconds
Started Oct 02 07:48:12 PM UTC 24
Finished Oct 02 07:51:51 PM UTC 24
Peak memory 219100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812808248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1812808248
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/10.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/10.hmac_smoke.645156085
Short name T194
Test name
Test status
Simulation time 798988043 ps
CPU time 15.4 seconds
Started Oct 02 07:48:12 PM UTC 24
Finished Oct 02 07:48:28 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645156085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.645156085
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/10.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/10.hmac_stress_all.2690210002
Short name T80
Test name
Test status
Simulation time 274232703665 ps
CPU time 1282.37 seconds
Started Oct 02 07:48:30 PM UTC 24
Finished Oct 02 08:10:08 PM UTC 24
Peak memory 728352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690210002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2690210002
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/10.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/10.hmac_wipe_secret.2647291249
Short name T98
Test name
Test status
Simulation time 1071865482 ps
CPU time 63.4 seconds
Started Oct 02 07:48:22 PM UTC 24
Finished Oct 02 07:49:27 PM UTC 24
Peak memory 210348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647291249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2647291249
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/10.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/11.hmac_alert_test.2726782613
Short name T198
Test name
Test status
Simulation time 15243258 ps
CPU time 0.92 seconds
Started Oct 02 07:48:46 PM UTC 24
Finished Oct 02 07:48:48 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726782613 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2726782613
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/11.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/11.hmac_back_pressure.3042760063
Short name T105
Test name
Test status
Simulation time 2180934347 ps
CPU time 81.96 seconds
Started Oct 02 07:48:37 PM UTC 24
Finished Oct 02 07:50:01 PM UTC 24
Peak memory 210516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042760063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3042760063
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/11.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/11.hmac_burst_wr.840780179
Short name T143
Test name
Test status
Simulation time 2052610138 ps
CPU time 47.59 seconds
Started Oct 02 07:48:37 PM UTC 24
Finished Oct 02 07:49:27 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840780179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.840780179
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/11.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/11.hmac_datapath_stress.3985898763
Short name T341
Test name
Test status
Simulation time 4424156162 ps
CPU time 951.73 seconds
Started Oct 02 07:48:37 PM UTC 24
Finished Oct 02 08:04:40 PM UTC 24
Peak memory 734544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985898763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3985898763
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/11.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/11.hmac_error.2319237858
Short name T202
Test name
Test status
Simulation time 455955410 ps
CPU time 33.01 seconds
Started Oct 02 07:48:37 PM UTC 24
Finished Oct 02 07:49:12 PM UTC 24
Peak memory 210308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319237858 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2319237858
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/11.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/11.hmac_long_msg.3723716738
Short name T207
Test name
Test status
Simulation time 7142965664 ps
CPU time 98.26 seconds
Started Oct 02 07:48:32 PM UTC 24
Finished Oct 02 07:50:13 PM UTC 24
Peak memory 210412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723716738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3723716738
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/11.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/11.hmac_smoke.3695290971
Short name T164
Test name
Test status
Simulation time 157819440 ps
CPU time 3.76 seconds
Started Oct 02 07:48:31 PM UTC 24
Finished Oct 02 07:48:36 PM UTC 24
Peak memory 210320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695290971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3695290971
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/11.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/11.hmac_stress_all.749031504
Short name T87
Test name
Test status
Simulation time 106586275239 ps
CPU time 3052.09 seconds
Started Oct 02 07:48:42 PM UTC 24
Finished Oct 02 08:40:07 PM UTC 24
Peak memory 804068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749031504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.749031504
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/11.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/11.hmac_wipe_secret.2593161734
Short name T102
Test name
Test status
Simulation time 6083546605 ps
CPU time 66.25 seconds
Started Oct 02 07:48:39 PM UTC 24
Finished Oct 02 07:49:47 PM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593161734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2593161734
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/11.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/12.hmac_alert_test.1015381165
Short name T203
Test name
Test status
Simulation time 34235038 ps
CPU time 0.94 seconds
Started Oct 02 07:49:13 PM UTC 24
Finished Oct 02 07:49:15 PM UTC 24
Peak memory 207280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015381165 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1015381165
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/12.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/12.hmac_burst_wr.2154274522
Short name T204
Test name
Test status
Simulation time 2794989783 ps
CPU time 8.56 seconds
Started Oct 02 07:49:05 PM UTC 24
Finished Oct 02 07:49:15 PM UTC 24
Peak memory 210600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154274522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2154274522
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/12.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/12.hmac_datapath_stress.1733377423
Short name T346
Test name
Test status
Simulation time 23209870541 ps
CPU time 955.99 seconds
Started Oct 02 07:49:05 PM UTC 24
Finished Oct 02 08:05:11 PM UTC 24
Peak memory 695524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733377423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1733377423
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/12.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/12.hmac_error.2433200021
Short name T92
Test name
Test status
Simulation time 3846396706 ps
CPU time 137.67 seconds
Started Oct 02 07:49:06 PM UTC 24
Finished Oct 02 07:51:26 PM UTC 24
Peak memory 210424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433200021 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2433200021
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/12.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/12.hmac_long_msg.3211292
Short name T206
Test name
Test status
Simulation time 1655855047 ps
CPU time 25.6 seconds
Started Oct 02 07:48:59 PM UTC 24
Finished Oct 02 07:49:26 PM UTC 24
Peak memory 210632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3211292
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/12.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/12.hmac_smoke.4198746255
Short name T201
Test name
Test status
Simulation time 3793634597 ps
CPU time 17.7 seconds
Started Oct 02 07:48:49 PM UTC 24
Finished Oct 02 07:49:08 PM UTC 24
Peak memory 210516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198746255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.4198746255
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/12.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/12.hmac_stress_all.2430257113
Short name T88
Test name
Test status
Simulation time 392610399737 ps
CPU time 3355.26 seconds
Started Oct 02 07:49:13 PM UTC 24
Finished Oct 02 08:45:44 PM UTC 24
Peak memory 822680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430257113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2430257113
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/12.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/12.hmac_wipe_secret.3722356298
Short name T104
Test name
Test status
Simulation time 3576663665 ps
CPU time 50.32 seconds
Started Oct 02 07:49:09 PM UTC 24
Finished Oct 02 07:50:01 PM UTC 24
Peak memory 210828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722356298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3722356298
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/12.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/13.hmac_alert_test.536990650
Short name T99
Test name
Test status
Simulation time 36755540 ps
CPU time 0.89 seconds
Started Oct 02 07:49:35 PM UTC 24
Finished Oct 02 07:49:37 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536990650 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.536990650
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/13.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/13.hmac_back_pressure.3949020963
Short name T56
Test name
Test status
Simulation time 210590238 ps
CPU time 16.59 seconds
Started Oct 02 07:49:16 PM UTC 24
Finished Oct 02 07:49:34 PM UTC 24
Peak memory 210632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949020963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3949020963
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/13.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/13.hmac_datapath_stress.2529218459
Short name T322
Test name
Test status
Simulation time 24789630650 ps
CPU time 778.74 seconds
Started Oct 02 07:49:22 PM UTC 24
Finished Oct 02 08:02:30 PM UTC 24
Peak memory 699648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529218459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2529218459
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/13.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/13.hmac_error.3315164760
Short name T212
Test name
Test status
Simulation time 4907578981 ps
CPU time 73.63 seconds
Started Oct 02 07:49:26 PM UTC 24
Finished Oct 02 07:50:42 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315164760 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3315164760
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/13.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/13.hmac_long_msg.1799654809
Short name T96
Test name
Test status
Simulation time 9585024232 ps
CPU time 150.19 seconds
Started Oct 02 07:49:16 PM UTC 24
Finished Oct 02 07:51:49 PM UTC 24
Peak memory 219132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799654809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1799654809
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/13.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/13.hmac_smoke.1421845419
Short name T205
Test name
Test status
Simulation time 571016697 ps
CPU time 3.61 seconds
Started Oct 02 07:49:16 PM UTC 24
Finished Oct 02 07:49:21 PM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421845419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1421845419
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/13.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/13.hmac_wipe_secret.1989276220
Short name T136
Test name
Test status
Simulation time 3898284814 ps
CPU time 60.01 seconds
Started Oct 02 07:49:28 PM UTC 24
Finished Oct 02 07:50:30 PM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989276220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1989276220
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/13.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/14.hmac_alert_test.4218670443
Short name T106
Test name
Test status
Simulation time 25668181 ps
CPU time 0.9 seconds
Started Oct 02 07:50:03 PM UTC 24
Finished Oct 02 07:50:05 PM UTC 24
Peak memory 207400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218670443 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.4218670443
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/14.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/14.hmac_back_pressure.4274578365
Short name T58
Test name
Test status
Simulation time 4481330574 ps
CPU time 63.53 seconds
Started Oct 02 07:49:46 PM UTC 24
Finished Oct 02 07:50:52 PM UTC 24
Peak memory 210568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274578365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.4274578365
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/14.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/14.hmac_burst_wr.276197529
Short name T209
Test name
Test status
Simulation time 5914840088 ps
CPU time 33.8 seconds
Started Oct 02 07:49:52 PM UTC 24
Finished Oct 02 07:50:28 PM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276197529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.276197529
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/14.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/14.hmac_datapath_stress.2780884844
Short name T326
Test name
Test status
Simulation time 42259192132 ps
CPU time 777.32 seconds
Started Oct 02 07:49:49 PM UTC 24
Finished Oct 02 08:02:56 PM UTC 24
Peak memory 724580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780884844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2780884844
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/14.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/14.hmac_error.3718507537
Short name T216
Test name
Test status
Simulation time 64201696761 ps
CPU time 141.68 seconds
Started Oct 02 07:49:54 PM UTC 24
Finished Oct 02 07:52:18 PM UTC 24
Peak memory 210856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718507537 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3718507537
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/14.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/14.hmac_long_msg.969840855
Short name T93
Test name
Test status
Simulation time 1398894335 ps
CPU time 100.11 seconds
Started Oct 02 07:49:46 PM UTC 24
Finished Oct 02 07:51:29 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969840855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.969840855
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/14.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/14.hmac_smoke.1878570083
Short name T100
Test name
Test status
Simulation time 343363734 ps
CPU time 4.67 seconds
Started Oct 02 07:49:38 PM UTC 24
Finished Oct 02 07:49:44 PM UTC 24
Peak memory 210512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878570083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1878570083
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/14.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/14.hmac_stress_all.2270991773
Short name T501
Test name
Test status
Simulation time 56713372942 ps
CPU time 2478.02 seconds
Started Oct 02 07:50:02 PM UTC 24
Finished Oct 02 08:31:49 PM UTC 24
Peak memory 769268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270991773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2270991773
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/14.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/14.hmac_wipe_secret.3629718309
Short name T137
Test name
Test status
Simulation time 15080536790 ps
CPU time 120.7 seconds
Started Oct 02 07:49:57 PM UTC 24
Finished Oct 02 07:52:00 PM UTC 24
Peak memory 210516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629718309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3629718309
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/14.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/15.hmac_alert_test.1923917832
Short name T211
Test name
Test status
Simulation time 36760362 ps
CPU time 0.88 seconds
Started Oct 02 07:50:37 PM UTC 24
Finished Oct 02 07:50:39 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923917832 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1923917832
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/15.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/15.hmac_back_pressure.2696946179
Short name T91
Test name
Test status
Simulation time 7624910772 ps
CPU time 43.33 seconds
Started Oct 02 07:50:14 PM UTC 24
Finished Oct 02 07:50:59 PM UTC 24
Peak memory 210488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696946179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2696946179
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/15.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/15.hmac_burst_wr.4101179943
Short name T90
Test name
Test status
Simulation time 4225405752 ps
CPU time 28.19 seconds
Started Oct 02 07:50:28 PM UTC 24
Finished Oct 02 07:50:58 PM UTC 24
Peak memory 210488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101179943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.4101179943
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/15.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/15.hmac_datapath_stress.2998524783
Short name T222
Test name
Test status
Simulation time 800607790 ps
CPU time 136.19 seconds
Started Oct 02 07:50:23 PM UTC 24
Finished Oct 02 07:52:41 PM UTC 24
Peak memory 666920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998524783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2998524783
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/15.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/15.hmac_error.320493505
Short name T224
Test name
Test status
Simulation time 7069683345 ps
CPU time 134.48 seconds
Started Oct 02 07:50:29 PM UTC 24
Finished Oct 02 07:52:47 PM UTC 24
Peak memory 210688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320493505 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.320493505
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/15.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/15.hmac_long_msg.3093830670
Short name T238
Test name
Test status
Simulation time 39299289507 ps
CPU time 222.42 seconds
Started Oct 02 07:50:09 PM UTC 24
Finished Oct 02 07:53:55 PM UTC 24
Peak memory 219328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093830670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3093830670
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/15.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/15.hmac_smoke.4134504766
Short name T208
Test name
Test status
Simulation time 3710795791 ps
CPU time 14.59 seconds
Started Oct 02 07:50:06 PM UTC 24
Finished Oct 02 07:50:22 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134504766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.4134504766
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/15.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/15.hmac_stress_all.1720504994
Short name T500
Test name
Test status
Simulation time 388500647361 ps
CPU time 2428.06 seconds
Started Oct 02 07:50:32 PM UTC 24
Finished Oct 02 08:31:29 PM UTC 24
Peak memory 779560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720504994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1720504994
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/15.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/15.hmac_wipe_secret.2043174980
Short name T138
Test name
Test status
Simulation time 7345943042 ps
CPU time 120.16 seconds
Started Oct 02 07:50:32 PM UTC 24
Finished Oct 02 07:52:34 PM UTC 24
Peak memory 210480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043174980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.2043174980
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/15.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/16.hmac_alert_test.1122128534
Short name T94
Test name
Test status
Simulation time 25538413 ps
CPU time 0.92 seconds
Started Oct 02 07:51:30 PM UTC 24
Finished Oct 02 07:51:32 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122128534 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1122128534
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/16.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/16.hmac_back_pressure.4287796706
Short name T221
Test name
Test status
Simulation time 4700740991 ps
CPU time 102.8 seconds
Started Oct 02 07:50:52 PM UTC 24
Finished Oct 02 07:52:37 PM UTC 24
Peak memory 210516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287796706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.4287796706
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/16.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/16.hmac_burst_wr.890779008
Short name T215
Test name
Test status
Simulation time 13360329787 ps
CPU time 76.06 seconds
Started Oct 02 07:50:54 PM UTC 24
Finished Oct 02 07:52:12 PM UTC 24
Peak memory 210744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890779008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.890779008
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/16.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/16.hmac_datapath_stress.3462821790
Short name T318
Test name
Test status
Simulation time 16733774786 ps
CPU time 671.35 seconds
Started Oct 02 07:50:52 PM UTC 24
Finished Oct 02 08:02:12 PM UTC 24
Peak memory 699908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462821790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3462821790
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/16.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/16.hmac_error.1894723748
Short name T218
Test name
Test status
Simulation time 22062720003 ps
CPU time 85.24 seconds
Started Oct 02 07:50:59 PM UTC 24
Finished Oct 02 07:52:27 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894723748 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1894723748
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/16.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/16.hmac_long_msg.1613204830
Short name T220
Test name
Test status
Simulation time 30655374871 ps
CPU time 109.65 seconds
Started Oct 02 07:50:43 PM UTC 24
Finished Oct 02 07:52:36 PM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613204830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1613204830
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/16.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/16.hmac_smoke.4017517629
Short name T89
Test name
Test status
Simulation time 1215190002 ps
CPU time 10.16 seconds
Started Oct 02 07:50:40 PM UTC 24
Finished Oct 02 07:50:51 PM UTC 24
Peak memory 210392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017517629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.4017517629
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/16.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/16.hmac_stress_all.2547568830
Short name T511
Test name
Test status
Simulation time 76067409010 ps
CPU time 2833.52 seconds
Started Oct 02 07:51:27 PM UTC 24
Finished Oct 02 08:39:11 PM UTC 24
Peak memory 742716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547568830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2547568830
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/16.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/16.hmac_wipe_secret.527369695
Short name T214
Test name
Test status
Simulation time 11623939896 ps
CPU time 51.13 seconds
Started Oct 02 07:51:00 PM UTC 24
Finished Oct 02 07:51:53 PM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527369695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.527369695
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/16.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/17.hmac_alert_test.1112852867
Short name T217
Test name
Test status
Simulation time 16003743 ps
CPU time 0.88 seconds
Started Oct 02 07:52:19 PM UTC 24
Finished Oct 02 07:52:21 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112852867 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1112852867
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/17.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/17.hmac_back_pressure.1985802420
Short name T228
Test name
Test status
Simulation time 1846206812 ps
CPU time 86.26 seconds
Started Oct 02 07:51:51 PM UTC 24
Finished Oct 02 07:53:19 PM UTC 24
Peak memory 210404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985802420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1985802420
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/17.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/17.hmac_burst_wr.290472069
Short name T167
Test name
Test status
Simulation time 2899000124 ps
CPU time 86.19 seconds
Started Oct 02 07:51:55 PM UTC 24
Finished Oct 02 07:53:23 PM UTC 24
Peak memory 210476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290472069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.290472069
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/17.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/17.hmac_datapath_stress.1714691753
Short name T344
Test name
Test status
Simulation time 15328920904 ps
CPU time 783.73 seconds
Started Oct 02 07:51:53 PM UTC 24
Finished Oct 02 08:05:07 PM UTC 24
Peak memory 720216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714691753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1714691753
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/17.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/17.hmac_error.2168366537
Short name T227
Test name
Test status
Simulation time 24643792461 ps
CPU time 72.21 seconds
Started Oct 02 07:52:01 PM UTC 24
Finished Oct 02 07:53:16 PM UTC 24
Peak memory 210528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168366537 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2168366537
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/17.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/17.hmac_long_msg.3914440363
Short name T231
Test name
Test status
Simulation time 28052276339 ps
CPU time 104.37 seconds
Started Oct 02 07:51:40 PM UTC 24
Finished Oct 02 07:53:27 PM UTC 24
Peak memory 210468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914440363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3914440363
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/17.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/17.hmac_smoke.3592053061
Short name T95
Test name
Test status
Simulation time 3930419579 ps
CPU time 5.58 seconds
Started Oct 02 07:51:33 PM UTC 24
Finished Oct 02 07:51:40 PM UTC 24
Peak memory 210448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592053061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3592053061
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/17.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/17.hmac_stress_all.2979669335
Short name T144
Test name
Test status
Simulation time 50668227158 ps
CPU time 713.04 seconds
Started Oct 02 07:52:14 PM UTC 24
Finished Oct 02 08:04:16 PM UTC 24
Peak memory 219032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979669335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2979669335
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/17.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/17.hmac_wipe_secret.1803952451
Short name T139
Test name
Test status
Simulation time 8070948283 ps
CPU time 82.49 seconds
Started Oct 02 07:52:08 PM UTC 24
Finished Oct 02 07:53:33 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803952451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1803952451
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/17.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/18.hmac_alert_test.910027353
Short name T223
Test name
Test status
Simulation time 48087317 ps
CPU time 0.9 seconds
Started Oct 02 07:52:43 PM UTC 24
Finished Oct 02 07:52:45 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910027353 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.910027353
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/18.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/18.hmac_back_pressure.2650895495
Short name T234
Test name
Test status
Simulation time 1011787393 ps
CPU time 57.75 seconds
Started Oct 02 07:52:31 PM UTC 24
Finished Oct 02 07:53:30 PM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650895495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2650895495
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/18.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/18.hmac_burst_wr.3335430477
Short name T165
Test name
Test status
Simulation time 254221709 ps
CPU time 12.37 seconds
Started Oct 02 07:52:36 PM UTC 24
Finished Oct 02 07:52:50 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335430477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3335430477
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/18.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/18.hmac_datapath_stress.752323134
Short name T291
Test name
Test status
Simulation time 4630248079 ps
CPU time 386.62 seconds
Started Oct 02 07:52:36 PM UTC 24
Finished Oct 02 07:59:08 PM UTC 24
Peak memory 496924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752323134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.752323134
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/18.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/18.hmac_error.1501230130
Short name T259
Test name
Test status
Simulation time 8302752368 ps
CPU time 180.31 seconds
Started Oct 02 07:52:39 PM UTC 24
Finished Oct 02 07:55:42 PM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501230130 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1501230130
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/18.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/18.hmac_long_msg.1877003575
Short name T246
Test name
Test status
Simulation time 20948040268 ps
CPU time 122.48 seconds
Started Oct 02 07:52:28 PM UTC 24
Finished Oct 02 07:54:33 PM UTC 24
Peak memory 210488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877003575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1877003575
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/18.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/18.hmac_smoke.2639349170
Short name T219
Test name
Test status
Simulation time 388561534 ps
CPU time 6.75 seconds
Started Oct 02 07:52:22 PM UTC 24
Finished Oct 02 07:52:30 PM UTC 24
Peak memory 210512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639349170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2639349170
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/18.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/18.hmac_wipe_secret.1357412491
Short name T226
Test name
Test status
Simulation time 2056351343 ps
CPU time 12.84 seconds
Started Oct 02 07:52:39 PM UTC 24
Finished Oct 02 07:52:53 PM UTC 24
Peak memory 210420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357412491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1357412491
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/18.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/19.hmac_alert_test.2671968236
Short name T229
Test name
Test status
Simulation time 29470860 ps
CPU time 0.9 seconds
Started Oct 02 07:53:19 PM UTC 24
Finished Oct 02 07:53:21 PM UTC 24
Peak memory 207400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671968236 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2671968236
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/19.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/19.hmac_back_pressure.2449620495
Short name T242
Test name
Test status
Simulation time 2899965059 ps
CPU time 90.88 seconds
Started Oct 02 07:52:51 PM UTC 24
Finished Oct 02 07:54:23 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449620495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2449620495
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/19.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/19.hmac_burst_wr.2336322998
Short name T230
Test name
Test status
Simulation time 1458197533 ps
CPU time 27.99 seconds
Started Oct 02 07:52:54 PM UTC 24
Finished Oct 02 07:53:23 PM UTC 24
Peak memory 219108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336322998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2336322998
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/19.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/19.hmac_datapath_stress.4238762849
Short name T161
Test name
Test status
Simulation time 224799197 ps
CPU time 25.99 seconds
Started Oct 02 07:52:51 PM UTC 24
Finished Oct 02 07:53:18 PM UTC 24
Peak memory 250996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238762849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.4238762849
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/19.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/19.hmac_error.2483858869
Short name T285
Test name
Test status
Simulation time 15219113810 ps
CPU time 295.32 seconds
Started Oct 02 07:53:08 PM UTC 24
Finished Oct 02 07:58:08 PM UTC 24
Peak memory 210756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483858869 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2483858869
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/19.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/19.hmac_long_msg.68540625
Short name T260
Test name
Test status
Simulation time 2901862388 ps
CPU time 175.62 seconds
Started Oct 02 07:52:48 PM UTC 24
Finished Oct 02 07:55:47 PM UTC 24
Peak memory 210416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68540625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.68540625
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/19.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/19.hmac_smoke.2536497756
Short name T225
Test name
Test status
Simulation time 90530166 ps
CPU time 2.57 seconds
Started Oct 02 07:52:46 PM UTC 24
Finished Oct 02 07:52:50 PM UTC 24
Peak memory 210512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536497756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2536497756
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/19.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/19.hmac_stress_all.2313548581
Short name T517
Test name
Test status
Simulation time 45221636250 ps
CPU time 3428.61 seconds
Started Oct 02 07:53:17 PM UTC 24
Finished Oct 02 08:51:00 PM UTC 24
Peak memory 853240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313548581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2313548581
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/19.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/19.hmac_wipe_secret.1082771944
Short name T233
Test name
Test status
Simulation time 2263876194 ps
CPU time 13.01 seconds
Started Oct 02 07:53:15 PM UTC 24
Finished Oct 02 07:53:29 PM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082771944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1082771944
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/19.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/2.hmac_alert_test.751889769
Short name T64
Test name
Test status
Simulation time 28860415 ps
CPU time 0.98 seconds
Started Oct 02 07:44:51 PM UTC 24
Finished Oct 02 07:44:53 PM UTC 24
Peak memory 207400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751889769 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.751889769
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/2.hmac_back_pressure.3573128224
Short name T14
Test name
Test status
Simulation time 3084391460 ps
CPU time 88.75 seconds
Started Oct 02 07:44:21 PM UTC 24
Finished Oct 02 07:45:51 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573128224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3573128224
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/2.hmac_burst_wr.2042801161
Short name T11
Test name
Test status
Simulation time 484752920 ps
CPU time 34.31 seconds
Started Oct 02 07:44:26 PM UTC 24
Finished Oct 02 07:45:02 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042801161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2042801161
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/2.hmac_datapath_stress.2326734083
Short name T410
Test name
Test status
Simulation time 6836609647 ps
CPU time 1600.16 seconds
Started Oct 02 07:44:22 PM UTC 24
Finished Oct 02 08:11:22 PM UTC 24
Peak memory 771688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326734083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2326734083
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/2.hmac_error.2956850535
Short name T179
Test name
Test status
Simulation time 2129570225 ps
CPU time 136.63 seconds
Started Oct 02 07:44:28 PM UTC 24
Finished Oct 02 07:46:48 PM UTC 24
Peak memory 210292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956850535 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2956850535
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/2.hmac_long_msg.1648877883
Short name T25
Test name
Test status
Simulation time 1280794286 ps
CPU time 25.47 seconds
Started Oct 02 07:44:16 PM UTC 24
Finished Oct 02 07:44:43 PM UTC 24
Peak memory 210280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648877883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1648877883
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/2.hmac_sec_cm.1206003310
Short name T65
Test name
Test status
Simulation time 187751921 ps
CPU time 1.1 seconds
Started Oct 02 07:44:51 PM UTC 24
Finished Oct 02 07:44:53 PM UTC 24
Peak memory 238204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206003310 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1206003310
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/2.hmac_smoke.1852894599
Short name T8
Test name
Test status
Simulation time 641971714 ps
CPU time 19.61 seconds
Started Oct 02 07:44:15 PM UTC 24
Finished Oct 02 07:44:36 PM UTC 24
Peak memory 210472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852894599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1852894599
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/2.hmac_stress_all.3009831553
Short name T28
Test name
Test status
Simulation time 37877271 ps
CPU time 1.02 seconds
Started Oct 02 07:44:44 PM UTC 24
Finished Oct 02 07:44:46 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009831553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3009831553
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/2.hmac_test_hmac256_vectors.2164739528
Short name T41
Test name
Test status
Simulation time 10042917554 ps
CPU time 97.11 seconds
Started Oct 02 07:44:37 PM UTC 24
Finished Oct 02 07:46:17 PM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164739528 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.2164739528
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/2.hmac_test_hmac384_vectors.2662206569
Short name T37
Test name
Test status
Simulation time 22443381551 ps
CPU time 76.55 seconds
Started Oct 02 07:44:41 PM UTC 24
Finished Oct 02 07:46:00 PM UTC 24
Peak memory 210476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662206569 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.2662206569
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/2.hmac_test_hmac512_vectors.398751636
Short name T39
Test name
Test status
Simulation time 12665432840 ps
CPU time 89.7 seconds
Started Oct 02 07:44:41 PM UTC 24
Finished Oct 02 07:46:13 PM UTC 24
Peak memory 210804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398751636 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.398751636
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/2.hmac_test_sha256_vectors.3567436085
Short name T269
Test name
Test status
Simulation time 568343711844 ps
CPU time 723.08 seconds
Started Oct 02 07:44:32 PM UTC 24
Finished Oct 02 07:56:44 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567436085 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3567436085
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/2.hmac_test_sha384_vectors.2740961472
Short name T488
Test name
Test status
Simulation time 37072248231 ps
CPU time 2214.26 seconds
Started Oct 02 07:44:34 PM UTC 24
Finished Oct 02 08:21:53 PM UTC 24
Peak memory 224724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740961472 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.2740961472
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/2.hmac_test_sha512_vectors.3341455117
Short name T510
Test name
Test status
Simulation time 875899558147 ps
CPU time 2964.53 seconds
Started Oct 02 07:44:37 PM UTC 24
Finished Oct 02 08:34:37 PM UTC 24
Peak memory 224624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341455117 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.3341455117
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/2.hmac_wipe_secret.4257048954
Short name T17
Test name
Test status
Simulation time 4006592246 ps
CPU time 71.66 seconds
Started Oct 02 07:44:31 PM UTC 24
Finished Oct 02 07:45:44 PM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257048954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.4257048954
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/2.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/20.hmac_alert_test.3789729507
Short name T236
Test name
Test status
Simulation time 36404943 ps
CPU time 0.89 seconds
Started Oct 02 07:53:32 PM UTC 24
Finished Oct 02 07:53:34 PM UTC 24
Peak memory 207284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789729507 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.3789729507
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/20.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/20.hmac_back_pressure.2069494157
Short name T245
Test name
Test status
Simulation time 3798192815 ps
CPU time 62.25 seconds
Started Oct 02 07:53:24 PM UTC 24
Finished Oct 02 07:54:28 PM UTC 24
Peak memory 210448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069494157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2069494157
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/20.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/20.hmac_burst_wr.2558005502
Short name T159
Test name
Test status
Simulation time 649261529 ps
CPU time 7.07 seconds
Started Oct 02 07:53:26 PM UTC 24
Finished Oct 02 07:53:34 PM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558005502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2558005502
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/20.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/20.hmac_datapath_stress.2429429323
Short name T502
Test name
Test status
Simulation time 66060796208 ps
CPU time 2280.06 seconds
Started Oct 02 07:53:24 PM UTC 24
Finished Oct 02 08:31:49 PM UTC 24
Peak memory 816512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429429323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2429429323
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/20.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/20.hmac_error.4043874502
Short name T255
Test name
Test status
Simulation time 7657698300 ps
CPU time 113.74 seconds
Started Oct 02 07:53:28 PM UTC 24
Finished Oct 02 07:55:24 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043874502 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.4043874502
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/20.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/20.hmac_long_msg.1703651393
Short name T253
Test name
Test status
Simulation time 7801079606 ps
CPU time 108.78 seconds
Started Oct 02 07:53:22 PM UTC 24
Finished Oct 02 07:55:13 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703651393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1703651393
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/20.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/20.hmac_smoke.3642915163
Short name T232
Test name
Test status
Simulation time 563747291 ps
CPU time 7.33 seconds
Started Oct 02 07:53:21 PM UTC 24
Finished Oct 02 07:53:29 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642915163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3642915163
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/20.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/20.hmac_stress_all.3240494407
Short name T518
Test name
Test status
Simulation time 102593233209 ps
CPU time 3431 seconds
Started Oct 02 07:53:32 PM UTC 24
Finished Oct 02 08:51:22 PM UTC 24
Peak memory 855168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240494407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3240494407
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/20.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/20.hmac_wipe_secret.1070115313
Short name T140
Test name
Test status
Simulation time 1542243741 ps
CPU time 73.18 seconds
Started Oct 02 07:53:30 PM UTC 24
Finished Oct 02 07:54:45 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070115313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1070115313
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/20.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/21.hmac_alert_test.91727700
Short name T241
Test name
Test status
Simulation time 15372549 ps
CPU time 0.9 seconds
Started Oct 02 07:54:04 PM UTC 24
Finished Oct 02 07:54:06 PM UTC 24
Peak memory 207396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91727700 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.91727700
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/21.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/21.hmac_back_pressure.1559204338
Short name T239
Test name
Test status
Simulation time 2661046566 ps
CPU time 22.39 seconds
Started Oct 02 07:53:38 PM UTC 24
Finished Oct 02 07:54:01 PM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559204338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1559204338
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/21.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/21.hmac_burst_wr.1987741855
Short name T240
Test name
Test status
Simulation time 1902763375 ps
CPU time 14.71 seconds
Started Oct 02 07:53:48 PM UTC 24
Finished Oct 02 07:54:04 PM UTC 24
Peak memory 210644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987741855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1987741855
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/21.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/21.hmac_datapath_stress.3740173420
Short name T336
Test name
Test status
Simulation time 3709389664 ps
CPU time 633.94 seconds
Started Oct 02 07:53:38 PM UTC 24
Finished Oct 02 08:04:19 PM UTC 24
Peak memory 665144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740173420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3740173420
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/21.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/21.hmac_error.2529053145
Short name T254
Test name
Test status
Simulation time 49966949513 ps
CPU time 80.3 seconds
Started Oct 02 07:53:58 PM UTC 24
Finished Oct 02 07:55:21 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529053145 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2529053145
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/21.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/21.hmac_long_msg.1279345600
Short name T252
Test name
Test status
Simulation time 12468932027 ps
CPU time 91.86 seconds
Started Oct 02 07:53:36 PM UTC 24
Finished Oct 02 07:55:10 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279345600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1279345600
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/21.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/21.hmac_smoke.2479337404
Short name T237
Test name
Test status
Simulation time 3445647743 ps
CPU time 9.8 seconds
Started Oct 02 07:53:36 PM UTC 24
Finished Oct 02 07:53:47 PM UTC 24
Peak memory 210472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479337404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2479337404
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/21.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/21.hmac_stress_all.3388493329
Short name T338
Test name
Test status
Simulation time 5119649233 ps
CPU time 624.2 seconds
Started Oct 02 07:54:03 PM UTC 24
Finished Oct 02 08:04:35 PM UTC 24
Peak memory 482616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388493329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3388493329
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/21.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/21.hmac_wipe_secret.4192568945
Short name T107
Test name
Test status
Simulation time 16188591864 ps
CPU time 58.17 seconds
Started Oct 02 07:54:02 PM UTC 24
Finished Oct 02 07:55:02 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192568945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.4192568945
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/21.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/22.hmac_alert_test.1355983262
Short name T250
Test name
Test status
Simulation time 14113213 ps
CPU time 0.86 seconds
Started Oct 02 07:54:55 PM UTC 24
Finished Oct 02 07:54:57 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355983262 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1355983262
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/22.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/22.hmac_back_pressure.3318287606
Short name T248
Test name
Test status
Simulation time 1184448477 ps
CPU time 25.4 seconds
Started Oct 02 07:54:25 PM UTC 24
Finished Oct 02 07:54:52 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318287606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3318287606
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/22.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/22.hmac_burst_wr.3109859081
Short name T261
Test name
Test status
Simulation time 9276530243 ps
CPU time 76.27 seconds
Started Oct 02 07:54:31 PM UTC 24
Finished Oct 02 07:55:50 PM UTC 24
Peak memory 219104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109859081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3109859081
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/22.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/22.hmac_datapath_stress.160852591
Short name T382
Test name
Test status
Simulation time 4039001508 ps
CPU time 834.71 seconds
Started Oct 02 07:54:30 PM UTC 24
Finished Oct 02 08:08:34 PM UTC 24
Peak memory 726360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160852591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.160852591
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/22.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/22.hmac_error.2081956984
Short name T256
Test name
Test status
Simulation time 4016342611 ps
CPU time 59.76 seconds
Started Oct 02 07:54:35 PM UTC 24
Finished Oct 02 07:55:36 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081956984 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2081956984
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/22.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/22.hmac_long_msg.253095328
Short name T268
Test name
Test status
Simulation time 5156019010 ps
CPU time 130.86 seconds
Started Oct 02 07:54:25 PM UTC 24
Finished Oct 02 07:56:39 PM UTC 24
Peak memory 219268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253095328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.253095328
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/22.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/22.hmac_smoke.3756981997
Short name T243
Test name
Test status
Simulation time 572040799 ps
CPU time 16.21 seconds
Started Oct 02 07:54:07 PM UTC 24
Finished Oct 02 07:54:25 PM UTC 24
Peak memory 210580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756981997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3756981997
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/22.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/22.hmac_stress_all.959971761
Short name T513
Test name
Test status
Simulation time 489139966363 ps
CPU time 3023.63 seconds
Started Oct 02 07:54:55 PM UTC 24
Finished Oct 02 08:45:52 PM UTC 24
Peak memory 765260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959971761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.959971761
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/22.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/22.hmac_wipe_secret.127782822
Short name T263
Test name
Test status
Simulation time 4028603279 ps
CPU time 82.29 seconds
Started Oct 02 07:54:46 PM UTC 24
Finished Oct 02 07:56:11 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127782822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.127782822
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/22.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/23.hmac_alert_test.3587477690
Short name T258
Test name
Test status
Simulation time 26077716 ps
CPU time 0.74 seconds
Started Oct 02 07:55:37 PM UTC 24
Finished Oct 02 07:55:39 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587477690 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3587477690
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/23.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/23.hmac_back_pressure.1744649200
Short name T257
Test name
Test status
Simulation time 534939805 ps
CPU time 34.19 seconds
Started Oct 02 07:55:03 PM UTC 24
Finished Oct 02 07:55:39 PM UTC 24
Peak memory 210308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744649200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1744649200
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/23.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/23.hmac_burst_wr.3070008272
Short name T141
Test name
Test status
Simulation time 502045573 ps
CPU time 35.41 seconds
Started Oct 02 07:55:12 PM UTC 24
Finished Oct 02 07:55:49 PM UTC 24
Peak memory 210628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070008272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3070008272
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/23.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/23.hmac_datapath_stress.2444903328
Short name T337
Test name
Test status
Simulation time 5341355534 ps
CPU time 549.35 seconds
Started Oct 02 07:55:12 PM UTC 24
Finished Oct 02 08:04:28 PM UTC 24
Peak memory 738604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444903328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2444903328
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/23.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/23.hmac_error.2408471993
Short name T293
Test name
Test status
Simulation time 27985804830 ps
CPU time 248.52 seconds
Started Oct 02 07:55:15 PM UTC 24
Finished Oct 02 07:59:27 PM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408471993 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2408471993
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/23.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/23.hmac_long_msg.4060638392
Short name T279
Test name
Test status
Simulation time 14034432835 ps
CPU time 149.69 seconds
Started Oct 02 07:54:59 PM UTC 24
Finished Oct 02 07:57:31 PM UTC 24
Peak memory 221148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060638392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.4060638392
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/23.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/23.hmac_smoke.2465660688
Short name T251
Test name
Test status
Simulation time 332721101 ps
CPU time 11.27 seconds
Started Oct 02 07:54:58 PM UTC 24
Finished Oct 02 07:55:10 PM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465660688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2465660688
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/23.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/23.hmac_stress_all.1223184382
Short name T505
Test name
Test status
Simulation time 297748106210 ps
CPU time 2268.05 seconds
Started Oct 02 07:55:25 PM UTC 24
Finished Oct 02 08:33:39 PM UTC 24
Peak memory 785664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223184382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1223184382
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/23.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/23.hmac_wipe_secret.1598104271
Short name T108
Test name
Test status
Simulation time 200714041 ps
CPU time 15.18 seconds
Started Oct 02 07:55:22 PM UTC 24
Finished Oct 02 07:55:40 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598104271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1598104271
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/23.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/24.hmac_alert_test.2579671886
Short name T264
Test name
Test status
Simulation time 32552692 ps
CPU time 0.86 seconds
Started Oct 02 07:56:12 PM UTC 24
Finished Oct 02 07:56:14 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579671886 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2579671886
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/24.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/24.hmac_back_pressure.3669831654
Short name T267
Test name
Test status
Simulation time 1694108311 ps
CPU time 54.63 seconds
Started Oct 02 07:55:41 PM UTC 24
Finished Oct 02 07:56:37 PM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669831654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3669831654
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/24.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/24.hmac_burst_wr.3192915015
Short name T266
Test name
Test status
Simulation time 6657325392 ps
CPU time 29.76 seconds
Started Oct 02 07:55:49 PM UTC 24
Finished Oct 02 07:56:20 PM UTC 24
Peak memory 210528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192915015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3192915015
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/24.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/24.hmac_datapath_stress.1057933206
Short name T391
Test name
Test status
Simulation time 16275967118 ps
CPU time 787.53 seconds
Started Oct 02 07:55:43 PM UTC 24
Finished Oct 02 08:09:00 PM UTC 24
Peak memory 702004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057933206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1057933206
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/24.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/24.hmac_error.4112713292
Short name T282
Test name
Test status
Simulation time 9486415672 ps
CPU time 109.06 seconds
Started Oct 02 07:55:50 PM UTC 24
Finished Oct 02 07:57:41 PM UTC 24
Peak memory 210428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112713292 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.4112713292
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/24.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/24.hmac_long_msg.3132699526
Short name T274
Test name
Test status
Simulation time 10061132338 ps
CPU time 82.12 seconds
Started Oct 02 07:55:40 PM UTC 24
Finished Oct 02 07:57:04 PM UTC 24
Peak memory 210540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132699526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3132699526
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/24.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/24.hmac_smoke.3064263855
Short name T262
Test name
Test status
Simulation time 1041418318 ps
CPU time 10.02 seconds
Started Oct 02 07:55:40 PM UTC 24
Finished Oct 02 07:55:51 PM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064263855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3064263855
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/24.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/24.hmac_stress_all.2271129280
Short name T35
Test name
Test status
Simulation time 13800132110 ps
CPU time 1608.19 seconds
Started Oct 02 07:55:52 PM UTC 24
Finished Oct 02 08:22:58 PM UTC 24
Peak memory 744796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271129280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2271129280
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/24.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/24.hmac_wipe_secret.1095769882
Short name T275
Test name
Test status
Simulation time 16764415923 ps
CPU time 75.34 seconds
Started Oct 02 07:55:50 PM UTC 24
Finished Oct 02 07:57:07 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095769882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1095769882
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/24.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/25.hmac_alert_test.3621545239
Short name T272
Test name
Test status
Simulation time 40278786 ps
CPU time 0.93 seconds
Started Oct 02 07:56:50 PM UTC 24
Finished Oct 02 07:56:52 PM UTC 24
Peak memory 207400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621545239 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3621545239
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/25.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/25.hmac_back_pressure.929037593
Short name T271
Test name
Test status
Simulation time 364421819 ps
CPU time 25.38 seconds
Started Oct 02 07:56:21 PM UTC 24
Finished Oct 02 07:56:47 PM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929037593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.929037593
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/25.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/25.hmac_burst_wr.3556644848
Short name T278
Test name
Test status
Simulation time 13005599234 ps
CPU time 43.51 seconds
Started Oct 02 07:56:40 PM UTC 24
Finished Oct 02 07:57:25 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556644848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3556644848
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/25.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/25.hmac_datapath_stress.2769829658
Short name T270
Test name
Test status
Simulation time 51223760 ps
CPU time 3.93 seconds
Started Oct 02 07:56:40 PM UTC 24
Finished Oct 02 07:56:45 PM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769829658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2769829658
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/25.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/25.hmac_error.4139256467
Short name T311
Test name
Test status
Simulation time 110157981442 ps
CPU time 281 seconds
Started Oct 02 07:56:48 PM UTC 24
Finished Oct 02 08:01:33 PM UTC 24
Peak memory 210508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139256467 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.4139256467
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/25.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/25.hmac_long_msg.2860093429
Short name T296
Test name
Test status
Simulation time 15395225861 ps
CPU time 210.82 seconds
Started Oct 02 07:56:19 PM UTC 24
Finished Oct 02 07:59:53 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860093429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2860093429
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/25.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/25.hmac_smoke.1754730384
Short name T265
Test name
Test status
Simulation time 22093597 ps
CPU time 1.28 seconds
Started Oct 02 07:56:15 PM UTC 24
Finished Oct 02 07:56:17 PM UTC 24
Peak memory 209048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754730384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1754730384
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/25.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/25.hmac_stress_all.361041283
Short name T36
Test name
Test status
Simulation time 94374675743 ps
CPU time 2205.84 seconds
Started Oct 02 07:56:50 PM UTC 24
Finished Oct 02 08:34:03 PM UTC 24
Peak memory 722304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361041283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.361041283
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/25.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/25.hmac_wipe_secret.322900484
Short name T280
Test name
Test status
Simulation time 8622741236 ps
CPU time 47.03 seconds
Started Oct 02 07:56:49 PM UTC 24
Finished Oct 02 07:57:38 PM UTC 24
Peak memory 210480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322900484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.322900484
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/25.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/26.hmac_alert_test.3198707212
Short name T281
Test name
Test status
Simulation time 18900993 ps
CPU time 0.95 seconds
Started Oct 02 07:57:39 PM UTC 24
Finished Oct 02 07:57:41 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198707212 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3198707212
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/26.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/26.hmac_back_pressure.3662074234
Short name T286
Test name
Test status
Simulation time 2673914940 ps
CPU time 61.01 seconds
Started Oct 02 07:57:05 PM UTC 24
Finished Oct 02 07:58:08 PM UTC 24
Peak memory 210516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662074234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3662074234
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/26.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/26.hmac_burst_wr.2776030842
Short name T287
Test name
Test status
Simulation time 2010102460 ps
CPU time 56.63 seconds
Started Oct 02 07:57:15 PM UTC 24
Finished Oct 02 07:58:13 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776030842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2776030842
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/26.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/26.hmac_datapath_stress.3953347643
Short name T503
Test name
Test status
Simulation time 31844247920 ps
CPU time 2120.8 seconds
Started Oct 02 07:57:09 PM UTC 24
Finished Oct 02 08:32:53 PM UTC 24
Peak memory 763212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953347643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3953347643
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/26.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/26.hmac_error.1399690912
Short name T302
Test name
Test status
Simulation time 24917927990 ps
CPU time 160.25 seconds
Started Oct 02 07:57:19 PM UTC 24
Finished Oct 02 08:00:02 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399690912 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1399690912
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/26.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/26.hmac_long_msg.868872278
Short name T289
Test name
Test status
Simulation time 9546054931 ps
CPU time 110.9 seconds
Started Oct 02 07:56:58 PM UTC 24
Finished Oct 02 07:58:51 PM UTC 24
Peak memory 219276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868872278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.868872278
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/26.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/26.hmac_smoke.1751279499
Short name T276
Test name
Test status
Simulation time 1223998735 ps
CPU time 20.65 seconds
Started Oct 02 07:56:53 PM UTC 24
Finished Oct 02 07:57:15 PM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751279499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1751279499
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/26.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/26.hmac_stress_all.334548950
Short name T486
Test name
Test status
Simulation time 11339328144 ps
CPU time 1360.64 seconds
Started Oct 02 07:57:33 PM UTC 24
Finished Oct 02 08:20:28 PM UTC 24
Peak memory 754996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334548950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.334548950
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/26.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/26.hmac_wipe_secret.158142236
Short name T299
Test name
Test status
Simulation time 81271654963 ps
CPU time 148.89 seconds
Started Oct 02 07:57:26 PM UTC 24
Finished Oct 02 07:59:58 PM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158142236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.158142236
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/26.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/27.hmac_alert_test.3401299440
Short name T290
Test name
Test status
Simulation time 38285492 ps
CPU time 0.88 seconds
Started Oct 02 07:58:53 PM UTC 24
Finished Oct 02 07:58:55 PM UTC 24
Peak memory 207400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401299440 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3401299440
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/27.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/27.hmac_back_pressure.3478394997
Short name T31
Test name
Test status
Simulation time 989089884 ps
CPU time 62.96 seconds
Started Oct 02 07:57:50 PM UTC 24
Finished Oct 02 07:58:54 PM UTC 24
Peak memory 210400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478394997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3478394997
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/27.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/27.hmac_burst_wr.276209758
Short name T288
Test name
Test status
Simulation time 86861952 ps
CPU time 2.5 seconds
Started Oct 02 07:58:11 PM UTC 24
Finished Oct 02 07:58:14 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276209758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.276209758
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/27.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/27.hmac_datapath_stress.858613448
Short name T484
Test name
Test status
Simulation time 11087246108 ps
CPU time 1320.78 seconds
Started Oct 02 07:58:02 PM UTC 24
Finished Oct 02 08:20:19 PM UTC 24
Peak memory 712036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858613448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.858613448
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/27.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/27.hmac_error.349970456
Short name T313
Test name
Test status
Simulation time 18235854236 ps
CPU time 209.99 seconds
Started Oct 02 07:58:11 PM UTC 24
Finished Oct 02 08:01:44 PM UTC 24
Peak memory 210740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349970456 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.349970456
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/27.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/27.hmac_long_msg.1795793953
Short name T308
Test name
Test status
Simulation time 49514973979 ps
CPU time 195.41 seconds
Started Oct 02 07:57:43 PM UTC 24
Finished Oct 02 08:01:01 PM UTC 24
Peak memory 210488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795793953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1795793953
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/27.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/27.hmac_smoke.3751600775
Short name T283
Test name
Test status
Simulation time 215555509 ps
CPU time 5.27 seconds
Started Oct 02 07:57:43 PM UTC 24
Finished Oct 02 07:57:49 PM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751600775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3751600775
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/27.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/27.hmac_stress_all.685012910
Short name T522
Test name
Test status
Simulation time 205130906373 ps
CPU time 5201.02 seconds
Started Oct 02 07:58:15 PM UTC 24
Finished Oct 02 09:25:50 PM UTC 24
Peak memory 867780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685012910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.685012910
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/27.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/27.hmac_wipe_secret.2188087553
Short name T304
Test name
Test status
Simulation time 1634800656 ps
CPU time 119.83 seconds
Started Oct 02 07:58:15 PM UTC 24
Finished Oct 02 08:00:17 PM UTC 24
Peak memory 210320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188087553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2188087553
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/27.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/28.hmac_alert_test.38741440
Short name T301
Test name
Test status
Simulation time 14637368 ps
CPU time 0.89 seconds
Started Oct 02 08:00:00 PM UTC 24
Finished Oct 02 08:00:02 PM UTC 24
Peak memory 205348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38741440 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.38741440
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/28.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/28.hmac_back_pressure.2004101258
Short name T305
Test name
Test status
Simulation time 5041882936 ps
CPU time 94.51 seconds
Started Oct 02 07:59:10 PM UTC 24
Finished Oct 02 08:00:47 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004101258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2004101258
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/28.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/28.hmac_burst_wr.1679451934
Short name T300
Test name
Test status
Simulation time 15371673220 ps
CPU time 30.45 seconds
Started Oct 02 07:59:30 PM UTC 24
Finished Oct 02 08:00:01 PM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679451934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1679451934
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/28.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/28.hmac_datapath_stress.2376667503
Short name T407
Test name
Test status
Simulation time 3404750158 ps
CPU time 709.6 seconds
Started Oct 02 07:59:12 PM UTC 24
Finished Oct 02 08:11:10 PM UTC 24
Peak memory 763464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376667503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2376667503
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/28.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/28.hmac_error.2472577680
Short name T295
Test name
Test status
Simulation time 442397007 ps
CPU time 7.46 seconds
Started Oct 02 07:59:34 PM UTC 24
Finished Oct 02 07:59:43 PM UTC 24
Peak memory 210244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472577680 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2472577680
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/28.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/28.hmac_long_msg.962639974
Short name T298
Test name
Test status
Simulation time 9175637234 ps
CPU time 59.11 seconds
Started Oct 02 07:58:56 PM UTC 24
Finished Oct 02 07:59:57 PM UTC 24
Peak memory 219360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962639974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.962639974
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/28.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/28.hmac_smoke.2870068825
Short name T292
Test name
Test status
Simulation time 558688818 ps
CPU time 14.26 seconds
Started Oct 02 07:58:56 PM UTC 24
Finished Oct 02 07:59:12 PM UTC 24
Peak memory 210484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870068825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2870068825
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/28.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/28.hmac_stress_all.1062157958
Short name T367
Test name
Test status
Simulation time 46983791705 ps
CPU time 406.95 seconds
Started Oct 02 07:59:56 PM UTC 24
Finished Oct 02 08:06:48 PM UTC 24
Peak memory 630372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062157958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.1062157958
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/28.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/28.hmac_wipe_secret.3150561285
Short name T315
Test name
Test status
Simulation time 2564244494 ps
CPU time 128.96 seconds
Started Oct 02 07:59:43 PM UTC 24
Finished Oct 02 08:01:55 PM UTC 24
Peak memory 210476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150561285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3150561285
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/28.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/29.hmac_alert_test.1043290303
Short name T307
Test name
Test status
Simulation time 13838556 ps
CPU time 0.9 seconds
Started Oct 02 08:00:55 PM UTC 24
Finished Oct 02 08:00:57 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043290303 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1043290303
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/29.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/29.hmac_back_pressure.4018008631
Short name T30
Test name
Test status
Simulation time 4426210516 ps
CPU time 83.11 seconds
Started Oct 02 08:00:03 PM UTC 24
Finished Oct 02 08:01:30 PM UTC 24
Peak memory 210528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018008631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.4018008631
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/29.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/29.hmac_burst_wr.2801604421
Short name T306
Test name
Test status
Simulation time 3340329805 ps
CPU time 45.99 seconds
Started Oct 02 08:00:06 PM UTC 24
Finished Oct 02 08:00:54 PM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801604421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2801604421
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/29.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/29.hmac_datapath_stress.320232474
Short name T321
Test name
Test status
Simulation time 700396742 ps
CPU time 138.94 seconds
Started Oct 02 08:00:06 PM UTC 24
Finished Oct 02 08:02:28 PM UTC 24
Peak memory 425152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320232474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.320232474
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/29.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/29.hmac_error.1107549838
Short name T310
Test name
Test status
Simulation time 9830265963 ps
CPU time 61.62 seconds
Started Oct 02 08:00:10 PM UTC 24
Finished Oct 02 08:01:14 PM UTC 24
Peak memory 210636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107549838 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1107549838
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/29.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/29.hmac_long_msg.1120865371
Short name T320
Test name
Test status
Simulation time 1783711988 ps
CPU time 138.25 seconds
Started Oct 02 08:00:01 PM UTC 24
Finished Oct 02 08:02:26 PM UTC 24
Peak memory 210388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120865371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1120865371
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/29.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/29.hmac_smoke.2137159241
Short name T303
Test name
Test status
Simulation time 287306992 ps
CPU time 8.4 seconds
Started Oct 02 08:00:00 PM UTC 24
Finished Oct 02 08:00:09 PM UTC 24
Peak memory 210480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137159241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2137159241
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/29.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/29.hmac_stress_all.1020437567
Short name T437
Test name
Test status
Simulation time 12513844266 ps
CPU time 808.38 seconds
Started Oct 02 08:00:48 PM UTC 24
Finished Oct 02 08:14:26 PM UTC 24
Peak memory 221056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020437567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1020437567
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/29.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/29.hmac_wipe_secret.2093533608
Short name T324
Test name
Test status
Simulation time 2371351547 ps
CPU time 140.33 seconds
Started Oct 02 08:00:18 PM UTC 24
Finished Oct 02 08:02:41 PM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093533608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2093533608
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/29.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/3.hmac_alert_test.2430243335
Short name T174
Test name
Test status
Simulation time 24569380 ps
CPU time 0.94 seconds
Started Oct 02 07:45:14 PM UTC 24
Finished Oct 02 07:45:16 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430243335 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2430243335
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/3.hmac_back_pressure.3927690434
Short name T15
Test name
Test status
Simulation time 899612442 ps
CPU time 61.18 seconds
Started Oct 02 07:44:54 PM UTC 24
Finished Oct 02 07:45:57 PM UTC 24
Peak memory 210360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927690434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3927690434
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/3.hmac_burst_wr.4060260072
Short name T24
Test name
Test status
Simulation time 8720479582 ps
CPU time 55.91 seconds
Started Oct 02 07:44:55 PM UTC 24
Finished Oct 02 07:45:52 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060260072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.4060260072
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/3.hmac_datapath_stress.222607945
Short name T244
Test name
Test status
Simulation time 13696740261 ps
CPU time 565.99 seconds
Started Oct 02 07:44:55 PM UTC 24
Finished Oct 02 07:54:28 PM UTC 24
Peak memory 712064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222607945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.222607945
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/3.hmac_error.682008120
Short name T61
Test name
Test status
Simulation time 2540067798 ps
CPU time 40.44 seconds
Started Oct 02 07:44:58 PM UTC 24
Finished Oct 02 07:45:40 PM UTC 24
Peak memory 210528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682008120 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.682008120
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/3.hmac_long_msg.2925793658
Short name T176
Test name
Test status
Simulation time 5792437502 ps
CPU time 87.66 seconds
Started Oct 02 07:44:53 PM UTC 24
Finished Oct 02 07:46:23 PM UTC 24
Peak memory 210756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925793658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2925793658
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/3.hmac_sec_cm.582470742
Short name T66
Test name
Test status
Simulation time 330965471 ps
CPU time 1.69 seconds
Started Oct 02 07:45:14 PM UTC 24
Finished Oct 02 07:45:16 PM UTC 24
Peak memory 238208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582470742 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.582470742
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/3.hmac_stress_all.696820917
Short name T44
Test name
Test status
Simulation time 20064893897 ps
CPU time 68.27 seconds
Started Oct 02 07:45:10 PM UTC 24
Finished Oct 02 07:46:21 PM UTC 24
Peak memory 210540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696820917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.696820917
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/3.hmac_test_hmac256_vectors.4235779517
Short name T177
Test name
Test status
Simulation time 17879150038 ps
CPU time 78.68 seconds
Started Oct 02 07:45:07 PM UTC 24
Finished Oct 02 07:46:28 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235779517 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.4235779517
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/3.hmac_test_hmac384_vectors.1052239776
Short name T180
Test name
Test status
Simulation time 9970759272 ps
CPU time 98.42 seconds
Started Oct 02 07:45:09 PM UTC 24
Finished Oct 02 07:46:50 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052239776 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.1052239776
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/3.hmac_test_hmac512_vectors.1148026409
Short name T181
Test name
Test status
Simulation time 5682319242 ps
CPU time 98.88 seconds
Started Oct 02 07:45:10 PM UTC 24
Finished Oct 02 07:46:51 PM UTC 24
Peak memory 210448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148026409 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.1148026409
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/3.hmac_test_sha256_vectors.4232069503
Short name T247
Test name
Test status
Simulation time 40546396079 ps
CPU time 581.67 seconds
Started Oct 02 07:45:03 PM UTC 24
Finished Oct 02 07:54:52 PM UTC 24
Peak memory 210380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232069503 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.4232069503
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/3.hmac_test_sha384_vectors.3941875551
Short name T497
Test name
Test status
Simulation time 170455446452 ps
CPU time 2570.47 seconds
Started Oct 02 07:45:03 PM UTC 24
Finished Oct 02 08:28:26 PM UTC 24
Peak memory 224688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941875551 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.3941875551
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/3.hmac_test_sha512_vectors.2973519115
Short name T506
Test name
Test status
Simulation time 1732376396461 ps
CPU time 2895.54 seconds
Started Oct 02 07:45:05 PM UTC 24
Finished Oct 02 08:33:54 PM UTC 24
Peak memory 230612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973519115 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2973519115
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/3.hmac_wipe_secret.2781005604
Short name T29
Test name
Test status
Simulation time 472423479 ps
CPU time 8.91 seconds
Started Oct 02 07:44:59 PM UTC 24
Finished Oct 02 07:45:09 PM UTC 24
Peak memory 210276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781005604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2781005604
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/3.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/30.hmac_alert_test.4115976253
Short name T316
Test name
Test status
Simulation time 17571129 ps
CPU time 0.92 seconds
Started Oct 02 08:01:54 PM UTC 24
Finished Oct 02 08:01:56 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115976253 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.4115976253
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/30.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/30.hmac_back_pressure.3044030013
Short name T323
Test name
Test status
Simulation time 1115191918 ps
CPU time 91.08 seconds
Started Oct 02 08:01:07 PM UTC 24
Finished Oct 02 08:02:41 PM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044030013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3044030013
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/30.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/30.hmac_burst_wr.1721875980
Short name T317
Test name
Test status
Simulation time 1969208272 ps
CPU time 37.55 seconds
Started Oct 02 08:01:32 PM UTC 24
Finished Oct 02 08:02:11 PM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721875980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1721875980
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/30.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/30.hmac_datapath_stress.379898874
Short name T438
Test name
Test status
Simulation time 17971068948 ps
CPU time 794.89 seconds
Started Oct 02 08:01:16 PM UTC 24
Finished Oct 02 08:14:39 PM UTC 24
Peak memory 738588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379898874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.379898874
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/30.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/30.hmac_error.901579957
Short name T312
Test name
Test status
Simulation time 103687875 ps
CPU time 4.15 seconds
Started Oct 02 08:01:35 PM UTC 24
Finished Oct 02 08:01:41 PM UTC 24
Peak memory 210276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901579957 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.901579957
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/30.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/30.hmac_long_msg.3411306217
Short name T335
Test name
Test status
Simulation time 11997114754 ps
CPU time 191.19 seconds
Started Oct 02 08:01:03 PM UTC 24
Finished Oct 02 08:04:18 PM UTC 24
Peak memory 219008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411306217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3411306217
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/30.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/30.hmac_smoke.2289129031
Short name T309
Test name
Test status
Simulation time 1247457014 ps
CPU time 7.56 seconds
Started Oct 02 08:00:58 PM UTC 24
Finished Oct 02 08:01:07 PM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289129031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2289129031
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/30.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/30.hmac_stress_all.534533092
Short name T388
Test name
Test status
Simulation time 29567772073 ps
CPU time 421.78 seconds
Started Oct 02 08:01:46 PM UTC 24
Finished Oct 02 08:08:54 PM UTC 24
Peak memory 210508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534533092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.534533092
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/30.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/30.hmac_wipe_secret.720530353
Short name T332
Test name
Test status
Simulation time 5671844314 ps
CPU time 117.18 seconds
Started Oct 02 08:01:41 PM UTC 24
Finished Oct 02 08:03:41 PM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720530353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.720530353
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/30.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/31.hmac_alert_test.3416225697
Short name T325
Test name
Test status
Simulation time 24397510 ps
CPU time 0.87 seconds
Started Oct 02 08:02:42 PM UTC 24
Finished Oct 02 08:02:44 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416225697 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3416225697
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/31.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/31.hmac_back_pressure.3711652362
Short name T327
Test name
Test status
Simulation time 569080132 ps
CPU time 40.77 seconds
Started Oct 02 08:02:14 PM UTC 24
Finished Oct 02 08:02:56 PM UTC 24
Peak memory 210432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711652362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3711652362
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/31.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/31.hmac_burst_wr.2005144293
Short name T330
Test name
Test status
Simulation time 2940111708 ps
CPU time 72.99 seconds
Started Oct 02 08:02:20 PM UTC 24
Finished Oct 02 08:03:35 PM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005144293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2005144293
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/31.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/31.hmac_datapath_stress.415946043
Short name T455
Test name
Test status
Simulation time 8499582557 ps
CPU time 855.07 seconds
Started Oct 02 08:02:14 PM UTC 24
Finished Oct 02 08:16:39 PM UTC 24
Peak memory 720172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415946043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.415946043
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/31.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/31.hmac_error.1687460561
Short name T339
Test name
Test status
Simulation time 6539844227 ps
CPU time 125.58 seconds
Started Oct 02 08:02:28 PM UTC 24
Finished Oct 02 08:04:36 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687460561 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1687460561
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/31.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/31.hmac_long_msg.4071176283
Short name T347
Test name
Test status
Simulation time 8324986990 ps
CPU time 192.16 seconds
Started Oct 02 08:01:57 PM UTC 24
Finished Oct 02 08:05:13 PM UTC 24
Peak memory 219328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071176283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.4071176283
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/31.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/31.hmac_smoke.1821248418
Short name T319
Test name
Test status
Simulation time 3708246726 ps
CPU time 21.13 seconds
Started Oct 02 08:01:57 PM UTC 24
Finished Oct 02 08:02:19 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821248418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1821248418
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/31.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/31.hmac_stress_all.893513004
Short name T145
Test name
Test status
Simulation time 12431686600 ps
CPU time 266.15 seconds
Started Oct 02 08:02:33 PM UTC 24
Finished Oct 02 08:07:03 PM UTC 24
Peak memory 218972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893513004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.893513004
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/31.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/31.hmac_wipe_secret.3894071009
Short name T110
Test name
Test status
Simulation time 14866840027 ps
CPU time 121.2 seconds
Started Oct 02 08:02:29 PM UTC 24
Finished Oct 02 08:04:33 PM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894071009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3894071009
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/31.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/32.hmac_alert_test.2247816176
Short name T333
Test name
Test status
Simulation time 16402337 ps
CPU time 0.91 seconds
Started Oct 02 08:03:41 PM UTC 24
Finished Oct 02 08:03:43 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247816176 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2247816176
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/32.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/32.hmac_back_pressure.886787954
Short name T349
Test name
Test status
Simulation time 7026353849 ps
CPU time 139.03 seconds
Started Oct 02 08:02:59 PM UTC 24
Finished Oct 02 08:05:21 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886787954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.886787954
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/32.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/32.hmac_burst_wr.139044440
Short name T331
Test name
Test status
Simulation time 2580597959 ps
CPU time 34.52 seconds
Started Oct 02 08:03:04 PM UTC 24
Finished Oct 02 08:03:40 PM UTC 24
Peak memory 210548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139044440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.139044440
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/32.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/32.hmac_datapath_stress.3295487686
Short name T487
Test name
Test status
Simulation time 107965655461 ps
CPU time 1089.17 seconds
Started Oct 02 08:02:59 PM UTC 24
Finished Oct 02 08:21:21 PM UTC 24
Peak memory 751116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295487686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3295487686
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/32.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/32.hmac_error.531081015
Short name T329
Test name
Test status
Simulation time 2253633819 ps
CPU time 7.09 seconds
Started Oct 02 08:03:23 PM UTC 24
Finished Oct 02 08:03:31 PM UTC 24
Peak memory 210236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531081015 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.531081015
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/32.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/32.hmac_long_msg.2370062327
Short name T350
Test name
Test status
Simulation time 74502944868 ps
CPU time 162.92 seconds
Started Oct 02 08:02:45 PM UTC 24
Finished Oct 02 08:05:31 PM UTC 24
Peak memory 219136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370062327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2370062327
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/32.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/32.hmac_smoke.3994968
Short name T328
Test name
Test status
Simulation time 4339167774 ps
CPU time 18.31 seconds
Started Oct 02 08:02:44 PM UTC 24
Finished Oct 02 08:03:03 PM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.hmac_smoke.3994968
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/32.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/32.hmac_stress_all.94825948
Short name T514
Test name
Test status
Simulation time 177892347098 ps
CPU time 2731.56 seconds
Started Oct 02 08:03:36 PM UTC 24
Finished Oct 02 08:49:36 PM UTC 24
Peak memory 814660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94825948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.94825948
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/32.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/32.hmac_wipe_secret.183162553
Short name T109
Test name
Test status
Simulation time 4030243706 ps
CPU time 37.6 seconds
Started Oct 02 08:03:32 PM UTC 24
Finished Oct 02 08:04:11 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183162553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.183162553
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/32.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/33.hmac_alert_test.2880125939
Short name T340
Test name
Test status
Simulation time 61350357 ps
CPU time 0.9 seconds
Started Oct 02 08:04:35 PM UTC 24
Finished Oct 02 08:04:37 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880125939 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2880125939
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/33.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/33.hmac_back_pressure.1438309443
Short name T353
Test name
Test status
Simulation time 2572067024 ps
CPU time 121.34 seconds
Started Oct 02 08:03:47 PM UTC 24
Finished Oct 02 08:05:51 PM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438309443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1438309443
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/33.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/33.hmac_datapath_stress.373258943
Short name T489
Test name
Test status
Simulation time 21873045786 ps
CPU time 1222.74 seconds
Started Oct 02 08:04:12 PM UTC 24
Finished Oct 02 08:24:49 PM UTC 24
Peak memory 716084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373258943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.373258943
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/33.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/33.hmac_error.960900675
Short name T386
Test name
Test status
Simulation time 12104322100 ps
CPU time 262.49 seconds
Started Oct 02 08:04:23 PM UTC 24
Finished Oct 02 08:08:49 PM UTC 24
Peak memory 210856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960900675 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.960900675
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/33.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/33.hmac_long_msg.1056338219
Short name T360
Test name
Test status
Simulation time 10368844410 ps
CPU time 167.81 seconds
Started Oct 02 08:03:44 PM UTC 24
Finished Oct 02 08:06:35 PM UTC 24
Peak memory 210512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056338219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1056338219
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/33.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/33.hmac_smoke.257681132
Short name T334
Test name
Test status
Simulation time 38500491 ps
CPU time 2.43 seconds
Started Oct 02 08:03:43 PM UTC 24
Finished Oct 02 08:03:46 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257681132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.257681132
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/33.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/33.hmac_stress_all.1811938625
Short name T515
Test name
Test status
Simulation time 73332690414 ps
CPU time 2709.72 seconds
Started Oct 02 08:04:30 PM UTC 24
Finished Oct 02 08:50:08 PM UTC 24
Peak memory 779580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811938625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1811938625
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/33.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/33.hmac_wipe_secret.2897421184
Short name T342
Test name
Test status
Simulation time 4273589950 ps
CPU time 22.61 seconds
Started Oct 02 08:04:25 PM UTC 24
Finished Oct 02 08:04:49 PM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897421184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2897421184
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/33.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/34.hmac_alert_test.3295027894
Short name T345
Test name
Test status
Simulation time 45481466 ps
CPU time 0.95 seconds
Started Oct 02 08:05:09 PM UTC 24
Finished Oct 02 08:05:11 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295027894 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3295027894
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/34.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/34.hmac_back_pressure.2763256973
Short name T32
Test name
Test status
Simulation time 3943448742 ps
CPU time 71.28 seconds
Started Oct 02 08:04:39 PM UTC 24
Finished Oct 02 08:05:52 PM UTC 24
Peak memory 226840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763256973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2763256973
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/34.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/34.hmac_burst_wr.94039499
Short name T348
Test name
Test status
Simulation time 1488780954 ps
CPU time 27.46 seconds
Started Oct 02 08:04:51 PM UTC 24
Finished Oct 02 08:05:19 PM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94039499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.94039499
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/34.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/34.hmac_datapath_stress.2684138573
Short name T476
Test name
Test status
Simulation time 3464289973 ps
CPU time 859.27 seconds
Started Oct 02 08:04:43 PM UTC 24
Finished Oct 02 08:19:13 PM UTC 24
Peak memory 755368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684138573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2684138573
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/34.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/34.hmac_error.2629757549
Short name T365
Test name
Test status
Simulation time 1796502255 ps
CPU time 108.98 seconds
Started Oct 02 08:04:52 PM UTC 24
Finished Oct 02 08:06:43 PM UTC 24
Peak memory 210660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629757549 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2629757549
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/34.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/34.hmac_long_msg.536691844
Short name T358
Test name
Test status
Simulation time 12160442672 ps
CPU time 93.38 seconds
Started Oct 02 08:04:38 PM UTC 24
Finished Oct 02 08:06:14 PM UTC 24
Peak memory 219088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536691844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.536691844
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/34.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/34.hmac_smoke.1190755371
Short name T343
Test name
Test status
Simulation time 653333831 ps
CPU time 16.09 seconds
Started Oct 02 08:04:38 PM UTC 24
Finished Oct 02 08:04:56 PM UTC 24
Peak memory 210584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190755371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1190755371
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/34.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/34.hmac_stress_all.1527074744
Short name T359
Test name
Test status
Simulation time 12808008282 ps
CPU time 81.84 seconds
Started Oct 02 08:05:09 PM UTC 24
Finished Oct 02 08:06:32 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527074744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1527074744
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/34.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/34.hmac_wipe_secret.2715998097
Short name T373
Test name
Test status
Simulation time 27253394669 ps
CPU time 145.97 seconds
Started Oct 02 08:04:57 PM UTC 24
Finished Oct 02 08:07:26 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715998097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2715998097
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/34.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/35.hmac_alert_test.1549427983
Short name T354
Test name
Test status
Simulation time 44394478 ps
CPU time 0.85 seconds
Started Oct 02 08:05:54 PM UTC 24
Finished Oct 02 08:05:56 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549427983 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1549427983
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/35.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/35.hmac_back_pressure.1072960244
Short name T363
Test name
Test status
Simulation time 5185998511 ps
CPU time 82.37 seconds
Started Oct 02 08:05:16 PM UTC 24
Finished Oct 02 08:06:40 PM UTC 24
Peak memory 210516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072960244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1072960244
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/35.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/35.hmac_burst_wr.1626556411
Short name T356
Test name
Test status
Simulation time 3566765493 ps
CPU time 37.56 seconds
Started Oct 02 08:05:23 PM UTC 24
Finished Oct 02 08:06:02 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626556411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1626556411
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/35.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/35.hmac_datapath_stress.3316457478
Short name T449
Test name
Test status
Simulation time 3136830337 ps
CPU time 614.92 seconds
Started Oct 02 08:05:20 PM UTC 24
Finished Oct 02 08:15:42 PM UTC 24
Peak memory 658688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316457478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3316457478
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/35.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/35.hmac_error.2264887139
Short name T380
Test name
Test status
Simulation time 24878224607 ps
CPU time 172.68 seconds
Started Oct 02 08:05:32 PM UTC 24
Finished Oct 02 08:08:28 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264887139 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2264887139
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/35.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/35.hmac_long_msg.1192970159
Short name T352
Test name
Test status
Simulation time 5751416448 ps
CPU time 27.3 seconds
Started Oct 02 08:05:14 PM UTC 24
Finished Oct 02 08:05:43 PM UTC 24
Peak memory 210564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192970159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1192970159
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/35.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/35.hmac_smoke.2813297692
Short name T351
Test name
Test status
Simulation time 3507320858 ps
CPU time 17.83 seconds
Started Oct 02 08:05:14 PM UTC 24
Finished Oct 02 08:05:33 PM UTC 24
Peak memory 210644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813297692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2813297692
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/35.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/35.hmac_stress_all.1451664995
Short name T85
Test name
Test status
Simulation time 155237588751 ps
CPU time 1806.14 seconds
Started Oct 02 08:05:44 PM UTC 24
Finished Oct 02 08:36:13 PM UTC 24
Peak memory 730532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451664995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1451664995
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/35.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/35.hmac_wipe_secret.3844164112
Short name T374
Test name
Test status
Simulation time 4091096724 ps
CPU time 112.2 seconds
Started Oct 02 08:05:34 PM UTC 24
Finished Oct 02 08:07:28 PM UTC 24
Peak memory 210448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844164112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3844164112
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/35.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/36.hmac_alert_test.2437030785
Short name T362
Test name
Test status
Simulation time 13329130 ps
CPU time 0.94 seconds
Started Oct 02 08:06:38 PM UTC 24
Finished Oct 02 08:06:40 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437030785 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2437030785
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/36.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/36.hmac_back_pressure.1264309286
Short name T364
Test name
Test status
Simulation time 568654461 ps
CPU time 35.51 seconds
Started Oct 02 08:06:04 PM UTC 24
Finished Oct 02 08:06:41 PM UTC 24
Peak memory 221004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264309286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1264309286
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/36.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/36.hmac_burst_wr.3106690446
Short name T361
Test name
Test status
Simulation time 6135421983 ps
CPU time 29.7 seconds
Started Oct 02 08:06:06 PM UTC 24
Finished Oct 02 08:06:37 PM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106690446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3106690446
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/36.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/36.hmac_datapath_stress.1209225758
Short name T401
Test name
Test status
Simulation time 1249000176 ps
CPU time 227.34 seconds
Started Oct 02 08:06:04 PM UTC 24
Finished Oct 02 08:09:56 PM UTC 24
Peak memory 464092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209225758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1209225758
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/36.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/36.hmac_error.1317106731
Short name T399
Test name
Test status
Simulation time 67267589901 ps
CPU time 204.03 seconds
Started Oct 02 08:06:15 PM UTC 24
Finished Oct 02 08:09:42 PM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317106731 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1317106731
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/36.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/36.hmac_long_msg.2547831158
Short name T397
Test name
Test status
Simulation time 54673160087 ps
CPU time 216.45 seconds
Started Oct 02 08:05:57 PM UTC 24
Finished Oct 02 08:09:37 PM UTC 24
Peak memory 210512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547831158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2547831158
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/36.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/36.hmac_smoke.860686766
Short name T357
Test name
Test status
Simulation time 2345995672 ps
CPU time 8.43 seconds
Started Oct 02 08:05:54 PM UTC 24
Finished Oct 02 08:06:03 PM UTC 24
Peak memory 210800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860686766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.860686766
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/36.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/36.hmac_stress_all.3112115838
Short name T86
Test name
Test status
Simulation time 64708841941 ps
CPU time 1977.37 seconds
Started Oct 02 08:06:37 PM UTC 24
Finished Oct 02 08:39:56 PM UTC 24
Peak memory 763452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112115838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3112115838
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/36.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/36.hmac_wipe_secret.2625243203
Short name T111
Test name
Test status
Simulation time 1134322399 ps
CPU time 57.04 seconds
Started Oct 02 08:06:34 PM UTC 24
Finished Oct 02 08:07:33 PM UTC 24
Peak memory 210448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625243203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2625243203
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/36.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/37.hmac_alert_test.815309403
Short name T371
Test name
Test status
Simulation time 14533119 ps
CPU time 0.91 seconds
Started Oct 02 08:07:05 PM UTC 24
Finished Oct 02 08:07:07 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815309403 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.815309403
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/37.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/37.hmac_back_pressure.3701787010
Short name T366
Test name
Test status
Simulation time 98489462 ps
CPU time 3.45 seconds
Started Oct 02 08:06:42 PM UTC 24
Finished Oct 02 08:06:47 PM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701787010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3701787010
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/37.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/37.hmac_burst_wr.2141783084
Short name T368
Test name
Test status
Simulation time 181655814 ps
CPU time 2.38 seconds
Started Oct 02 08:06:48 PM UTC 24
Finished Oct 02 08:06:51 PM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141783084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2141783084
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/37.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/37.hmac_datapath_stress.3799206932
Short name T492
Test name
Test status
Simulation time 6328280620 ps
CPU time 1241.33 seconds
Started Oct 02 08:06:45 PM UTC 24
Finished Oct 02 08:27:40 PM UTC 24
Peak memory 712356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799206932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3799206932
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/37.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/37.hmac_error.3475218464
Short name T405
Test name
Test status
Simulation time 45945316494 ps
CPU time 232.29 seconds
Started Oct 02 08:06:51 PM UTC 24
Finished Oct 02 08:10:48 PM UTC 24
Peak memory 210792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475218464 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3475218464
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/37.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/37.hmac_long_msg.4065394310
Short name T375
Test name
Test status
Simulation time 2758579944 ps
CPU time 58.19 seconds
Started Oct 02 08:06:42 PM UTC 24
Finished Oct 02 08:07:42 PM UTC 24
Peak memory 210528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065394310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.4065394310
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/37.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/37.hmac_smoke.2788311947
Short name T369
Test name
Test status
Simulation time 929869528 ps
CPU time 13.53 seconds
Started Oct 02 08:06:42 PM UTC 24
Finished Oct 02 08:06:57 PM UTC 24
Peak memory 210616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788311947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2788311947
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/37.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/37.hmac_stress_all.3352678930
Short name T370
Test name
Test status
Simulation time 235686128 ps
CPU time 7.69 seconds
Started Oct 02 08:06:58 PM UTC 24
Finished Oct 02 08:07:06 PM UTC 24
Peak memory 210404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352678930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3352678930
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/37.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/37.hmac_wipe_secret.371851861
Short name T112
Test name
Test status
Simulation time 5351599848 ps
CPU time 86.28 seconds
Started Oct 02 08:06:53 PM UTC 24
Finished Oct 02 08:08:21 PM UTC 24
Peak memory 210768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371851861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.371851861
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/37.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/38.hmac_alert_test.1835650479
Short name T379
Test name
Test status
Simulation time 43603650 ps
CPU time 0.84 seconds
Started Oct 02 08:08:08 PM UTC 24
Finished Oct 02 08:08:10 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835650479 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1835650479
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/38.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/38.hmac_back_pressure.383336864
Short name T389
Test name
Test status
Simulation time 1199844487 ps
CPU time 86.85 seconds
Started Oct 02 08:07:27 PM UTC 24
Finished Oct 02 08:08:57 PM UTC 24
Peak memory 210380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383336864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.383336864
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/38.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/38.hmac_burst_wr.41250944
Short name T392
Test name
Test status
Simulation time 19392166021 ps
CPU time 96.15 seconds
Started Oct 02 08:07:29 PM UTC 24
Finished Oct 02 08:09:08 PM UTC 24
Peak memory 219096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41250944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.41250944
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/38.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/38.hmac_datapath_stress.2697177074
Short name T498
Test name
Test status
Simulation time 47263233967 ps
CPU time 1325.65 seconds
Started Oct 02 08:07:27 PM UTC 24
Finished Oct 02 08:29:47 PM UTC 24
Peak memory 752988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697177074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2697177074
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/38.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/38.hmac_error.2073448592
Short name T376
Test name
Test status
Simulation time 2054245896 ps
CPU time 13.34 seconds
Started Oct 02 08:07:34 PM UTC 24
Finished Oct 02 08:07:49 PM UTC 24
Peak memory 210280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073448592 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2073448592
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/38.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/38.hmac_long_msg.2262716262
Short name T400
Test name
Test status
Simulation time 3856482954 ps
CPU time 158.98 seconds
Started Oct 02 08:07:08 PM UTC 24
Finished Oct 02 08:09:50 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262716262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2262716262
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/38.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/38.hmac_smoke.3142760276
Short name T372
Test name
Test status
Simulation time 4206490613 ps
CPU time 16.89 seconds
Started Oct 02 08:07:07 PM UTC 24
Finished Oct 02 08:07:25 PM UTC 24
Peak memory 210548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142760276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3142760276
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/38.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/38.hmac_stress_all.3730455828
Short name T520
Test name
Test status
Simulation time 39485598143 ps
CPU time 2983.68 seconds
Started Oct 02 08:07:49 PM UTC 24
Finished Oct 02 08:58:06 PM UTC 24
Peak memory 744768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730455828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3730455828
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/38.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/38.hmac_wipe_secret.1803915488
Short name T113
Test name
Test status
Simulation time 4175004135 ps
CPU time 53.86 seconds
Started Oct 02 08:07:43 PM UTC 24
Finished Oct 02 08:08:39 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803915488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1803915488
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/38.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/39.hmac_alert_test.756296556
Short name T387
Test name
Test status
Simulation time 13189764 ps
CPU time 0.79 seconds
Started Oct 02 08:08:48 PM UTC 24
Finished Oct 02 08:08:49 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756296556 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.756296556
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/39.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/39.hmac_back_pressure.691871645
Short name T384
Test name
Test status
Simulation time 507268934 ps
CPU time 20.37 seconds
Started Oct 02 08:08:23 PM UTC 24
Finished Oct 02 08:08:44 PM UTC 24
Peak memory 210508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691871645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.691871645
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/39.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/39.hmac_datapath_stress.1525223930
Short name T457
Test name
Test status
Simulation time 2429842717 ps
CPU time 489.57 seconds
Started Oct 02 08:08:29 PM UTC 24
Finished Oct 02 08:16:45 PM UTC 24
Peak memory 710308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525223930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1525223930
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/39.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/39.hmac_error.1216583962
Short name T406
Test name
Test status
Simulation time 26654746508 ps
CPU time 144.64 seconds
Started Oct 02 08:08:36 PM UTC 24
Finished Oct 02 08:11:04 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216583962 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1216583962
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/39.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/39.hmac_long_msg.3512912445
Short name T403
Test name
Test status
Simulation time 7844567307 ps
CPU time 129.81 seconds
Started Oct 02 08:08:14 PM UTC 24
Finished Oct 02 08:10:26 PM UTC 24
Peak memory 210488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512912445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3512912445
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/39.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/39.hmac_smoke.1827977661
Short name T381
Test name
Test status
Simulation time 466028696 ps
CPU time 15.21 seconds
Started Oct 02 08:08:13 PM UTC 24
Finished Oct 02 08:08:29 PM UTC 24
Peak memory 210448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827977661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1827977661
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/39.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/39.hmac_stress_all.2806904396
Short name T83
Test name
Test status
Simulation time 60782863021 ps
CPU time 1371.74 seconds
Started Oct 02 08:08:48 PM UTC 24
Finished Oct 02 08:31:56 PM UTC 24
Peak memory 722172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806904396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2806904396
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/39.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/39.hmac_wipe_secret.3855996564
Short name T396
Test name
Test status
Simulation time 1142058701 ps
CPU time 47.97 seconds
Started Oct 02 08:08:40 PM UTC 24
Finished Oct 02 08:09:30 PM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855996564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3855996564
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/39.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/4.hmac_alert_test.3567384958
Short name T79
Test name
Test status
Simulation time 119297264 ps
CPU time 0.94 seconds
Started Oct 02 07:45:54 PM UTC 24
Finished Oct 02 07:45:56 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567384958 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3567384958
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/4.hmac_back_pressure.965678913
Short name T38
Test name
Test status
Simulation time 464808566 ps
CPU time 39.18 seconds
Started Oct 02 07:45:19 PM UTC 24
Finished Oct 02 07:46:00 PM UTC 24
Peak memory 210336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965678913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.965678913
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/4.hmac_datapath_stress.2917795966
Short name T355
Test name
Test status
Simulation time 5350878340 ps
CPU time 1222.98 seconds
Started Oct 02 07:45:22 PM UTC 24
Finished Oct 02 08:06:01 PM UTC 24
Peak memory 748852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917795966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2917795966
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/4.hmac_error.1110830949
Short name T154
Test name
Test status
Simulation time 62936191260 ps
CPU time 213.38 seconds
Started Oct 02 07:45:25 PM UTC 24
Finished Oct 02 07:49:02 PM UTC 24
Peak memory 210788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110830949 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1110830949
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/4.hmac_long_msg.2722722794
Short name T193
Test name
Test status
Simulation time 25255807194 ps
CPU time 187.67 seconds
Started Oct 02 07:45:17 PM UTC 24
Finished Oct 02 07:48:28 PM UTC 24
Peak memory 210528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722722794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2722722794
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/4.hmac_sec_cm.2014693746
Short name T67
Test name
Test status
Simulation time 86201429 ps
CPU time 1.8 seconds
Started Oct 02 07:45:54 PM UTC 24
Finished Oct 02 07:45:57 PM UTC 24
Peak memory 238200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014693746 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2014693746
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/4.hmac_smoke.3580109391
Short name T155
Test name
Test status
Simulation time 326394160 ps
CPU time 3.62 seconds
Started Oct 02 07:45:17 PM UTC 24
Finished Oct 02 07:45:21 PM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580109391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3580109391
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/4.hmac_stress_all.3367961627
Short name T523
Test name
Test status
Simulation time 104398734391 ps
CPU time 5973.65 seconds
Started Oct 02 07:45:50 PM UTC 24
Finished Oct 02 09:26:26 PM UTC 24
Peak memory 902680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367961627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.3367961627
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/4.hmac_test_hmac256_vectors.3577853603
Short name T42
Test name
Test status
Simulation time 5575154973 ps
CPU time 40.2 seconds
Started Oct 02 07:45:36 PM UTC 24
Finished Oct 02 07:46:17 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577853603 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.3577853603
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/4.hmac_test_hmac384_vectors.2626360727
Short name T187
Test name
Test status
Simulation time 8172817029 ps
CPU time 109.29 seconds
Started Oct 02 07:45:41 PM UTC 24
Finished Oct 02 07:47:33 PM UTC 24
Peak memory 210476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626360727 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.2626360727
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/4.hmac_test_hmac512_vectors.2313352454
Short name T191
Test name
Test status
Simulation time 8793304305 ps
CPU time 145.96 seconds
Started Oct 02 07:45:46 PM UTC 24
Finished Oct 02 07:48:14 PM UTC 24
Peak memory 210804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313352454 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.2313352454
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/4.hmac_test_sha256_vectors.1794335165
Short name T284
Test name
Test status
Simulation time 210896356903 ps
CPU time 740.8 seconds
Started Oct 02 07:45:27 PM UTC 24
Finished Oct 02 07:57:58 PM UTC 24
Peak memory 210636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794335165 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1794335165
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/4.hmac_test_sha384_vectors.3347110452
Short name T499
Test name
Test status
Simulation time 550394433087 ps
CPU time 2676.05 seconds
Started Oct 02 07:45:29 PM UTC 24
Finished Oct 02 08:30:35 PM UTC 24
Peak memory 230612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347110452 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.3347110452
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/4.hmac_test_sha512_vectors.924457763
Short name T504
Test name
Test status
Simulation time 767070348276 ps
CPU time 2832.67 seconds
Started Oct 02 07:45:33 PM UTC 24
Finished Oct 02 08:33:18 PM UTC 24
Peak memory 230776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924457763 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.924457763
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/4.hmac_wipe_secret.1018205985
Short name T170
Test name
Test status
Simulation time 4514272034 ps
CPU time 105.94 seconds
Started Oct 02 07:45:27 PM UTC 24
Finished Oct 02 07:47:15 PM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018205985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1018205985
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/4.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/40.hmac_alert_test.1273379546
Short name T394
Test name
Test status
Simulation time 13291293 ps
CPU time 0.96 seconds
Started Oct 02 08:09:15 PM UTC 24
Finished Oct 02 08:09:17 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273379546 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1273379546
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/40.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/40.hmac_back_pressure.3245392954
Short name T393
Test name
Test status
Simulation time 172679926 ps
CPU time 13.84 seconds
Started Oct 02 08:08:59 PM UTC 24
Finished Oct 02 08:09:14 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245392954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3245392954
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/40.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/40.hmac_burst_wr.4264937781
Short name T398
Test name
Test status
Simulation time 519685700 ps
CPU time 36.05 seconds
Started Oct 02 08:09:01 PM UTC 24
Finished Oct 02 08:09:38 PM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264937781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.4264937781
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/40.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/40.hmac_datapath_stress.4253344048
Short name T478
Test name
Test status
Simulation time 5347966027 ps
CPU time 634.43 seconds
Started Oct 02 08:08:59 PM UTC 24
Finished Oct 02 08:19:41 PM UTC 24
Peak memory 728324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253344048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.4253344048
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/40.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/40.hmac_error.18478668
Short name T385
Test name
Test status
Simulation time 5672555444 ps
CPU time 137.9 seconds
Started Oct 02 08:09:04 PM UTC 24
Finished Oct 02 08:11:24 PM UTC 24
Peak memory 210724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18478668 -assert nopostproc +UVM_TESTNAME=hmac
_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.18478668
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/40.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/40.hmac_long_msg.3881787832
Short name T417
Test name
Test status
Simulation time 11106222276 ps
CPU time 184.37 seconds
Started Oct 02 08:08:51 PM UTC 24
Finished Oct 02 08:11:58 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881787832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3881787832
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/40.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/40.hmac_smoke.467037787
Short name T390
Test name
Test status
Simulation time 328283746 ps
CPU time 8.15 seconds
Started Oct 02 08:08:51 PM UTC 24
Finished Oct 02 08:09:00 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467037787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.467037787
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/40.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/40.hmac_stress_all.1915900926
Short name T519
Test name
Test status
Simulation time 203345760725 ps
CPU time 2515.87 seconds
Started Oct 02 08:09:09 PM UTC 24
Finished Oct 02 08:51:31 PM UTC 24
Peak memory 732388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915900926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1915900926
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/40.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/40.hmac_wipe_secret.2369882958
Short name T415
Test name
Test status
Simulation time 2236426414 ps
CPU time 152.16 seconds
Started Oct 02 08:09:04 PM UTC 24
Finished Oct 02 08:11:39 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369882958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2369882958
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/40.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/41.hmac_alert_test.1998787842
Short name T402
Test name
Test status
Simulation time 29412740 ps
CPU time 0.88 seconds
Started Oct 02 08:10:13 PM UTC 24
Finished Oct 02 08:10:15 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998787842 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1998787842
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/41.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/41.hmac_back_pressure.1945129648
Short name T409
Test name
Test status
Simulation time 5572949776 ps
CPU time 98.49 seconds
Started Oct 02 08:09:32 PM UTC 24
Finished Oct 02 08:11:12 PM UTC 24
Peak memory 210516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945129648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1945129648
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/41.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/41.hmac_burst_wr.2858424013
Short name T408
Test name
Test status
Simulation time 19628306718 ps
CPU time 90.31 seconds
Started Oct 02 08:09:39 PM UTC 24
Finished Oct 02 08:11:11 PM UTC 24
Peak memory 210512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858424013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2858424013
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/41.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/41.hmac_datapath_stress.2020735539
Short name T480
Test name
Test status
Simulation time 12945298377 ps
CPU time 606.34 seconds
Started Oct 02 08:09:39 PM UTC 24
Finished Oct 02 08:19:53 PM UTC 24
Peak memory 732544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020735539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2020735539
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/41.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/41.hmac_error.4220633091
Short name T413
Test name
Test status
Simulation time 3120253957 ps
CPU time 105.92 seconds
Started Oct 02 08:09:44 PM UTC 24
Finished Oct 02 08:11:32 PM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220633091 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.4220633091
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/41.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/41.hmac_long_msg.1794263616
Short name T411
Test name
Test status
Simulation time 6650469925 ps
CPU time 112.4 seconds
Started Oct 02 08:09:28 PM UTC 24
Finished Oct 02 08:11:23 PM UTC 24
Peak memory 210732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794263616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1794263616
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/41.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/41.hmac_smoke.919963709
Short name T395
Test name
Test status
Simulation time 138555038 ps
CPU time 8.36 seconds
Started Oct 02 08:09:18 PM UTC 24
Finished Oct 02 08:09:28 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919963709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.919963709
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/41.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/41.hmac_wipe_secret.4024177842
Short name T429
Test name
Test status
Simulation time 12187403758 ps
CPU time 194.28 seconds
Started Oct 02 08:09:52 PM UTC 24
Finished Oct 02 08:13:10 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024177842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.4024177842
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/41.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/42.hmac_alert_test.2307514875
Short name T412
Test name
Test status
Simulation time 16558615 ps
CPU time 0.85 seconds
Started Oct 02 08:11:21 PM UTC 24
Finished Oct 02 08:11:23 PM UTC 24
Peak memory 207400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307514875 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2307514875
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/42.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/42.hmac_back_pressure.3718145613
Short name T34
Test name
Test status
Simulation time 2222341573 ps
CPU time 89.12 seconds
Started Oct 02 08:10:41 PM UTC 24
Finished Oct 02 08:12:12 PM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718145613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3718145613
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/42.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/42.hmac_burst_wr.294740099
Short name T419
Test name
Test status
Simulation time 2813627182 ps
CPU time 59.09 seconds
Started Oct 02 08:11:05 PM UTC 24
Finished Oct 02 08:12:06 PM UTC 24
Peak memory 210800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294740099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.294740099
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/42.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/42.hmac_datapath_stress.3377614412
Short name T490
Test name
Test status
Simulation time 10529332379 ps
CPU time 843.82 seconds
Started Oct 02 08:10:49 PM UTC 24
Finished Oct 02 08:25:03 PM UTC 24
Peak memory 718140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377614412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3377614412
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/42.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/42.hmac_error.699093259
Short name T421
Test name
Test status
Simulation time 14659353413 ps
CPU time 52.06 seconds
Started Oct 02 08:11:19 PM UTC 24
Finished Oct 02 08:12:13 PM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699093259 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.699093259
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/42.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/42.hmac_long_msg.2129844305
Short name T447
Test name
Test status
Simulation time 47499991153 ps
CPU time 298.05 seconds
Started Oct 02 08:10:28 PM UTC 24
Finished Oct 02 08:15:30 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129844305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2129844305
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/42.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/42.hmac_smoke.3294855570
Short name T404
Test name
Test status
Simulation time 24076463069 ps
CPU time 21.1 seconds
Started Oct 02 08:10:16 PM UTC 24
Finished Oct 02 08:10:39 PM UTC 24
Peak memory 210552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294855570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3294855570
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/42.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/42.hmac_stress_all.1597303299
Short name T524
Test name
Test status
Simulation time 153057604071 ps
CPU time 4748.42 seconds
Started Oct 02 08:11:19 PM UTC 24
Finished Oct 02 09:31:15 PM UTC 24
Peak memory 859736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597303299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1597303299
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/42.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/42.hmac_wipe_secret.1951533715
Short name T416
Test name
Test status
Simulation time 13145927925 ps
CPU time 29.53 seconds
Started Oct 02 08:11:19 PM UTC 24
Finished Oct 02 08:11:50 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951533715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1951533715
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/42.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/43.hmac_alert_test.2669870749
Short name T418
Test name
Test status
Simulation time 12391746 ps
CPU time 0.88 seconds
Started Oct 02 08:12:00 PM UTC 24
Finished Oct 02 08:12:02 PM UTC 24
Peak memory 207400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669870749 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2669870749
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/43.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/43.hmac_back_pressure.559078430
Short name T422
Test name
Test status
Simulation time 3269939515 ps
CPU time 65.13 seconds
Started Oct 02 08:11:27 PM UTC 24
Finished Oct 02 08:12:34 PM UTC 24
Peak memory 210608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559078430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.559078430
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/43.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/43.hmac_burst_wr.372679181
Short name T424
Test name
Test status
Simulation time 1812265794 ps
CPU time 68.45 seconds
Started Oct 02 08:11:34 PM UTC 24
Finished Oct 02 08:12:44 PM UTC 24
Peak memory 210420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372679181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.372679181
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/43.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/43.hmac_datapath_stress.435225821
Short name T477
Test name
Test status
Simulation time 2125045683 ps
CPU time 467.35 seconds
Started Oct 02 08:11:27 PM UTC 24
Finished Oct 02 08:19:20 PM UTC 24
Peak memory 744896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435225821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.435225821
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/43.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/43.hmac_error.3912674374
Short name T423
Test name
Test status
Simulation time 6399873737 ps
CPU time 59.58 seconds
Started Oct 02 08:11:35 PM UTC 24
Finished Oct 02 08:12:36 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912674374 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3912674374
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/43.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/43.hmac_long_msg.1382406126
Short name T458
Test name
Test status
Simulation time 116140880215 ps
CPU time 313.61 seconds
Started Oct 02 08:11:27 PM UTC 24
Finished Oct 02 08:16:46 PM UTC 24
Peak memory 219292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382406126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1382406126
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/43.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/43.hmac_smoke.1647449869
Short name T414
Test name
Test status
Simulation time 300877294 ps
CPU time 7.39 seconds
Started Oct 02 08:11:25 PM UTC 24
Finished Oct 02 08:11:34 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647449869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1647449869
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/43.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/43.hmac_stress_all.3648450184
Short name T485
Test name
Test status
Simulation time 89655933242 ps
CPU time 506.71 seconds
Started Oct 02 08:11:51 PM UTC 24
Finished Oct 02 08:20:24 PM UTC 24
Peak memory 219032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648450184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3648450184
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/43.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/43.hmac_wipe_secret.4070433529
Short name T430
Test name
Test status
Simulation time 17667428435 ps
CPU time 115.59 seconds
Started Oct 02 08:11:41 PM UTC 24
Finished Oct 02 08:13:39 PM UTC 24
Peak memory 210864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070433529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.4070433529
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/43.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/44.hmac_alert_test.2840335786
Short name T426
Test name
Test status
Simulation time 12007399 ps
CPU time 0.84 seconds
Started Oct 02 08:12:47 PM UTC 24
Finished Oct 02 08:12:49 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840335786 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2840335786
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/44.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/44.hmac_back_pressure.1723542198
Short name T433
Test name
Test status
Simulation time 3645242395 ps
CPU time 109.25 seconds
Started Oct 02 08:12:11 PM UTC 24
Finished Oct 02 08:14:03 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723542198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1723542198
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/44.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/44.hmac_burst_wr.2473250742
Short name T425
Test name
Test status
Simulation time 798685240 ps
CPU time 29.65 seconds
Started Oct 02 08:12:15 PM UTC 24
Finished Oct 02 08:12:46 PM UTC 24
Peak memory 210336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473250742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2473250742
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/44.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/44.hmac_datapath_stress.2461289099
Short name T509
Test name
Test status
Simulation time 17931065378 ps
CPU time 1314.35 seconds
Started Oct 02 08:12:15 PM UTC 24
Finished Oct 02 08:34:24 PM UTC 24
Peak memory 777524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461289099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2461289099
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/44.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/44.hmac_error.1471547485
Short name T427
Test name
Test status
Simulation time 1462050874 ps
CPU time 16.57 seconds
Started Oct 02 08:12:35 PM UTC 24
Finished Oct 02 08:12:53 PM UTC 24
Peak memory 210244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471547485 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1471547485
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/44.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/44.hmac_long_msg.3435445320
Short name T432
Test name
Test status
Simulation time 17712185263 ps
CPU time 114.15 seconds
Started Oct 02 08:12:06 PM UTC 24
Finished Oct 02 08:14:03 PM UTC 24
Peak memory 219040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435445320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3435445320
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/44.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/44.hmac_smoke.1577885954
Short name T420
Test name
Test status
Simulation time 580830947 ps
CPU time 6.04 seconds
Started Oct 02 08:12:03 PM UTC 24
Finished Oct 02 08:12:11 PM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577885954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1577885954
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/44.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/44.hmac_stress_all.3582125949
Short name T82
Test name
Test status
Simulation time 28124316368 ps
CPU time 905.74 seconds
Started Oct 02 08:12:45 PM UTC 24
Finished Oct 02 08:28:02 PM UTC 24
Peak memory 701700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582125949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3582125949
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/44.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/44.hmac_wipe_secret.3614404269
Short name T434
Test name
Test status
Simulation time 3480017242 ps
CPU time 89.61 seconds
Started Oct 02 08:12:38 PM UTC 24
Finished Oct 02 08:14:09 PM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614404269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3614404269
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/44.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/45.hmac_alert_test.808595480
Short name T435
Test name
Test status
Simulation time 15664317 ps
CPU time 0.84 seconds
Started Oct 02 08:14:11 PM UTC 24
Finished Oct 02 08:14:13 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808595480 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.808595480
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/45.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/45.hmac_back_pressure.463710575
Short name T431
Test name
Test status
Simulation time 511423057 ps
CPU time 41.41 seconds
Started Oct 02 08:13:03 PM UTC 24
Finished Oct 02 08:13:46 PM UTC 24
Peak memory 210636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463710575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.463710575
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/45.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/45.hmac_burst_wr.3323056950
Short name T441
Test name
Test status
Simulation time 1307359534 ps
CPU time 86.67 seconds
Started Oct 02 08:13:40 PM UTC 24
Finished Oct 02 08:15:09 PM UTC 24
Peak memory 210384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323056950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3323056950
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/45.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/45.hmac_datapath_stress.2780583667
Short name T481
Test name
Test status
Simulation time 9313905360 ps
CPU time 398.78 seconds
Started Oct 02 08:13:11 PM UTC 24
Finished Oct 02 08:19:56 PM UTC 24
Peak memory 654584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780583667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2780583667
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/45.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/45.hmac_error.2987243830
Short name T442
Test name
Test status
Simulation time 17924606712 ps
CPU time 81.96 seconds
Started Oct 02 08:13:47 PM UTC 24
Finished Oct 02 08:15:11 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987243830 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2987243830
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/45.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/45.hmac_long_msg.170998495
Short name T452
Test name
Test status
Simulation time 14614158290 ps
CPU time 211.11 seconds
Started Oct 02 08:12:54 PM UTC 24
Finished Oct 02 08:16:29 PM UTC 24
Peak memory 219028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170998495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.170998495
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/45.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/45.hmac_smoke.602937983
Short name T428
Test name
Test status
Simulation time 759203761 ps
CPU time 11.37 seconds
Started Oct 02 08:12:50 PM UTC 24
Finished Oct 02 08:13:02 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602937983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.602937983
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/45.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/45.hmac_stress_all.1533298018
Short name T464
Test name
Test status
Simulation time 7303390415 ps
CPU time 180.99 seconds
Started Oct 02 08:14:05 PM UTC 24
Finished Oct 02 08:17:10 PM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533298018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1533298018
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/45.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/45.hmac_wipe_secret.849894432
Short name T453
Test name
Test status
Simulation time 16696204852 ps
CPU time 143.1 seconds
Started Oct 02 08:14:05 PM UTC 24
Finished Oct 02 08:16:31 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849894432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.849894432
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/45.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/46.hmac_alert_test.3137692393
Short name T444
Test name
Test status
Simulation time 13164680 ps
CPU time 0.83 seconds
Started Oct 02 08:15:17 PM UTC 24
Finished Oct 02 08:15:19 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137692393 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3137692393
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/46.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/46.hmac_back_pressure.4227369289
Short name T446
Test name
Test status
Simulation time 1488631710 ps
CPU time 51.66 seconds
Started Oct 02 08:14:32 PM UTC 24
Finished Oct 02 08:15:25 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227369289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.4227369289
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/46.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/46.hmac_burst_wr.77387168
Short name T451
Test name
Test status
Simulation time 3728581996 ps
CPU time 66.88 seconds
Started Oct 02 08:14:44 PM UTC 24
Finished Oct 02 08:15:53 PM UTC 24
Peak memory 219220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77387168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.77387168
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/46.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/46.hmac_datapath_stress.1956466913
Short name T439
Test name
Test status
Simulation time 19567845 ps
CPU time 1.1 seconds
Started Oct 02 08:14:41 PM UTC 24
Finished Oct 02 08:14:43 PM UTC 24
Peak memory 209908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956466913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1956466913
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/46.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/46.hmac_error.3103154047
Short name T461
Test name
Test status
Simulation time 11760377038 ps
CPU time 120.25 seconds
Started Oct 02 08:15:01 PM UTC 24
Finished Oct 02 08:17:03 PM UTC 24
Peak memory 210756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103154047 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3103154047
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/46.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/46.hmac_long_msg.2617798640
Short name T440
Test name
Test status
Simulation time 4229664182 ps
CPU time 31.88 seconds
Started Oct 02 08:14:26 PM UTC 24
Finished Oct 02 08:14:59 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617798640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2617798640
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/46.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/46.hmac_smoke.3506683542
Short name T436
Test name
Test status
Simulation time 542640748 ps
CPU time 9.92 seconds
Started Oct 02 08:14:14 PM UTC 24
Finished Oct 02 08:14:25 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506683542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3506683542
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/46.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/46.hmac_stress_all.1367256427
Short name T512
Test name
Test status
Simulation time 43374686251 ps
CPU time 1752.46 seconds
Started Oct 02 08:15:12 PM UTC 24
Finished Oct 02 08:44:44 PM UTC 24
Peak memory 783880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367256427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1367256427
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/46.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/46.hmac_wipe_secret.2143331029
Short name T443
Test name
Test status
Simulation time 263169743 ps
CPU time 5.65 seconds
Started Oct 02 08:15:10 PM UTC 24
Finished Oct 02 08:15:17 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143331029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2143331029
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/46.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/47.hmac_alert_test.1636285036
Short name T454
Test name
Test status
Simulation time 10459815 ps
CPU time 0.87 seconds
Started Oct 02 08:16:31 PM UTC 24
Finished Oct 02 08:16:33 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636285036 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1636285036
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/47.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/47.hmac_back_pressure.3879889570
Short name T462
Test name
Test status
Simulation time 9989592855 ps
CPU time 96.81 seconds
Started Oct 02 08:15:26 PM UTC 24
Finished Oct 02 08:17:05 PM UTC 24
Peak memory 218968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879889570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3879889570
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/47.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/47.hmac_burst_wr.1101443673
Short name T456
Test name
Test status
Simulation time 3306473762 ps
CPU time 56.33 seconds
Started Oct 02 08:15:45 PM UTC 24
Finished Oct 02 08:16:44 PM UTC 24
Peak memory 210468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101443673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1101443673
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/47.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/47.hmac_datapath_stress.2258272813
Short name T494
Test name
Test status
Simulation time 6638743794 ps
CPU time 719.96 seconds
Started Oct 02 08:15:33 PM UTC 24
Finished Oct 02 08:27:41 PM UTC 24
Peak memory 709944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258272813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2258272813
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/47.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/47.hmac_error.3849224905
Short name T472
Test name
Test status
Simulation time 24053749369 ps
CPU time 159.06 seconds
Started Oct 02 08:15:48 PM UTC 24
Finished Oct 02 08:18:30 PM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849224905 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3849224905
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/47.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/47.hmac_long_msg.3277268288
Short name T473
Test name
Test status
Simulation time 9040557033 ps
CPU time 185.15 seconds
Started Oct 02 08:15:23 PM UTC 24
Finished Oct 02 08:18:32 PM UTC 24
Peak memory 219268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277268288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3277268288
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/47.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/47.hmac_smoke.3935864195
Short name T445
Test name
Test status
Simulation time 23431709 ps
CPU time 1.55 seconds
Started Oct 02 08:15:20 PM UTC 24
Finished Oct 02 08:15:23 PM UTC 24
Peak memory 210580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935864195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3935864195
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/47.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/47.hmac_stress_all.4207567652
Short name T516
Test name
Test status
Simulation time 97802485713 ps
CPU time 2051.81 seconds
Started Oct 02 08:15:54 PM UTC 24
Finished Oct 02 08:50:29 PM UTC 24
Peak memory 668928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207567652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.4207567652
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/47.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/47.hmac_wipe_secret.980588608
Short name T466
Test name
Test status
Simulation time 5089729425 ps
CPU time 91.07 seconds
Started Oct 02 08:15:49 PM UTC 24
Finished Oct 02 08:17:22 PM UTC 24
Peak memory 210800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980588608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.980588608
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/47.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/48.hmac_alert_test.1018793257
Short name T463
Test name
Test status
Simulation time 21860032 ps
CPU time 0.84 seconds
Started Oct 02 08:17:05 PM UTC 24
Finished Oct 02 08:17:07 PM UTC 24
Peak memory 207400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018793257 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1018793257
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/48.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/48.hmac_back_pressure.2366172814
Short name T460
Test name
Test status
Simulation time 453845375 ps
CPU time 16.36 seconds
Started Oct 02 08:16:42 PM UTC 24
Finished Oct 02 08:17:00 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366172814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2366172814
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/48.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/48.hmac_burst_wr.3311806647
Short name T465
Test name
Test status
Simulation time 4262555369 ps
CPU time 19.85 seconds
Started Oct 02 08:16:49 PM UTC 24
Finished Oct 02 08:17:10 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311806647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3311806647
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/48.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/48.hmac_datapath_stress.3045596057
Short name T496
Test name
Test status
Simulation time 22879938374 ps
CPU time 688.08 seconds
Started Oct 02 08:16:44 PM UTC 24
Finished Oct 02 08:28:21 PM UTC 24
Peak memory 773400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045596057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3045596057
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/48.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/48.hmac_error.2698835050
Short name T483
Test name
Test status
Simulation time 14550552444 ps
CPU time 204.98 seconds
Started Oct 02 08:16:49 PM UTC 24
Finished Oct 02 08:20:17 PM UTC 24
Peak memory 210508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698835050 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2698835050
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/48.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/48.hmac_long_msg.114431849
Short name T479
Test name
Test status
Simulation time 13008288142 ps
CPU time 190.84 seconds
Started Oct 02 08:16:34 PM UTC 24
Finished Oct 02 08:19:48 PM UTC 24
Peak memory 219240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114431849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.114431849
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/48.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/48.hmac_smoke.21970344
Short name T459
Test name
Test status
Simulation time 5880964481 ps
CPU time 15.73 seconds
Started Oct 02 08:16:33 PM UTC 24
Finished Oct 02 08:16:50 PM UTC 24
Peak memory 210768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21970344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 48.hmac_smoke.21970344
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/48.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/48.hmac_stress_all.376564575
Short name T521
Test name
Test status
Simulation time 177053117580 ps
CPU time 3776.5 seconds
Started Oct 02 08:17:01 PM UTC 24
Finished Oct 02 09:20:40 PM UTC 24
Peak memory 837012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376564575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.376564575
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/48.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/48.hmac_wipe_secret.1396960070
Short name T469
Test name
Test status
Simulation time 15170501640 ps
CPU time 45.89 seconds
Started Oct 02 08:16:50 PM UTC 24
Finished Oct 02 08:17:37 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396960070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1396960070
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/48.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/49.hmac_alert_test.1289480062
Short name T471
Test name
Test status
Simulation time 44753774 ps
CPU time 0.89 seconds
Started Oct 02 08:17:59 PM UTC 24
Finished Oct 02 08:18:01 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289480062 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1289480062
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/49.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/49.hmac_back_pressure.3111577786
Short name T474
Test name
Test status
Simulation time 3366733886 ps
CPU time 81.69 seconds
Started Oct 02 08:17:11 PM UTC 24
Finished Oct 02 08:18:35 PM UTC 24
Peak memory 219100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111577786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3111577786
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/49.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/49.hmac_burst_wr.2599817034
Short name T468
Test name
Test status
Simulation time 81894822 ps
CPU time 2.64 seconds
Started Oct 02 08:17:23 PM UTC 24
Finished Oct 02 08:17:26 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599817034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2599817034
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/49.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/49.hmac_datapath_stress.1405970023
Short name T491
Test name
Test status
Simulation time 3083489970 ps
CPU time 544.67 seconds
Started Oct 02 08:17:11 PM UTC 24
Finished Oct 02 08:26:23 PM UTC 24
Peak memory 655016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405970023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1405970023
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/49.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/49.hmac_error.3367707142
Short name T475
Test name
Test status
Simulation time 1588694548 ps
CPU time 89.58 seconds
Started Oct 02 08:17:24 PM UTC 24
Finished Oct 02 08:18:55 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367707142 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3367707142
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/49.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/49.hmac_long_msg.2870636552
Short name T470
Test name
Test status
Simulation time 2259759479 ps
CPU time 47.99 seconds
Started Oct 02 08:17:08 PM UTC 24
Finished Oct 02 08:17:57 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870636552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2870636552
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/49.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/49.hmac_smoke.2566398593
Short name T467
Test name
Test status
Simulation time 1570055068 ps
CPU time 14.7 seconds
Started Oct 02 08:17:07 PM UTC 24
Finished Oct 02 08:17:23 PM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566398593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2566398593
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/49.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/49.hmac_stress_all.1307548567
Short name T84
Test name
Test status
Simulation time 166684512392 ps
CPU time 1098.7 seconds
Started Oct 02 08:17:38 PM UTC 24
Finished Oct 02 08:36:10 PM UTC 24
Peak memory 708228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307548567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1307548567
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/49.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/49.hmac_wipe_secret.2763979656
Short name T482
Test name
Test status
Simulation time 23469619303 ps
CPU time 158.38 seconds
Started Oct 02 08:17:27 PM UTC 24
Finished Oct 02 08:20:08 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763979656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2763979656
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/49.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/5.hmac_alert_test.3013155824
Short name T43
Test name
Test status
Simulation time 37655443 ps
CPU time 0.91 seconds
Started Oct 02 07:46:16 PM UTC 24
Finished Oct 02 07:46:18 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013155824 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3013155824
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/5.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/5.hmac_back_pressure.3185028857
Short name T185
Test name
Test status
Simulation time 1387857899 ps
CPU time 86.12 seconds
Started Oct 02 07:45:59 PM UTC 24
Finished Oct 02 07:47:27 PM UTC 24
Peak memory 210400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185028857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3185028857
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/5.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/5.hmac_burst_wr.4098255915
Short name T55
Test name
Test status
Simulation time 5335650325 ps
CPU time 52.28 seconds
Started Oct 02 07:46:01 PM UTC 24
Finished Oct 02 07:46:55 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098255915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.4098255915
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/5.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/5.hmac_datapath_stress.2140701402
Short name T294
Test name
Test status
Simulation time 8155160216 ps
CPU time 801.71 seconds
Started Oct 02 07:46:01 PM UTC 24
Finished Oct 02 07:59:31 PM UTC 24
Peak memory 705756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140701402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2140701402
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/5.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/5.hmac_long_msg.931771343
Short name T199
Test name
Test status
Simulation time 44373176299 ps
CPU time 178.54 seconds
Started Oct 02 07:45:59 PM UTC 24
Finished Oct 02 07:49:01 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931771343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.931771343
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/5.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/5.hmac_smoke.1394310451
Short name T40
Test name
Test status
Simulation time 5265108345 ps
CPU time 15.68 seconds
Started Oct 02 07:45:57 PM UTC 24
Finished Oct 02 07:46:15 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394310451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1394310451
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/5.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/5.hmac_stress_all.1283011057
Short name T81
Test name
Test status
Simulation time 172185575372 ps
CPU time 1974.41 seconds
Started Oct 02 07:46:14 PM UTC 24
Finished Oct 02 08:19:31 PM UTC 24
Peak memory 740616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283011057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1283011057
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/5.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/5.hmac_stress_all_with_rand_reset.277364257
Short name T19
Test name
Test status
Simulation time 11973509973 ps
CPU time 117.72 seconds
Started Oct 02 07:46:14 PM UTC 24
Finished Oct 02 07:48:15 PM UTC 24
Peak memory 221200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27736425
7 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.277364257
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/5.hmac_wipe_secret.2282154341
Short name T169
Test name
Test status
Simulation time 2976865704 ps
CPU time 31.87 seconds
Started Oct 02 07:46:01 PM UTC 24
Finished Oct 02 07:46:34 PM UTC 24
Peak memory 210704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282154341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2282154341
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/5.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/6.hmac_alert_test.4009306337
Short name T178
Test name
Test status
Simulation time 24502222 ps
CPU time 0.94 seconds
Started Oct 02 07:46:39 PM UTC 24
Finished Oct 02 07:46:41 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009306337 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.4009306337
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/6.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/6.hmac_back_pressure.409247550
Short name T22
Test name
Test status
Simulation time 7576184802 ps
CPU time 75 seconds
Started Oct 02 07:46:18 PM UTC 24
Finished Oct 02 07:47:35 PM UTC 24
Peak memory 210480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409247550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.409247550
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/6.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/6.hmac_burst_wr.891025759
Short name T188
Test name
Test status
Simulation time 5178860287 ps
CPU time 69.88 seconds
Started Oct 02 07:46:22 PM UTC 24
Finished Oct 02 07:47:34 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891025759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.891025759
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/6.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/6.hmac_datapath_stress.2755414874
Short name T277
Test name
Test status
Simulation time 8066335715 ps
CPU time 651.38 seconds
Started Oct 02 07:46:18 PM UTC 24
Finished Oct 02 07:57:17 PM UTC 24
Peak memory 683252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755414874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2755414874
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/6.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/6.hmac_error.1271096649
Short name T62
Test name
Test status
Simulation time 29831865153 ps
CPU time 132.21 seconds
Started Oct 02 07:46:23 PM UTC 24
Finished Oct 02 07:48:38 PM UTC 24
Peak memory 210428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271096649 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1271096649
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/6.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/6.hmac_long_msg.1742732107
Short name T186
Test name
Test status
Simulation time 5867498859 ps
CPU time 68.13 seconds
Started Oct 02 07:46:18 PM UTC 24
Finished Oct 02 07:47:28 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742732107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1742732107
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/6.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/6.hmac_smoke.1383257294
Short name T158
Test name
Test status
Simulation time 9492012490 ps
CPU time 20.65 seconds
Started Oct 02 07:46:18 PM UTC 24
Finished Oct 02 07:46:40 PM UTC 24
Peak memory 210508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383257294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1383257294
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/6.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/6.hmac_stress_all.574734031
Short name T235
Test name
Test status
Simulation time 179613405365 ps
CPU time 417.9 seconds
Started Oct 02 07:46:29 PM UTC 24
Finished Oct 02 07:53:33 PM UTC 24
Peak memory 449792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574734031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.574734031
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/6.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/7.hmac_alert_test.1950678836
Short name T183
Test name
Test status
Simulation time 15909931 ps
CPU time 1 seconds
Started Oct 02 07:47:17 PM UTC 24
Finished Oct 02 07:47:19 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950678836 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1950678836
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/7.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/7.hmac_back_pressure.480275896
Short name T192
Test name
Test status
Simulation time 2125711355 ps
CPU time 91.32 seconds
Started Oct 02 07:46:47 PM UTC 24
Finished Oct 02 07:48:20 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480275896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.480275896
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/7.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/7.hmac_burst_wr.3522928976
Short name T59
Test name
Test status
Simulation time 1677403822 ps
CPU time 23.54 seconds
Started Oct 02 07:46:50 PM UTC 24
Finished Oct 02 07:47:14 PM UTC 24
Peak memory 210580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522928976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3522928976
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/7.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/7.hmac_datapath_stress.3044621943
Short name T377
Test name
Test status
Simulation time 6366994702 ps
CPU time 1262.95 seconds
Started Oct 02 07:46:48 PM UTC 24
Finished Oct 02 08:08:04 PM UTC 24
Peak memory 785716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044621943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3044621943
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/7.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/7.hmac_error.2361987923
Short name T101
Test name
Test status
Simulation time 4385996246 ps
CPU time 170.78 seconds
Started Oct 02 07:46:51 PM UTC 24
Finished Oct 02 07:49:45 PM UTC 24
Peak memory 210592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361987923 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2361987923
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/7.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/7.hmac_long_msg.4176575108
Short name T163
Test name
Test status
Simulation time 2459900337 ps
CPU time 154.34 seconds
Started Oct 02 07:46:42 PM UTC 24
Finished Oct 02 07:49:20 PM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176575108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.4176575108
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/7.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/7.hmac_smoke.3077015748
Short name T171
Test name
Test status
Simulation time 50250965 ps
CPU time 3.66 seconds
Started Oct 02 07:46:41 PM UTC 24
Finished Oct 02 07:46:46 PM UTC 24
Peak memory 210560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077015748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3077015748
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/7.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/7.hmac_wipe_secret.1890255747
Short name T182
Test name
Test status
Simulation time 338344743 ps
CPU time 23.57 seconds
Started Oct 02 07:46:53 PM UTC 24
Finished Oct 02 07:47:18 PM UTC 24
Peak memory 210308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890255747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1890255747
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/7.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/8.hmac_alert_test.1381915666
Short name T45
Test name
Test status
Simulation time 30235729 ps
CPU time 0.92 seconds
Started Oct 02 07:47:36 PM UTC 24
Finished Oct 02 07:47:38 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381915666 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1381915666
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/8.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/8.hmac_back_pressure.1596130377
Short name T162
Test name
Test status
Simulation time 6449473230 ps
CPU time 99.33 seconds
Started Oct 02 07:47:21 PM UTC 24
Finished Oct 02 07:49:03 PM UTC 24
Peak memory 226832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596130377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1596130377
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/8.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/8.hmac_burst_wr.2809093765
Short name T46
Test name
Test status
Simulation time 863399778 ps
CPU time 13.6 seconds
Started Oct 02 07:47:28 PM UTC 24
Finished Oct 02 07:47:43 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809093765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2809093765
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/8.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/8.hmac_datapath_stress.3658845703
Short name T297
Test name
Test status
Simulation time 31238851877 ps
CPU time 747.06 seconds
Started Oct 02 07:47:21 PM UTC 24
Finished Oct 02 07:59:56 PM UTC 24
Peak memory 685376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658845703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3658845703
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/8.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/8.hmac_error.1933867761
Short name T48
Test name
Test status
Simulation time 1007064908 ps
CPU time 18.6 seconds
Started Oct 02 07:47:28 PM UTC 24
Finished Oct 02 07:47:48 PM UTC 24
Peak memory 210628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933867761 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1933867761
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/8.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/8.hmac_long_msg.406552620
Short name T196
Test name
Test status
Simulation time 20210244853 ps
CPU time 73.61 seconds
Started Oct 02 07:47:20 PM UTC 24
Finished Oct 02 07:48:35 PM UTC 24
Peak memory 210508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406552620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.406552620
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/8.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/8.hmac_smoke.1644067229
Short name T184
Test name
Test status
Simulation time 175371586 ps
CPU time 6.41 seconds
Started Oct 02 07:47:19 PM UTC 24
Finished Oct 02 07:47:26 PM UTC 24
Peak memory 210356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644067229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1644067229
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/8.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/8.hmac_stress_all.3477567977
Short name T73
Test name
Test status
Simulation time 222963259893 ps
CPU time 934.19 seconds
Started Oct 02 07:47:34 PM UTC 24
Finished Oct 02 08:03:20 PM UTC 24
Peak memory 685312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477567977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3477567977
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/8.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/8.hmac_wipe_secret.1986614234
Short name T135
Test name
Test status
Simulation time 1979042371 ps
CPU time 102.21 seconds
Started Oct 02 07:47:30 PM UTC 24
Finished Oct 02 07:49:14 PM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986614234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1986614234
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/8.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/9.hmac_alert_test.2672608952
Short name T189
Test name
Test status
Simulation time 57245354 ps
CPU time 0.92 seconds
Started Oct 02 07:48:08 PM UTC 24
Finished Oct 02 07:48:11 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672608952 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2672608952
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/9.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/9.hmac_back_pressure.1993236778
Short name T52
Test name
Test status
Simulation time 1412813177 ps
CPU time 22.29 seconds
Started Oct 02 07:47:44 PM UTC 24
Finished Oct 02 07:48:07 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993236778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1993236778
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/9.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/9.hmac_burst_wr.1922453723
Short name T166
Test name
Test status
Simulation time 3269208800 ps
CPU time 24.46 seconds
Started Oct 02 07:47:50 PM UTC 24
Finished Oct 02 07:48:16 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922453723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1922453723
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/9.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/9.hmac_datapath_stress.1456637949
Short name T314
Test name
Test status
Simulation time 4120446895 ps
CPU time 832.01 seconds
Started Oct 02 07:47:50 PM UTC 24
Finished Oct 02 08:01:52 PM UTC 24
Peak memory 697688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456637949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1456637949
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/9.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/9.hmac_error.1130304076
Short name T210
Test name
Test status
Simulation time 10491284494 ps
CPU time 161.28 seconds
Started Oct 02 07:47:50 PM UTC 24
Finished Oct 02 07:50:35 PM UTC 24
Peak memory 210848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130304076 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1130304076
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/9.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/9.hmac_long_msg.3881074144
Short name T50
Test name
Test status
Simulation time 2044467921 ps
CPU time 16.12 seconds
Started Oct 02 07:47:39 PM UTC 24
Finished Oct 02 07:47:57 PM UTC 24
Peak memory 210296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881074144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3881074144
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/9.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/9.hmac_smoke.2124538726
Short name T49
Test name
Test status
Simulation time 3962020491 ps
CPU time 11.7 seconds
Started Oct 02 07:47:36 PM UTC 24
Finished Oct 02 07:47:49 PM UTC 24
Peak memory 210564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124538726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2124538726
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/9.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/9.hmac_stress_all.1995554635
Short name T53
Test name
Test status
Simulation time 178484411 ps
CPU time 11.82 seconds
Started Oct 02 07:47:58 PM UTC 24
Finished Oct 02 07:48:11 PM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995554635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1995554635
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/9.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/default/9.hmac_wipe_secret.1762661088
Short name T190
Test name
Test status
Simulation time 1335725009 ps
CPU time 17.48 seconds
Started Oct 02 07:47:53 PM UTC 24
Finished Oct 02 07:48:12 PM UTC 24
Peak memory 210348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762661088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1762661088
Directory /workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/9.hmac_wipe_secret/latest
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