Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16526676	1			T1	110		T4	3		T5	4416
all_values[1]	16526676	1			T1	110		T4	3		T5	4416
all_values[2]	16526676	1			T1	110		T4	3		T5	4416

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

217307

1

T1

87

T5

1738

T6

2

auto[1]

49362721

1

T1

243

T4

9

T5

11510

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42395204

1

T1

312

T4

8

T5

11461

auto[1]

7184824

1

T1

18

T4

1

T5

1787

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	80257	1			T5	1738		T137	610		T139	3
all_values[0]	auto[0]	auto[1]	351	1			T137	2		T77	2		T138	2
all_values[0]	auto[1]	auto[0]	16427803	1			T1	108		T4	2		T5	2676
all_values[0]	auto[1]	auto[1]	18265	1			T1	2		T4	1		T5	2
all_values[1]	auto[0]	auto[0]	63068	1			T1	87		T32	407		T20	1
all_values[1]	auto[0]	auto[1]	208	1			T56	1		T67	5		T21	4
all_values[1]	auto[1]	auto[0]	16463059	1			T1	23		T4	3		T5	4416
all_values[1]	auto[1]	auto[1]	341	1			T7	4		T30	2		T31	3
all_values[2]	auto[0]	auto[0]	36712	1			T6	1		T9	1076		T15	76
all_values[2]	auto[0]	auto[1]	36711	1			T6	1		T15	91		T32	619
all_values[2]	auto[1]	auto[0]	9324305	1			T1	94		T4	3		T5	2631
all_values[2]	auto[1]	auto[1]	7128948	1			T1	16		T5	1785		T6	1