Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

128745

1

T1

2

T6

8

T7

732

auto[1]

109650

1

T4

4

T5

10

T7

252

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	92374	1			T5	3		T7	430		T8	15
len_1026_2046	5400	1			T7	15		T10	1		T13	29
len_514_1022	3452	1			T7	4		T9	1		T14	1
len_2_510	3432	1			T7	2		T15	1		T13	179
len_2056	291	1			T47	1		T60	3		T73	4
len_2048	268	1			T11	1		T13	2		T30	2
len_2040	122	1			T6	1		T47	6		T149	1
len_1032	116	1			T1	1		T6	1		T10	2
len_1024	1763	1			T7	1		T15	1		T11	1
len_1016	127	1			T47	3		T60	1		T149	2
len_520	163	1			T60	4		T150	5		T73	1
len_512	276	1			T13	1		T46	1		T31	1
len_504	151	1			T47	1		T60	4		T149	1
len_8	1008	1			T151	2		T152	2		T24	1
len_0	10255	1			T4	2		T5	2		T6	2

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

127

1

T15

1

T13

2

T47

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	51044	1			T7	309		T8	8		T9	3
auto[0]	len_1026_2046	3445	1			T7	11		T13	24		T30	16
auto[0]	len_514_1022	2039	1			T7	3		T9	1		T14	1
auto[0]	len_2_510	2249	1			T7	2		T15	1		T13	12
auto[0]	len_2056	91	1			T60	2		T73	3		T74	7
auto[0]	len_2048	159	1			T11	1		T13	2		T30	1
auto[0]	len_2040	63	1			T6	1		T47	3		T149	1
auto[0]	len_1032	58	1			T1	1		T6	1		T10	1
auto[0]	len_1024	236	1			T7	1		T15	1		T11	1
auto[0]	len_1016	75	1			T47	2		T60	1		T149	2
auto[0]	len_520	85	1			T60	1		T150	2		T38	6
auto[0]	len_512	172	1			T13	1		T46	1		T60	1
auto[0]	len_504	88	1			T47	1		T149	1		T77	1
auto[0]	len_8	37	1			T153	2		T154	2		T155	2
auto[0]	len_0	4532	1			T6	2		T7	40		T14	3
auto[1]	len_2050_plus	41330	1			T5	3		T7	121		T8	7
auto[1]	len_1026_2046	1955	1			T7	4		T10	1		T13	5
auto[1]	len_514_1022	1413	1			T7	1		T13	155		T30	5
auto[1]	len_2_510	1183	1			T13	167		T30	1		T31	2
auto[1]	len_2056	200	1			T47	1		T60	1		T73	1
auto[1]	len_2048	109	1			T30	1		T47	2		T60	2
auto[1]	len_2040	59	1			T47	3		T97	1		T150	1
auto[1]	len_1032	58	1			T10	1		T149	1		T34	1
auto[1]	len_1024	1527	1			T57	66		T13	1		T30	1
auto[1]	len_1016	52	1			T47	1		T19	2		T156	1
auto[1]	len_520	78	1			T60	3		T150	3		T73	1
auto[1]	len_512	104	1			T31	1		T60	3		T74	1
auto[1]	len_504	63	1			T60	4		T77	1		T157	1
auto[1]	len_8	971	1			T151	2		T152	2		T24	1
auto[1]	len_0	5723	1			T4	2		T5	2		T9	1

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

71

1

T15

1

T13

2

T46

1

auto[1]

len_upper

56

1

T47

1

T46

3

T149

1