Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4262627

1

T1

28

T4

1

T5

877

auto[1]

2541473

1

T1

14

T5

446

T6

47

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2563919

1

T1

14

T5

878

T6

48

auto[1]

4240181

1

T1

28

T4

1

T5

445

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3114046

1

T1

42

T6

70

T7

5185

auto[1]

3690054

1

T4

1

T5

1323

T6

2

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4324503

1

T1

42

T5

3

T6

1

auto[1]

2479597

1

T4

1

T5

1320

T6

71

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6112242	1			T1	42		T4	1		T5	1300
fifo_depth[1]	107326	1			T5	18		T7	14		T9	37
fifo_depth[2]	80846	1			T5	5		T6	2		T7	45
fifo_depth[3]	65121	1			T6	1		T7	16		T9	4
fifo_depth[4]	61411	1			T6	2		T7	121		T8	1
fifo_depth[5]	49584	1			T6	1		T7	29		T14	3
fifo_depth[6]	40364	1			T6	2		T7	79		T14	3
fifo_depth[7]	26981	1			T7	64		T8	1		T14	1

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

691858

1

T5

23

T6

9

T7

7253

auto[1]

6112242

1

T1

42

T4

1

T5

1300

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6791098

1

T1

42

T4

1

T5

1323

auto[1]

13002

1

T7

262

T30

988

T31

297

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

33838

1

T7

182

T30

955

T129

7

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

26222

1

T7

11

T8

1

T15

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

40243

1

T8

1

T9

23

T11

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

31655

1

T6

5

T7

1541

T13

21

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

108580

1

T7

1054

T11

1

T13

13

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

29696

1

T6

4

T11

1

T13

11

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

34441

1

T7

315

T11

2

T30

1700

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

32268

1

T7

1743

T9

16

T11

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

40494

1

T9

8

T13

23

T30

404

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

43525

1

T5

23

T11

1

T13

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

45092

1

T7

465

T10

2

T13

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

43519

1

T8

1

T9

5

T14

22

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

55637

1

T7

571

T11

1

T57

968

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

35189

1

T10

2

T13

7

T137

13

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

48351

1

T7

1371

T8

1

T13

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

43108

1

T8

1

T13

14

T30

1128

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

162080

1

T7

61

T9

1

T14

337

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

147587

1

T7

27

T8

1

T15

57

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

153006

1

T1

14

T7

159

T9

459

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

136452

1

T6

41

T7

57

T8

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1732789

1

T1

28

T6

1

T7

14

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

140489

1

T6

19

T8

1

T9

537

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

147653

1

T7

5

T8

2

T14

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

157047

1

T7

16

T9

743

T11

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

438520

1

T8

2

T9

725

T13

154

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

386048

1

T5

853

T6

1

T8

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

415980

1

T5

2

T7

3

T9

363

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

419658

1

T6

1

T7

76

T9

476

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

480947

1

T5

1

T7

86

T8

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

400986

1

T4

1

T7

35

T10

23

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

386852

1

T7

139

T8

2

T9

18

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

406148

1

T5

444

T8

1

T9

1

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

193569

1

T7

240

T9

1

T14

337

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

173484

1

T7

38

T8

2

T15

64

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

190996

1

T1

14

T7

159

T8

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

167753

1

T6

46

T7

1587

T8

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1840631

1

T1

28

T6

1

T7

1002

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

169568

1

T6

23

T8

1

T9

537

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

180931

1

T7

312

T8

2

T14

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

188615

1

T7

1663

T9

759

T11

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

478655

1

T8

2

T9

733

T13

177

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

428890

1

T5

876

T6

1

T8

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

459900

1

T5

2

T7

465

T9

363

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

462803

1

T6

1

T7

76

T8

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

535987

1

T5

1

T7

657

T8

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

435838

1

T4

1

T7

35

T10

25

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

434296

1

T7

1435

T8

3

T9

18

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

449182

1

T5

444

T8

2

T9

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

2349

1

T7

3

T30

59

T160

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

325

1

T160

44

T161

1

T48

11

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

2253

1

T30

11

T162

2

T48

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

354

1

T7

11

T31

3

T162

22

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

738

1

T7

66

T31

41

T162

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

617

1

T31

2

T162

6

T160

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1163

1

T7

8

T30

660

T31

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

700

1

T7

96

T30

7

T163

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

359

1

T30

108

T163

3

T164

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

683

1

T30

5

T31

226

T163

11

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1172

1

T7

3

T160

40

T164

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

374

1

T89

7

T161

144

T165

22

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

597

1

T30

1

T162

1

T21

56

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

337

1

T89

23

T21

22

T48

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

907

1

T7

75

T30

136

T160

194

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

74

1

T30

1

T31

19

T166

9

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

162080

1

T7

61

T9

1

T14

337

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

147587

1

T7

27

T8

1

T15

57

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

153006

1

T1

14

T7

159

T9

459

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

136452

1

T6

41

T7

57

T8

2

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1732789

1

T1

28

T6

1

T7

14

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

140489

1

T6

19

T8

1

T9

537

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

147653

1

T7

5

T8

2

T14

1

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

157047

1

T7

16

T9

743

T11

1

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

438520

1

T8

2

T9

725

T13

154

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

386048

1

T5

853

T6

1

T8

2

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

415980

1

T5

2

T7

3

T9

363

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

419658

1

T6

1

T7

76

T9

476

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

480947

1

T5

1

T7

86

T8

1

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

400986

1

T4

1

T7

35

T10

23

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

386852

1

T7

139

T8

2

T9

18

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

406148

1

T5

444

T8

1

T9

1

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3673

1

T30

8

T129

7

T47

2

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

2990

1

T7

2

T16

13

T30

15

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3227

1

T9

16

T16

5

T30

3

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3093

1

T7

7

T13

8

T16

8

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

34474

1

T13

13

T16

5

T52

111

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

2743

1

T16

31

T137

8

T97

17

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3603

1

T52

17

T31

7

T167

6

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3328

1

T7

1

T9

11

T13

5

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

5675

1

T9

7

T13

1

T30

9

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

5541

1

T5

18

T13

1

T16

12

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

6581

1

T10

1

T129

3

T47

1

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

6515

1

T9

3

T14

6

T129

8

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

7988

1

T7

4

T57

202

T13

9

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

5027

1

T10

1

T13

1

T137

8

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

6082

1

T16

16

T129

5

T47

1

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

6786

1

T13

2

T30

12

T47

1

fifo_depth[2]

auto[0]

auto[0]

auto[0]

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3

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7

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3

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1

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17

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8

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10

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1

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15

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13

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192

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8

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3

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4

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5

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16

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6

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1

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18

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10

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7

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2

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2

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1

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24

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6

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4

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12

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3

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4

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9

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1

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1

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10

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1

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1

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5

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7

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5

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1

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5

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178

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7

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1

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1

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11

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1

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1

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5

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3

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10

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1

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5

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12

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3

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1

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12

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4

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34

fifo_depth[4]

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16

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1

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9

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1

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7

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9

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4

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6

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6

fifo_depth[4]

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40

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5

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4

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4

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11

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16

fifo_depth[4]

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6

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34

fifo_depth[4]

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6

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3

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4

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1

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11

fifo_depth[4]

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41

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174

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6

fifo_depth[4]

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1

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1

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16

fifo_depth[4]

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1

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1

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11

fifo_depth[4]

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78

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8

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10

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13

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1

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26

fifo_depth[5]

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1

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15

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29

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49

fifo_depth[5]

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1

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8

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2

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4

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1

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1

fifo_depth[5]

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12

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6

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4

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3

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7

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15

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3

fifo_depth[5]

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1

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18

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43

fifo_depth[5]

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1

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6

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1

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4

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T7

5

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120

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3

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1

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17

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1

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1

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3

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10

fifo_depth[5]

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11

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2

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6

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1

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17

fifo_depth[6]

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7

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4

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18

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15

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8

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5

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5

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5

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10

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11

fifo_depth[6]

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12

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15

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4

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1

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7

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3

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8

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5

fifo_depth[6]

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1

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39

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64

T30

3

fifo_depth[6]

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1

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1

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12

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1

fifo_depth[6]

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1

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3

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8

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1

fifo_depth[6]

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1

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2

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75

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6

fifo_depth[7]

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1

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6

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2

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5

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1

T30

24

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1

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2

fifo_depth[7]

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1

T8

1

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17

T168

1

fifo_depth[7]

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1

T7

8

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7

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12

fifo_depth[7]

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1

T7

34

T168

5

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4

fifo_depth[7]

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1

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1

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13

T97

3

fifo_depth[7]

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1

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1

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8

T97

3

fifo_depth[7]

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1

T13

1

T30

4

T52

5

fifo_depth[7]

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1

T13

1

T30

9

T97

5

fifo_depth[7]

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1

T97

11

T163

41

T159

10

fifo_depth[7]

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1

T7

1

T30

7

T168

3

fifo_depth[7]

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1

T14

1

T103

8

T163

9

fifo_depth[7]

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1

T7

6

T57

26

T58

138

fifo_depth[7]

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1

T103

7

T170

1

T73

1

fifo_depth[7]

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1

T7

15

T31

4

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6

fifo_depth[7]

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2421

1

T13

1

T30

13

T97

3