Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16526676	1			T1	110		T4	3		T5	4416
all_pins[1]	16526676	1			T1	110		T4	3		T5	4416
all_pins[2]	16526676	1			T1	110		T4	3		T5	4416

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	42431620	1			T1	311		T4	8		T5	11461
values[0x1]	7148408	1			T1	19		T4	1		T5	1787
transitions[0x0=>0x1]	7148217	1			T1	19		T4	1		T5	1787
transitions[0x1=>0x0]	7148234	1			T1	19		T4	1		T5	1787

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	16507584	1			T1	107		T4	2		T5	4414
all_pins[0]	values[0x1]	19092	1			T1	3		T4	1		T5	2
all_pins[0]	transitions[0x0=>0x1]	19009	1			T1	3		T4	1		T5	2
all_pins[0]	transitions[0x1=>0x0]	7128882	1			T1	16		T5	1785		T6	1
all_pins[1]	values[0x0]	16526308	1			T1	110		T4	3		T5	4416
all_pins[1]	values[0x1]	368	1			T7	5		T30	2		T31	4
all_pins[1]	transitions[0x0=>0x1]	307	1			T7	5		T30	2		T31	4
all_pins[1]	transitions[0x1=>0x0]	19031	1			T1	3		T4	1		T5	2
all_pins[2]	values[0x0]	9397728	1			T1	94		T4	3		T5	2631
all_pins[2]	values[0x1]	7128948	1			T1	16		T5	1785		T6	1
all_pins[2]	transitions[0x0=>0x1]	7128901	1			T1	16		T5	1785		T6	1
all_pins[2]	transitions[0x1=>0x0]	321	1			T7	5		T30	2		T31	4