Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1010 1 T56 4 T23 7 T67 30
all_values[1] 1010 1 T56 4 T23 7 T67 30
all_values[2] 1010 1 T56 4 T23 7 T67 30


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1564 1 T56 4 T23 7 T67 36
auto[1] 1466 1 T56 8 T23 14 T67 54


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1060 1 T56 1 T23 8 T67 34
auto[1] 1970 1 T56 11 T23 13 T67 56


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1725 1 T56 5 T23 12 T67 55
auto[1] 1305 1 T56 7 T23 9 T67 35


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 179 1 T23 1 T67 8 T21 5
all_values[0] auto[0] auto[0] auto[1] 104 1 T21 3 T22 4 T140 10
all_values[0] auto[0] auto[1] auto[0] 173 1 T23 1 T67 13 T21 1
all_values[0] auto[0] auto[1] auto[1] 112 1 T56 2 T23 1 T21 1
all_values[0] auto[1] auto[0] auto[1] 224 1 T23 2 T67 4 T21 4
all_values[0] auto[1] auto[1] auto[1] 218 1 T56 2 T23 2 T67 5
all_values[1] auto[0] auto[0] auto[0] 183 1 T23 2 T67 4 T21 2
all_values[1] auto[0] auto[0] auto[1] 131 1 T67 5 T21 1 T81 1
all_values[1] auto[0] auto[1] auto[0] 151 1 T56 1 T23 3 T67 3
all_values[1] auto[0] auto[1] auto[1] 123 1 T56 1 T23 1 T67 6
all_values[1] auto[1] auto[0] auto[1] 218 1 T56 1 T67 2 T21 4
all_values[1] auto[1] auto[1] auto[1] 204 1 T56 1 T23 1 T67 10
all_values[2] auto[0] auto[0] auto[0] 200 1 T67 2 T21 5 T22 4
all_values[2] auto[0] auto[0] auto[1] 94 1 T56 1 T23 2 T67 6
all_values[2] auto[0] auto[1] auto[0] 174 1 T23 1 T67 4 T21 1
all_values[2] auto[0] auto[1] auto[1] 101 1 T67 4 T21 1 T81 1
all_values[2] auto[1] auto[0] auto[1] 231 1 T56 2 T67 5 T21 3
all_values[2] auto[1] auto[1] auto[1] 210 1 T56 1 T23 4 T67 9


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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