Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	3722	1			T5	1		T6	1		T7	3
sha2_none	3635	1			T1	1		T5	1		T6	1
sha2_512	7011	1			T6	1		T7	3		T8	6
sha2_384	6722	1			T5	1		T7	9		T8	2
sha2_256	5734	1			T1	1		T4	1		T5	1

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17276

1

T1

1

T4

1

T5

3

auto[1]

9864

1

T1

1

T5

2

T6

2

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9872

1

T1

1

T5

3

T6

3

auto[1]

17268

1

T1

1

T4

1

T5

2

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

13912

1

T4

1

T5

4

T6

2

disabled

13228

1

T1

2

T5

1

T6

3

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4058	1			T1	1		T5	2		T6	2
key_none	7454	1			T5	1		T6	1		T7	4
key_1024	3953	1			T5	1		T7	1		T8	6
key_512	3331	1			T7	5		T8	1		T9	1
key_384	3047	1			T1	1		T7	7		T8	4
key_256	2688	1			T6	1		T7	3		T8	1
key_128	2537	1			T4	1		T5	1		T6	1

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17393

1

T1

2

T5

2

T6

1

auto[1]

9747

1

T4

1

T5

3

T6

4

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

26997

1

T1

2

T4

1

T5

5

disabled

143

1

T52

1

T55

3

T56

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1402

1

T7

1

T8

2

T9

2

enabled

auto[0]

auto[0]

auto[1]

1402

1

T5

1

T6

1

T8

2

enabled

auto[0]

auto[1]

auto[0]

1442

1

T5

1

T7

1

T9

1

enabled

auto[0]

auto[1]

auto[1]

1380

1

T6

1

T7

1

T8

1

enabled

auto[1]

auto[0]

auto[0]

4050

1

T5

1

T7

2

T8

1

enabled

auto[1]

auto[0]

auto[1]

1395

1

T4

1

T7

1

T10

1

enabled

auto[1]

auto[1]

auto[0]

1455

1

T7

4

T8

3

T9

1

enabled

auto[1]

auto[1]

auto[1]

1386

1

T5

1

T8

2

T9

1

disabled

auto[0]

auto[0]

auto[0]

1097

1

T7

3

T9

1

T14

2

disabled

auto[0]

auto[0]

auto[1]

1041

1

T5

1

T7

2

T8

2

disabled

auto[0]

auto[1]

auto[0]

1058

1

T1

1

T7

1

T8

1

disabled

auto[0]

auto[1]

auto[1]

1050

1

T6

1

T7

3

T8

2

disabled

auto[1]

auto[0]

auto[0]

5853

1

T1

1

T6

1

T7

2

disabled

auto[1]

auto[0]

auto[1]

1036

1

T6

1

T8

1

T9

2

disabled

auto[1]

auto[1]

auto[0]

1036

1

T7

1

T8

2

T14

1

disabled

auto[1]

auto[1]

auto[1]

1057

1

T7

3

T9

2

T11

3

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

13863

1

T4

1

T5

4

T6

2

enabled

disabled

49

1

T55

2

T56

1

T80

2

disabled

disabled

94

1

T52

1

T55

1

T80

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

13134

1

T1

2

T5

1

T6

3

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1001	1			T5	1		T14	2		T10	1
key_invalid	sha2_none	761	1			T7	3		T8	1		T9	3
key_invalid	sha2_512	693	1			T9	1		T13	4		T30	2
key_invalid	sha2_384	731	1			T7	1		T9	1		T14	1
key_invalid	sha2_256	782	1			T1	1		T6	2		T7	1
key_none	sha2_invalid	429	1			T7	2		T14	1		T11	2
key_none	sha2_none	482	1			T5	1		T8	1		T11	1
key_none	sha2_512	2478	1			T6	1		T8	1		T9	1
key_none	sha2_384	2488	1			T7	1		T8	1		T15	1
key_none	sha2_256	1530	1			T7	1		T8	1		T10	1
key_1024	sha2_invalid	447	1			T8	2		T11	1		T13	2
key_1024	sha2_none	485	1			T8	2		T11	2		T13	1
key_1024	sha2_512	1669	1			T8	1		T9	1		T10	1
key_1024	sha2_384	778	1			T5	1		T7	1		T8	1
key_512	sha2_invalid	472	1			T9	1		T30	2		T129	1
key_512	sha2_none	458	1			T7	1		T13	3		T12	1
key_512	sha2_512	572	1			T7	2		T8	1		T13	2
key_512	sha2_384	1081	1			T7	2		T11	1		T16	1
key_512	sha2_256	711	1			T11	1		T57	45		T13	3
key_384	sha2_invalid	439	1			T7	1		T15	1		T11	1
key_384	sha2_none	501	1			T1	1		T11	1		T13	1
key_384	sha2_512	526	1			T7	1		T8	3		T9	1
key_384	sha2_384	576	1			T7	2		T9	1		T14	1
key_384	sha2_256	964	1			T7	3		T8	1		T10	1
key_256	sha2_invalid	454	1			T8	1		T9	1		T47	3
key_256	sha2_none	464	1			T6	1		T14	1		T13	1
key_256	sha2_512	536	1			T11	4		T13	2		T16	1
key_256	sha2_384	541	1			T7	2		T14	1		T11	1
key_256	sha2_256	662	1			T7	1		T9	1		T14	1
key_128	sha2_invalid	460	1			T6	1		T30	1		T129	1
key_128	sha2_none	473	1			T8	1		T14	1		T10	1
key_128	sha2_512	525	1			T9	2		T14	1		T15	2
key_128	sha2_384	514	1			T16	1		T30	1		T47	4
key_128	sha2_256	528	1			T4	1		T5	1		T14	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

542

1

T11

2

T13

1

T16

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1001	1			T5	1		T14	2		T10	1
key_invalid	sha2_none	761	1			T7	3		T8	1		T9	3
key_invalid	sha2_512	693	1			T9	1		T13	4		T30	2
key_invalid	sha2_384	731	1			T7	1		T9	1		T14	1
key_invalid	sha2_256	782	1			T1	1		T6	2		T7	1
key_none	sha2_invalid	429	1			T7	2		T14	1		T11	2
key_none	sha2_none	482	1			T5	1		T8	1		T11	1
key_none	sha2_512	2478	1			T6	1		T8	1		T9	1
key_none	sha2_384	2488	1			T7	1		T8	1		T15	1
key_none	sha2_256	1530	1			T7	1		T8	1		T10	1
key_1024	sha2_invalid	447	1			T8	2		T11	1		T13	2
key_1024	sha2_none	485	1			T8	2		T11	2		T13	1
key_1024	sha2_512	1669	1			T8	1		T9	1		T10	1
key_1024	sha2_384	778	1			T5	1		T7	1		T8	1
key_1024	sha2_256	542	1			T11	2		T13	1		T16	1
key_512	sha2_invalid	472	1			T9	1		T30	2		T129	1
key_512	sha2_none	458	1			T7	1		T13	3		T12	1
key_512	sha2_512	572	1			T7	2		T8	1		T13	2
key_512	sha2_384	1081	1			T7	2		T11	1		T16	1
key_512	sha2_256	711	1			T11	1		T57	45		T13	3
key_384	sha2_invalid	439	1			T7	1		T15	1		T11	1
key_384	sha2_none	501	1			T1	1		T11	1		T13	1
key_384	sha2_512	526	1			T7	1		T8	3		T9	1
key_384	sha2_384	576	1			T7	2		T9	1		T14	1
key_384	sha2_256	964	1			T7	3		T8	1		T10	1
key_256	sha2_invalid	454	1			T8	1		T9	1		T47	3
key_256	sha2_none	464	1			T6	1		T14	1		T13	1
key_256	sha2_512	536	1			T11	4		T13	2		T16	1
key_256	sha2_384	541	1			T7	2		T14	1		T11	1
key_256	sha2_256	662	1			T7	1		T9	1		T14	1
key_128	sha2_invalid	460	1			T6	1		T30	1		T129	1
key_128	sha2_none	473	1			T8	1		T14	1		T10	1
key_128	sha2_512	525	1			T9	2		T14	1		T15	2
key_128	sha2_384	514	1			T16	1		T30	1		T47	4
key_128	sha2_256	528	1			T4	1		T5	1		T14	1