| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.62 | 95.37 | 97.22 | 100.00 | 94.12 | 98.25 | 98.52 | 99.85 |
| T70 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.3684213116 | Oct 09 07:12:53 AM UTC 24 | Oct 09 07:12:57 AM UTC 24 | 358049992 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3505603974 | Oct 09 07:12:54 AM UTC 24 | Oct 09 07:12:57 AM UTC 24 | 86328006 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2133519390 | Oct 09 07:12:53 AM UTC 24 | Oct 09 07:12:57 AM UTC 24 | 81802171 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1447459059 | Oct 09 07:12:54 AM UTC 24 | Oct 09 07:12:58 AM UTC 24 | 109148968 ps | ||
| T528 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.494222811 | Oct 09 07:12:56 AM UTC 24 | Oct 09 07:12:58 AM UTC 24 | 21040265 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.2982852068 | Oct 09 07:12:53 AM UTC 24 | Oct 09 07:12:59 AM UTC 24 | 283632697 ps | ||
| T529 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.1669381404 | Oct 09 07:12:57 AM UTC 24 | Oct 09 07:13:00 AM UTC 24 | 57940154 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.1265408409 | Oct 09 07:12:57 AM UTC 24 | Oct 09 07:13:00 AM UTC 24 | 87377806 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.21826149 | Oct 09 07:12:55 AM UTC 24 | Oct 09 07:13:00 AM UTC 24 | 105392740 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.3686778160 | Oct 09 07:12:55 AM UTC 24 | Oct 09 07:13:02 AM UTC 24 | 164145887 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2857923627 | Oct 09 07:12:59 AM UTC 24 | Oct 09 07:13:02 AM UTC 24 | 306392453 ps | ||
| T530 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.3218867641 | Oct 09 07:13:01 AM UTC 24 | Oct 09 07:13:03 AM UTC 24 | 11572496 ps | ||
| T531 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.1393337869 | Oct 09 07:12:54 AM UTC 24 | Oct 09 07:13:03 AM UTC 24 | 1147312717 ps | ||
| T532 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.2213965666 | Oct 09 07:12:59 AM UTC 24 | Oct 09 07:13:03 AM UTC 24 | 221826712 ps | ||
| T533 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.2454281244 | Oct 09 07:13:01 AM UTC 24 | Oct 09 07:13:03 AM UTC 24 | 55068486 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.1865848879 | Oct 09 07:13:01 AM UTC 24 | Oct 09 07:13:03 AM UTC 24 | 183847988 ps | ||
| T534 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.2346012821 | Oct 09 07:12:54 AM UTC 24 | Oct 09 07:13:03 AM UTC 24 | 530425881 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2841592185 | Oct 09 07:13:02 AM UTC 24 | Oct 09 07:13:05 AM UTC 24 | 44731243 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.3357467525 | Oct 09 07:13:00 AM UTC 24 | Oct 09 07:13:05 AM UTC 24 | 237290843 ps | ||
| T535 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.83750148 | Oct 09 07:12:50 AM UTC 24 | Oct 09 07:13:06 AM UTC 24 | 2939746350 ps | ||
| T536 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.896394719 | Oct 09 07:13:04 AM UTC 24 | Oct 09 07:13:06 AM UTC 24 | 31123586 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.2341369124 | Oct 09 07:13:05 AM UTC 24 | Oct 09 07:13:07 AM UTC 24 | 40509546 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.2832497968 | Oct 09 07:13:04 AM UTC 24 | Oct 09 07:13:07 AM UTC 24 | 54248956 ps | ||
| T537 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.1524854109 | Oct 09 07:13:01 AM UTC 24 | Oct 09 07:13:08 AM UTC 24 | 2169707808 ps | ||
| T538 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.60873944 | Oct 09 07:13:03 AM UTC 24 | Oct 09 07:13:08 AM UTC 24 | 216753705 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.1234293761 | Oct 09 07:12:59 AM UTC 24 | Oct 09 07:13:08 AM UTC 24 | 303187905 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.641012283 | Oct 09 07:13:06 AM UTC 24 | Oct 09 07:13:09 AM UTC 24 | 230263397 ps | ||
| T539 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.2633208435 | Oct 09 07:13:07 AM UTC 24 | Oct 09 07:13:09 AM UTC 24 | 46392280 ps | ||
| T540 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.1010609175 | Oct 09 07:13:07 AM UTC 24 | Oct 09 07:13:09 AM UTC 24 | 19809227 ps | ||
| T541 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.29139503 | Oct 09 07:13:06 AM UTC 24 | Oct 09 07:13:10 AM UTC 24 | 68694797 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.2068570510 | Oct 09 07:13:04 AM UTC 24 | Oct 09 07:13:10 AM UTC 24 | 1041269792 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.2000191383 | Oct 09 07:13:07 AM UTC 24 | Oct 09 07:13:11 AM UTC 24 | 256377954 ps | ||
| T542 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.423557610 | Oct 09 07:13:08 AM UTC 24 | Oct 09 07:13:11 AM UTC 24 | 33816528 ps | ||
| T543 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.1075384516 | Oct 09 07:13:09 AM UTC 24 | Oct 09 07:13:12 AM UTC 24 | 24681074 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.697830530 | Oct 09 07:13:09 AM UTC 24 | Oct 09 07:13:12 AM UTC 24 | 33425270 ps | ||
| T544 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.2248977785 | Oct 09 07:13:07 AM UTC 24 | Oct 09 07:13:12 AM UTC 24 | 57022106 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.1412303269 | Oct 09 07:13:01 AM UTC 24 | Oct 09 07:13:13 AM UTC 24 | 302722882 ps | ||
| T545 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.4201282111 | Oct 09 07:13:09 AM UTC 24 | Oct 09 07:13:13 AM UTC 24 | 41701253 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.3451370145 | Oct 09 07:13:09 AM UTC 24 | Oct 09 07:13:13 AM UTC 24 | 364094458 ps | ||
| T546 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.4264155891 | Oct 09 07:13:11 AM UTC 24 | Oct 09 07:13:13 AM UTC 24 | 146112332 ps | ||
| T547 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4100965465 | Oct 09 07:13:11 AM UTC 24 | Oct 09 07:13:13 AM UTC 24 | 25813713 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.4011240230 | Oct 09 07:13:06 AM UTC 24 | Oct 09 07:13:13 AM UTC 24 | 662838264 ps | ||
| T548 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.2674713009 | Oct 09 07:13:14 AM UTC 24 | Oct 09 07:13:20 AM UTC 24 | 234866289 ps | ||
| T549 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.2610633877 | Oct 09 07:13:05 AM UTC 24 | Oct 09 07:13:21 AM UTC 24 | 1231520411 ps | ||
| T550 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.756415995 | Oct 09 07:13:08 AM UTC 24 | Oct 09 07:13:13 AM UTC 24 | 373351120 ps | ||
| T551 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.569649378 | Oct 09 07:13:12 AM UTC 24 | Oct 09 07:13:14 AM UTC 24 | 26172339 ps | ||
| T552 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.4116188728 | Oct 09 07:13:12 AM UTC 24 | Oct 09 07:13:14 AM UTC 24 | 98326736 ps | ||
| T553 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3225159954 | Oct 09 07:13:11 AM UTC 24 | Oct 09 07:13:15 AM UTC 24 | 111402622 ps | ||
| T554 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.2355040768 | Oct 09 07:12:57 AM UTC 24 | Oct 09 07:13:21 AM UTC 24 | 3269110998 ps | ||
| T555 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.2899463213 | Oct 09 07:13:14 AM UTC 24 | Oct 09 07:13:16 AM UTC 24 | 33875145 ps | ||
| T556 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.1599377476 | Oct 09 07:13:15 AM UTC 24 | Oct 09 07:13:16 AM UTC 24 | 68827392 ps | ||
| T557 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.3821198536 | Oct 09 07:13:14 AM UTC 24 | Oct 09 07:13:16 AM UTC 24 | 41792093 ps | ||
| T558 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1020233388 | Oct 09 07:13:13 AM UTC 24 | Oct 09 07:13:17 AM UTC 24 | 232006643 ps | ||
| T559 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.872085359 | Oct 09 07:13:14 AM UTC 24 | Oct 09 07:13:17 AM UTC 24 | 56621591 ps | ||
| T560 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.1496552980 | Oct 09 07:13:16 AM UTC 24 | Oct 09 07:13:18 AM UTC 24 | 14308961 ps | ||
| T561 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.942071716 | Oct 09 07:13:13 AM UTC 24 | Oct 09 07:13:18 AM UTC 24 | 353483301 ps | ||
| T562 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.4069280675 | Oct 09 07:13:14 AM UTC 24 | Oct 09 07:13:18 AM UTC 24 | 155978112 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.389803663 | Oct 09 07:13:13 AM UTC 24 | Oct 09 07:13:18 AM UTC 24 | 502071538 ps | ||
| T563 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.3726355544 | Oct 09 07:13:12 AM UTC 24 | Oct 09 07:13:18 AM UTC 24 | 915746978 ps | ||
| T564 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.500926611 | Oct 09 07:13:16 AM UTC 24 | Oct 09 07:13:19 AM UTC 24 | 293412809 ps | ||
| T565 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.3586635242 | Oct 09 07:13:17 AM UTC 24 | Oct 09 07:13:20 AM UTC 24 | 63396088 ps | ||
| T566 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.3076551609 | Oct 09 07:13:18 AM UTC 24 | Oct 09 07:13:20 AM UTC 24 | 16591390 ps | ||
| T567 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.1728445587 | Oct 09 07:13:18 AM UTC 24 | Oct 09 07:13:20 AM UTC 24 | 157023944 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.2178617337 | Oct 09 07:13:14 AM UTC 24 | Oct 09 07:13:21 AM UTC 24 | 126269475 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.3206083505 | Oct 09 07:13:18 AM UTC 24 | Oct 09 07:13:21 AM UTC 24 | 177413087 ps | ||
| T568 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.3285038479 | Oct 09 07:13:19 AM UTC 24 | Oct 09 07:13:21 AM UTC 24 | 11402117 ps | ||
| T569 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.859619246 | Oct 09 07:13:17 AM UTC 24 | Oct 09 07:13:21 AM UTC 24 | 82837658 ps | ||
| T570 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.406835212 | Oct 09 07:13:19 AM UTC 24 | Oct 09 07:13:22 AM UTC 24 | 104519986 ps | ||
| T571 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.12558511 | Oct 09 07:13:19 AM UTC 24 | Oct 09 07:13:22 AM UTC 24 | 41579113 ps | ||
| T572 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.2124332738 | Oct 09 07:13:19 AM UTC 24 | Oct 09 07:13:23 AM UTC 24 | 482566633 ps | ||
| T573 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.3805543526 | Oct 09 07:13:19 AM UTC 24 | Oct 09 07:13:23 AM UTC 24 | 49162661 ps | ||
| T574 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.4254237267 | Oct 09 07:13:20 AM UTC 24 | Oct 09 07:13:23 AM UTC 24 | 57491539 ps | ||
| T575 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.1692302017 | Oct 09 07:13:22 AM UTC 24 | Oct 09 07:13:24 AM UTC 24 | 15063016 ps | ||
| T576 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.1492444306 | Oct 09 07:13:22 AM UTC 24 | Oct 09 07:13:24 AM UTC 24 | 22961638 ps | ||
| T577 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2905995865 | Oct 09 07:13:21 AM UTC 24 | Oct 09 07:13:24 AM UTC 24 | 253000443 ps | ||
| T578 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3261976480 | Oct 09 07:13:20 AM UTC 24 | Oct 09 07:13:25 AM UTC 24 | 1447387433 ps | ||
| T579 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.811082124 | Oct 09 07:13:22 AM UTC 24 | Oct 09 07:13:25 AM UTC 24 | 35658058 ps | ||
| T580 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.4092505616 | Oct 09 07:13:23 AM UTC 24 | Oct 09 07:13:25 AM UTC 24 | 16475069 ps | ||
| T581 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.2824844196 | Oct 09 07:13:23 AM UTC 24 | Oct 09 07:13:25 AM UTC 24 | 59236283 ps | ||
| T582 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.2926329602 | Oct 09 07:13:23 AM UTC 24 | Oct 09 07:13:26 AM UTC 24 | 219802191 ps | ||
| T583 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.1460774546 | Oct 09 07:13:25 AM UTC 24 | Oct 09 07:13:27 AM UTC 24 | 12973638 ps | ||
| T584 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.1830913350 | Oct 09 07:13:25 AM UTC 24 | Oct 09 07:13:27 AM UTC 24 | 16181172 ps | ||
| T585 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3637717526 | Oct 09 07:13:23 AM UTC 24 | Oct 09 07:13:27 AM UTC 24 | 178526729 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.174594071 | Oct 09 07:13:22 AM UTC 24 | Oct 09 07:13:27 AM UTC 24 | 163281266 ps | ||
| T586 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.222861295 | Oct 09 07:13:22 AM UTC 24 | Oct 09 07:13:27 AM UTC 24 | 252174692 ps | ||
| T587 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.705113299 | Oct 09 07:13:23 AM UTC 24 | Oct 09 07:13:28 AM UTC 24 | 563721572 ps | ||
| T588 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.2674197368 | Oct 09 07:13:26 AM UTC 24 | Oct 09 07:13:28 AM UTC 24 | 37188755 ps | ||
| T589 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.1228962261 | Oct 09 07:13:22 AM UTC 24 | Oct 09 07:13:28 AM UTC 24 | 244680169 ps | ||
| T590 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2359883208 | Oct 09 07:13:26 AM UTC 24 | Oct 09 07:13:28 AM UTC 24 | 263724385 ps | ||
| T591 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1495464677 | Oct 09 07:13:26 AM UTC 24 | Oct 09 07:13:28 AM UTC 24 | 50866462 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.1365700509 | Oct 09 07:13:22 AM UTC 24 | Oct 09 07:13:29 AM UTC 24 | 544214670 ps | ||
| T592 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.1586926893 | Oct 09 07:13:27 AM UTC 24 | Oct 09 07:13:29 AM UTC 24 | 31276505 ps | ||
| T593 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.2873018984 | Oct 09 07:13:27 AM UTC 24 | Oct 09 07:13:29 AM UTC 24 | 36590637 ps | ||
| T594 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1773833998 | Oct 09 07:13:27 AM UTC 24 | Oct 09 07:13:30 AM UTC 24 | 78594162 ps | ||
| T595 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.891370080 | Oct 09 07:13:26 AM UTC 24 | Oct 09 07:13:30 AM UTC 24 | 91155405 ps | ||
| T596 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1540201226 | Oct 09 07:13:27 AM UTC 24 | Oct 09 07:13:30 AM UTC 24 | 310256789 ps | ||
| T597 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.379333038 | Oct 09 07:13:23 AM UTC 24 | Oct 09 07:13:30 AM UTC 24 | 1440676313 ps | ||
| T598 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.242192801 | Oct 09 07:13:28 AM UTC 24 | Oct 09 07:13:30 AM UTC 24 | 34367962 ps | ||
| T599 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.562960773 | Oct 09 07:13:27 AM UTC 24 | Oct 09 07:13:31 AM UTC 24 | 80445620 ps | ||
| T600 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1835215964 | Oct 09 07:13:28 AM UTC 24 | Oct 09 07:13:31 AM UTC 24 | 303457657 ps | ||
| T601 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.2857081290 | Oct 09 07:13:30 AM UTC 24 | Oct 09 07:13:32 AM UTC 24 | 48159971 ps | ||
| T602 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.3955239178 | Oct 09 07:13:30 AM UTC 24 | Oct 09 07:13:32 AM UTC 24 | 78632367 ps | ||
| T603 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2671287885 | Oct 09 07:13:30 AM UTC 24 | Oct 09 07:13:32 AM UTC 24 | 69611735 ps | ||
| T604 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.1963154684 | Oct 09 07:13:31 AM UTC 24 | Oct 09 07:13:33 AM UTC 24 | 38888858 ps | ||
| T605 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.2743054010 | Oct 09 07:13:27 AM UTC 24 | Oct 09 07:13:33 AM UTC 24 | 207119808 ps | ||
| T606 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.365130607 | Oct 09 07:13:31 AM UTC 24 | Oct 09 07:13:33 AM UTC 24 | 146987521 ps | ||
| T607 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.1839689774 | Oct 09 07:13:26 AM UTC 24 | Oct 09 07:13:33 AM UTC 24 | 460692130 ps | ||
| T608 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.673004561 | Oct 09 07:13:29 AM UTC 24 | Oct 09 07:13:33 AM UTC 24 | 81429681 ps | ||
| T609 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3944393912 | Oct 09 07:13:28 AM UTC 24 | Oct 09 07:13:33 AM UTC 24 | 54140707 ps | ||
| T610 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.1246334486 | Oct 09 07:13:31 AM UTC 24 | Oct 09 07:13:34 AM UTC 24 | 349722775 ps | ||
| T611 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.4010595962 | Oct 09 07:13:32 AM UTC 24 | Oct 09 07:13:34 AM UTC 24 | 13923680 ps | ||
| T612 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.322874932 | Oct 09 07:13:32 AM UTC 24 | Oct 09 07:13:35 AM UTC 24 | 20552692 ps | ||
| T613 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.933508166 | Oct 09 07:13:31 AM UTC 24 | Oct 09 07:13:35 AM UTC 24 | 170954116 ps | ||
| T614 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.856621380 | Oct 09 07:13:32 AM UTC 24 | Oct 09 07:13:35 AM UTC 24 | 78376145 ps | ||
| T615 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.3168810187 | Oct 09 07:13:29 AM UTC 24 | Oct 09 07:13:35 AM UTC 24 | 768834217 ps | ||
| T616 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.4183590546 | Oct 09 07:13:33 AM UTC 24 | Oct 09 07:13:35 AM UTC 24 | 41885862 ps | ||
| T617 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.1129805995 | Oct 09 07:13:34 AM UTC 24 | Oct 09 07:13:35 AM UTC 24 | 43015509 ps | ||
| T618 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2329069634 | Oct 09 07:13:32 AM UTC 24 | Oct 09 07:13:35 AM UTC 24 | 30630927 ps | ||
| T619 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.316316186 | Oct 09 07:13:33 AM UTC 24 | Oct 09 07:13:36 AM UTC 24 | 172381546 ps | ||
| T620 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.3882220893 | Oct 09 07:13:32 AM UTC 24 | Oct 09 07:13:36 AM UTC 24 | 84518413 ps | ||
| T621 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1990066283 | Oct 09 07:13:33 AM UTC 24 | Oct 09 07:13:36 AM UTC 24 | 82405272 ps | ||
| T622 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.4037385837 | Oct 09 07:13:35 AM UTC 24 | Oct 09 07:13:36 AM UTC 24 | 20358650 ps | ||
| T623 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.1903223737 | Oct 09 07:13:35 AM UTC 24 | Oct 09 07:13:36 AM UTC 24 | 54020246 ps | ||
| T624 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.554778357 | Oct 09 07:13:35 AM UTC 24 | Oct 09 07:13:37 AM UTC 24 | 57333225 ps | ||
| T625 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.2499485383 | Oct 09 07:13:35 AM UTC 24 | Oct 09 07:13:37 AM UTC 24 | 23613549 ps | ||
| T626 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.1831969798 | Oct 09 07:13:35 AM UTC 24 | Oct 09 07:13:37 AM UTC 24 | 13331299 ps | ||
| T627 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.3433891258 | Oct 09 07:13:35 AM UTC 24 | Oct 09 07:13:37 AM UTC 24 | 31105520 ps | ||
| T628 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.286665562 | Oct 09 07:13:32 AM UTC 24 | Oct 09 07:13:37 AM UTC 24 | 1748145298 ps | ||
| T629 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.1990680465 | Oct 09 07:13:36 AM UTC 24 | Oct 09 07:13:38 AM UTC 24 | 32986348 ps | ||
| T630 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.210139935 | Oct 09 07:13:36 AM UTC 24 | Oct 09 07:13:38 AM UTC 24 | 25479621 ps | ||
| T631 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.4143854654 | Oct 09 07:13:36 AM UTC 24 | Oct 09 07:13:38 AM UTC 24 | 19487021 ps | ||
| T632 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.3937541476 | Oct 09 07:13:36 AM UTC 24 | Oct 09 07:13:38 AM UTC 24 | 49824159 ps | ||
| T633 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.3668281879 | Oct 09 07:13:36 AM UTC 24 | Oct 09 07:13:38 AM UTC 24 | 45582632 ps | ||
| T634 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.1506768912 | Oct 09 07:13:36 AM UTC 24 | Oct 09 07:13:38 AM UTC 24 | 13984231 ps | ||
| T635 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.3545550901 | Oct 09 07:13:36 AM UTC 24 | Oct 09 07:13:38 AM UTC 24 | 16575267 ps | ||
| T636 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.976525793 | Oct 09 07:13:36 AM UTC 24 | Oct 09 07:13:38 AM UTC 24 | 33785646 ps | ||
| T637 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.4225540348 | Oct 09 07:13:36 AM UTC 24 | Oct 09 07:13:38 AM UTC 24 | 21769240 ps | ||
| T638 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.2361170247 | Oct 09 07:13:38 AM UTC 24 | Oct 09 07:13:39 AM UTC 24 | 116546957 ps | ||
| T639 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.2740592720 | Oct 09 07:13:37 AM UTC 24 | Oct 09 07:13:39 AM UTC 24 | 31775969 ps | ||
| T640 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.438786163 | Oct 09 07:13:38 AM UTC 24 | Oct 09 07:13:39 AM UTC 24 | 19140613 ps | ||
| T641 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.4040971278 | Oct 09 07:13:38 AM UTC 24 | Oct 09 07:13:39 AM UTC 24 | 40893902 ps | ||
| T642 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.4157390829 | Oct 09 07:13:38 AM UTC 24 | Oct 09 07:13:40 AM UTC 24 | 32773845 ps | ||
| T643 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.2453671574 | Oct 09 07:13:38 AM UTC 24 | Oct 09 07:13:40 AM UTC 24 | 35472344 ps | ||
| T644 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.594014976 | Oct 09 07:13:38 AM UTC 24 | Oct 09 07:13:40 AM UTC 24 | 44609923 ps | ||
| T645 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.1280087946 | Oct 09 07:13:38 AM UTC 24 | Oct 09 07:13:40 AM UTC 24 | 15611461 ps | ||
| T646 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.1735820784 | Oct 09 07:13:38 AM UTC 24 | Oct 09 07:13:40 AM UTC 24 | 12102668 ps | ||
| T647 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.3130371422 | Oct 09 07:13:38 AM UTC 24 | Oct 09 07:13:40 AM UTC 24 | 48049416 ps | ||
| T648 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.2672935971 | Oct 09 07:13:39 AM UTC 24 | Oct 09 07:13:41 AM UTC 24 | 19806138 ps | ||
| T649 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.2177245994 | Oct 09 07:13:39 AM UTC 24 | Oct 09 07:13:41 AM UTC 24 | 14291591 ps | ||
| T650 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.2980056160 | Oct 09 07:13:39 AM UTC 24 | Oct 09 07:13:41 AM UTC 24 | 11572549 ps | ||
| T651 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1856640018 | Oct 09 07:13:22 AM UTC 24 | Oct 09 07:16:01 AM UTC 24 | 74904065739 ps | ||
| T652 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1960217763 | Oct 09 07:13:31 AM UTC 24 | Oct 09 07:23:59 AM UTC 24 | 447441774657 ps | ||
| T653 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.454153938 | Oct 09 07:13:13 AM UTC 24 | Oct 09 07:27:40 AM UTC 24 | 186770384091 ps | ||
| T654 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.632570766 | Oct 09 07:13:03 AM UTC 24 | Oct 09 07:30:28 AM UTC 24 | 141428151547 ps | ||
| T655 | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3120315379 | Oct 09 07:12:59 AM UTC 24 | Oct 09 07:30:43 AM UTC 24 | 429628998946 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/0.hmac_burst_wr.411895193 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1236051522 ps |
| CPU time | 31.82 seconds |
| Started | Oct 09 07:38:05 AM UTC 24 |
| Finished | Oct 09 07:38:38 AM UTC 24 |
| Peak memory | 210304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411895193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.411895193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/1.hmac_burst_wr.967198050 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 43688185111 ps |
| CPU time | 61.57 seconds |
| Started | Oct 09 07:38:15 AM UTC 24 |
| Finished | Oct 09 07:39:18 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967198050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.967198050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/3.hmac_stress_all_with_rand_reset.1031476101 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 25870054027 ps |
| CPU time | 461.45 seconds |
| Started | Oct 09 07:39:19 AM UTC 24 |
| Finished | Oct 09 07:47:07 AM UTC 24 |
| Peak memory | 382300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10314761 01 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.1031476101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/3.hmac_wipe_secret.3419074887 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1634234338 ps |
| CPU time | 93.51 seconds |
| Started | Oct 09 07:39:07 AM UTC 24 |
| Finished | Oct 09 07:40:42 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419074887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3419074887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.3686778160 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 164145887 ps |
| CPU time | 5.31 seconds |
| Started | Oct 09 07:12:55 AM UTC 24 |
| Finished | Oct 09 07:13:02 AM UTC 24 |
| Peak memory | 206896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686778160 -assert nopostproc +UVM_TESTNAM E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3686778160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/1.hmac_sec_cm.2351829469 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 64088494 ps |
| CPU time | 1.46 seconds |
| Started | Oct 09 07:38:32 AM UTC 24 |
| Finished | Oct 09 07:38:35 AM UTC 24 |
| Peak memory | 239584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351829469 -assert nopostproc +UVM_TESTNAME=hmac_b ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hm ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2351829469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/4.hmac_smoke.1147721832 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4849442862 ps |
| CPU time | 15.89 seconds |
| Started | Oct 09 07:39:26 AM UTC 24 |
| Finished | Oct 09 07:39:43 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147721832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1147721832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/8.hmac_back_pressure.219990859 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1780417606 ps |
| CPU time | 106.69 seconds |
| Started | Oct 09 07:41:03 AM UTC 24 |
| Finished | Oct 09 07:42:52 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219990859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.219990859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/8.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/0.hmac_stress_all.1795173321 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 9957596562 ps |
| CPU time | 175.71 seconds |
| Started | Oct 09 07:38:08 AM UTC 24 |
| Finished | Oct 09 07:41:07 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795173321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1795173321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_rw.3731953420 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 15646345 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 07:12:50 AM UTC 24 |
| Finished | Oct 09 07:12:53 AM UTC 24 |
| Peak memory | 206080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731953420 -assert nopostproc +UVM_TESTNAME=hmac_ba se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3731953420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/6.hmac_burst_wr.2764486665 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 20572898462 ps |
| CPU time | 62.09 seconds |
| Started | Oct 09 07:40:34 AM UTC 24 |
| Finished | Oct 09 07:41:38 AM UTC 24 |
| Peak memory | 210640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764486665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2764486665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/6.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/13.hmac_burst_wr.1449875239 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1163707154 ps |
| CPU time | 47.18 seconds |
| Started | Oct 09 07:42:45 AM UTC 24 |
| Finished | Oct 09 07:43:34 AM UTC 24 |
| Peak memory | 210300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449875239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1449875239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/13.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/5.hmac_stress_all_with_rand_reset.2880994925 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11430660670 ps |
| CPU time | 129.28 seconds |
| Started | Oct 09 07:40:22 AM UTC 24 |
| Finished | Oct 09 07:42:34 AM UTC 24 |
| Peak memory | 269564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28809949 25 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.2880994925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/9.hmac_smoke.4178985684 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1060717100 ps |
| CPU time | 13.59 seconds |
| Started | Oct 09 07:41:21 AM UTC 24 |
| Finished | Oct 09 07:41:35 AM UTC 24 |
| Peak memory | 210340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178985684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.4178985684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/9.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/2.hmac_burst_wr.3574054156 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 850963282 ps |
| CPU time | 49.9 seconds |
| Started | Oct 09 07:38:38 AM UTC 24 |
| Finished | Oct 09 07:39:29 AM UTC 24 |
| Peak memory | 210604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574054156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3574054156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/0.hmac_alert_test.3881970615 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 12025811 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 07:38:10 AM UTC 24 |
| Finished | Oct 09 07:38:12 AM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881970615 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3881970615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/9.hmac_datapath_stress.442602669 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 397001300 ps |
| CPU time | 5.75 seconds |
| Started | Oct 09 07:41:26 AM UTC 24 |
| Finished | Oct 09 07:41:33 AM UTC 24 |
| Peak memory | 210244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442602669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.442602669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/9.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/20.hmac_burst_wr.2285503907 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1515838825 ps |
| CPU time | 27.34 seconds |
| Started | Oct 09 07:46:24 AM UTC 24 |
| Finished | Oct 09 07:46:53 AM UTC 24 |
| Peak memory | 210320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285503907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2285503907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/20.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.389803663 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 502071538 ps |
| CPU time | 3.95 seconds |
| Started | Oct 09 07:13:13 AM UTC 24 |
| Finished | Oct 09 07:13:18 AM UTC 24 |
| Peak memory | 207096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389803663 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.389803663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/8.hmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/13.hmac_smoke.1093374842 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4790339248 ps |
| CPU time | 13.92 seconds |
| Started | Oct 09 07:42:38 AM UTC 24 |
| Finished | Oct 09 07:42:53 AM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093374842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1093374842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/13.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/15.hmac_smoke.215458313 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1153473068 ps |
| CPU time | 15.55 seconds |
| Started | Oct 09 07:43:17 AM UTC 24 |
| Finished | Oct 09 07:43:34 AM UTC 24 |
| Peak memory | 210328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215458313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 15.hmac_smoke.215458313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/15.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.174594071 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 163281266 ps |
| CPU time | 3.99 seconds |
| Started | Oct 09 07:13:22 AM UTC 24 |
| Finished | Oct 09 07:13:27 AM UTC 24 |
| Peak memory | 206868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174594071 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.174594071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/12.hmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/0.hmac_error.1897619008 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 10000913854 ps |
| CPU time | 24.25 seconds |
| Started | Oct 09 07:38:05 AM UTC 24 |
| Finished | Oct 09 07:38:31 AM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897619008 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1897619008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/0.hmac_test_sha256_vectors.591703586 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 232469314669 ps |
| CPU time | 664.06 seconds |
| Started | Oct 09 07:38:06 AM UTC 24 |
| Finished | Oct 09 07:49:19 AM UTC 24 |
| Peak memory | 210360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591703586 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.591703586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_test_sha256_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/1.hmac_error.3036196334 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 5557780518 ps |
| CPU time | 76.08 seconds |
| Started | Oct 09 07:38:15 AM UTC 24 |
| Finished | Oct 09 07:39:33 AM UTC 24 |
| Peak memory | 210420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036196334 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3036196334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.1365700509 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 544214670 ps |
| CPU time | 5.53 seconds |
| Started | Oct 09 07:13:22 AM UTC 24 |
| Finished | Oct 09 07:13:29 AM UTC 24 |
| Peak memory | 207140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365700509 -assert nopostproc +UVM_TESTNAM E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1365700509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/13.hmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.2582667403 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 116674504 ps |
| CPU time | 4.14 seconds |
| Started | Oct 09 07:12:51 AM UTC 24 |
| Finished | Oct 09 07:12:57 AM UTC 24 |
| Peak memory | 207140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582667403 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2582667403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.83750148 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 2939746350 ps |
| CPU time | 14.55 seconds |
| Started | Oct 09 07:12:50 AM UTC 24 |
| Finished | Oct 09 07:13:06 AM UTC 24 |
| Peak memory | 206892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83750148 -assert nopostproc +UVM_TESTNAME=hma c_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.83750148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_hw_reset.2166341028 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 40971896 ps |
| CPU time | 1.37 seconds |
| Started | Oct 09 07:12:50 AM UTC 24 |
| Finished | Oct 09 07:12:53 AM UTC 24 |
| Peak memory | 206552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166341028 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2166341028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2133519390 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 81802171 ps |
| CPU time | 3.68 seconds |
| Started | Oct 09 07:12:53 AM UTC 24 |
| Finished | Oct 09 07:12:57 AM UTC 24 |
| Peak memory | 206864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2133519390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_r eset.2133519390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_intr_test.345013869 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 15190598 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 07:12:49 AM UTC 24 |
| Finished | Oct 09 07:12:51 AM UTC 24 |
| Peak memory | 204064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345013869 -assert nopostproc +UVM_TESTNAME=hmac_base_t est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.345013869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_same_csr_outstanding.616653353 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 76602115 ps |
| CPU time | 2.37 seconds |
| Started | Oct 09 07:12:51 AM UTC 24 |
| Finished | Oct 09 07:12:55 AM UTC 24 |
| Peak memory | 206812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616653353 -assert nopostproc +UVM _TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_outstanding.616653353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_errors.3226569614 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 53298127 ps |
| CPU time | 1.94 seconds |
| Started | Oct 09 07:12:49 AM UTC 24 |
| Finished | Oct 09 07:12:52 AM UTC 24 |
| Peak memory | 206092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226569614 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.3226569614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_intg_err.669185091 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 173201538 ps |
| CPU time | 2.35 seconds |
| Started | Oct 09 07:12:49 AM UTC 24 |
| Finished | Oct 09 07:12:53 AM UTC 24 |
| Peak memory | 206812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669185091 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.669185091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.1393337869 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 1147312717 ps |
| CPU time | 7.88 seconds |
| Started | Oct 09 07:12:54 AM UTC 24 |
| Finished | Oct 09 07:13:03 AM UTC 24 |
| Peak memory | 206812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393337869 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1393337869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.2346012821 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 530425881 ps |
| CPU time | 8.41 seconds |
| Started | Oct 09 07:12:54 AM UTC 24 |
| Finished | Oct 09 07:13:03 AM UTC 24 |
| Peak memory | 206812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346012821 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2346012821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.87841925 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 60680987 ps |
| CPU time | 1.06 seconds |
| Started | Oct 09 07:12:53 AM UTC 24 |
| Finished | Oct 09 07:12:55 AM UTC 24 |
| Peak memory | 205344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87841925 -assert nopostproc +UVM_TESTNAME=hma c_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.87841925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1447459059 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 109148968 ps |
| CPU time | 2.55 seconds |
| Started | Oct 09 07:12:54 AM UTC 24 |
| Finished | Oct 09 07:12:58 AM UTC 24 |
| Peak memory | 215404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1447459059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_r eset.1447459059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.2095663611 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 27798604 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 07:12:54 AM UTC 24 |
| Finished | Oct 09 07:12:56 AM UTC 24 |
| Peak memory | 206080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095663611 -assert nopostproc +UVM_TESTNAME=hmac_ba se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2095663611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_intr_test.2398652379 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 29593513 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 07:12:53 AM UTC 24 |
| Finished | Oct 09 07:12:55 AM UTC 24 |
| Peak memory | 203140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398652379 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2398652379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3505603974 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 86328006 ps |
| CPU time | 2.06 seconds |
| Started | Oct 09 07:12:54 AM UTC 24 |
| Finished | Oct 09 07:12:57 AM UTC 24 |
| Peak memory | 206812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505603974 -assert nopostproc +UV M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_outstanding.3505603974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.3684213116 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 358049992 ps |
| CPU time | 2.95 seconds |
| Started | Oct 09 07:12:53 AM UTC 24 |
| Finished | Oct 09 07:12:57 AM UTC 24 |
| Peak memory | 207004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684213116 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3684213116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.2982852068 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 283632697 ps |
| CPU time | 5.29 seconds |
| Started | Oct 09 07:12:53 AM UTC 24 |
| Finished | Oct 09 07:12:59 AM UTC 24 |
| Peak memory | 206804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982852068 -assert nopostproc +UVM_TESTNAM E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2982852068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.12558511 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 41579113 ps |
| CPU time | 1.75 seconds |
| Started | Oct 09 07:13:19 AM UTC 24 |
| Finished | Oct 09 07:13:22 AM UTC 24 |
| Peak memory | 206140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=12558511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.12558511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/10.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.1728445587 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 157023944 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 07:13:18 AM UTC 24 |
| Finished | Oct 09 07:13:20 AM UTC 24 |
| Peak memory | 206196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728445587 -assert nopostproc +UVM_TESTNAME=hmac_ba se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1728445587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/10.hmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.3076551609 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 16591390 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 07:13:18 AM UTC 24 |
| Finished | Oct 09 07:13:20 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076551609 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3076551609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/10.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.406835212 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 104519986 ps |
| CPU time | 1.38 seconds |
| Started | Oct 09 07:13:19 AM UTC 24 |
| Finished | Oct 09 07:13:22 AM UTC 24 |
| Peak memory | 206084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406835212 -assert nopostproc +UVM _TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr_outstanding.406835212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/10.hmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.3586635242 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 63396088 ps |
| CPU time | 1.77 seconds |
| Started | Oct 09 07:13:17 AM UTC 24 |
| Finished | Oct 09 07:13:20 AM UTC 24 |
| Peak memory | 206072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586635242 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3586635242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/10.hmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.3206083505 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 177413087 ps |
| CPU time | 2.3 seconds |
| Started | Oct 09 07:13:18 AM UTC 24 |
| Finished | Oct 09 07:13:21 AM UTC 24 |
| Peak memory | 207068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206083505 -assert nopostproc +UVM_TESTNAM E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3206083505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/10.hmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2905995865 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 253000443 ps |
| CPU time | 2.65 seconds |
| Started | Oct 09 07:13:21 AM UTC 24 |
| Finished | Oct 09 07:13:24 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2905995865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_ reset.2905995865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/11.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.4254237267 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 57491539 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 07:13:20 AM UTC 24 |
| Finished | Oct 09 07:13:23 AM UTC 24 |
| Peak memory | 206084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254237267 -assert nopostproc +UVM_TESTNAME=hmac_ba se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.4254237267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/11.hmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.3285038479 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 11402117 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 07:13:19 AM UTC 24 |
| Finished | Oct 09 07:13:21 AM UTC 24 |
| Peak memory | 203020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285038479 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3285038479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/11.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3261976480 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 1447387433 ps |
| CPU time | 3 seconds |
| Started | Oct 09 07:13:20 AM UTC 24 |
| Finished | Oct 09 07:13:25 AM UTC 24 |
| Peak memory | 206804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261976480 -assert nopostproc +UV M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr_outstanding.3261976480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/11.hmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.2124332738 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 482566633 ps |
| CPU time | 2.32 seconds |
| Started | Oct 09 07:13:19 AM UTC 24 |
| Finished | Oct 09 07:13:23 AM UTC 24 |
| Peak memory | 207208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124332738 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2124332738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/11.hmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.3805543526 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 49162661 ps |
| CPU time | 2.31 seconds |
| Started | Oct 09 07:13:19 AM UTC 24 |
| Finished | Oct 09 07:13:23 AM UTC 24 |
| Peak memory | 206892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805543526 -assert nopostproc +UVM_TESTNAM E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3805543526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/11.hmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1856640018 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 74904065739 ps |
| CPU time | 155.74 seconds |
| Started | Oct 09 07:13:22 AM UTC 24 |
| Finished | Oct 09 07:16:01 AM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1856640018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_ reset.1856640018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/12.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.1492444306 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 22961638 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 07:13:22 AM UTC 24 |
| Finished | Oct 09 07:13:24 AM UTC 24 |
| Peak memory | 206084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492444306 -assert nopostproc +UVM_TESTNAME=hmac_ba se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1492444306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/12.hmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.1692302017 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 15063016 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 07:13:22 AM UTC 24 |
| Finished | Oct 09 07:13:24 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692302017 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1692302017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/12.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.811082124 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 35658058 ps |
| CPU time | 1.81 seconds |
| Started | Oct 09 07:13:22 AM UTC 24 |
| Finished | Oct 09 07:13:25 AM UTC 24 |
| Peak memory | 206092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811082124 -assert nopostproc +UVM _TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr_outstanding.811082124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/12.hmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.222861295 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 252174692 ps |
| CPU time | 4.7 seconds |
| Started | Oct 09 07:13:22 AM UTC 24 |
| Finished | Oct 09 07:13:27 AM UTC 24 |
| Peak memory | 206944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222861295 -assert nopostproc +UVM_TESTNAME=hmac_base_t est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.222861295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/12.hmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3637717526 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 178526729 ps |
| CPU time | 2.26 seconds |
| Started | Oct 09 07:13:23 AM UTC 24 |
| Finished | Oct 09 07:13:27 AM UTC 24 |
| Peak memory | 206936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3637717526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_ reset.3637717526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/13.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.2824844196 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 59236283 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 07:13:23 AM UTC 24 |
| Finished | Oct 09 07:13:25 AM UTC 24 |
| Peak memory | 206080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824844196 -assert nopostproc +UVM_TESTNAME=hmac_ba se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2824844196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/13.hmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.4092505616 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 16475069 ps |
| CPU time | 0.8 seconds |
| Started | Oct 09 07:13:23 AM UTC 24 |
| Finished | Oct 09 07:13:25 AM UTC 24 |
| Peak memory | 202940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092505616 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.4092505616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/13.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.705113299 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 563721572 ps |
| CPU time | 3.53 seconds |
| Started | Oct 09 07:13:23 AM UTC 24 |
| Finished | Oct 09 07:13:28 AM UTC 24 |
| Peak memory | 206824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705113299 -assert nopostproc +UVM _TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_outstanding.705113299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/13.hmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.1228962261 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 244680169 ps |
| CPU time | 5 seconds |
| Started | Oct 09 07:13:22 AM UTC 24 |
| Finished | Oct 09 07:13:28 AM UTC 24 |
| Peak memory | 206868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228962261 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1228962261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/13.hmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2359883208 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 263724385 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 07:13:26 AM UTC 24 |
| Finished | Oct 09 07:13:28 AM UTC 24 |
| Peak memory | 206144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2359883208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_ reset.2359883208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/14.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.1830913350 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 16181172 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 07:13:25 AM UTC 24 |
| Finished | Oct 09 07:13:27 AM UTC 24 |
| Peak memory | 206732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830913350 -assert nopostproc +UVM_TESTNAME=hmac_ba se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1830913350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/14.hmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.1460774546 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 12973638 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 07:13:25 AM UTC 24 |
| Finished | Oct 09 07:13:27 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460774546 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1460774546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/14.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1495464677 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 50866462 ps |
| CPU time | 1.59 seconds |
| Started | Oct 09 07:13:26 AM UTC 24 |
| Finished | Oct 09 07:13:28 AM UTC 24 |
| Peak memory | 206032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495464677 -assert nopostproc +UV M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr_outstanding.1495464677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/14.hmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.2926329602 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 219802191 ps |
| CPU time | 1.56 seconds |
| Started | Oct 09 07:13:23 AM UTC 24 |
| Finished | Oct 09 07:13:26 AM UTC 24 |
| Peak memory | 206024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926329602 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2926329602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/14.hmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.379333038 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 1440676313 ps |
| CPU time | 5.83 seconds |
| Started | Oct 09 07:13:23 AM UTC 24 |
| Finished | Oct 09 07:13:30 AM UTC 24 |
| Peak memory | 206952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379333038 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.379333038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/14.hmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1773833998 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 78594162 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 07:13:27 AM UTC 24 |
| Finished | Oct 09 07:13:30 AM UTC 24 |
| Peak memory | 206144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1773833998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_ reset.1773833998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/15.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.1586926893 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 31276505 ps |
| CPU time | 1 seconds |
| Started | Oct 09 07:13:27 AM UTC 24 |
| Finished | Oct 09 07:13:29 AM UTC 24 |
| Peak memory | 206136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586926893 -assert nopostproc +UVM_TESTNAME=hmac_ba se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1586926893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/15.hmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.2674197368 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 37188755 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 07:13:26 AM UTC 24 |
| Finished | Oct 09 07:13:28 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674197368 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2674197368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/15.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1540201226 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 310256789 ps |
| CPU time | 2.1 seconds |
| Started | Oct 09 07:13:27 AM UTC 24 |
| Finished | Oct 09 07:13:30 AM UTC 24 |
| Peak memory | 207076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540201226 -assert nopostproc +UV M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr_outstanding.1540201226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/15.hmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.1839689774 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 460692130 ps |
| CPU time | 6.11 seconds |
| Started | Oct 09 07:13:26 AM UTC 24 |
| Finished | Oct 09 07:13:33 AM UTC 24 |
| Peak memory | 206948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839689774 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1839689774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/15.hmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.891370080 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 91155405 ps |
| CPU time | 2.97 seconds |
| Started | Oct 09 07:13:26 AM UTC 24 |
| Finished | Oct 09 07:13:30 AM UTC 24 |
| Peak memory | 206876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891370080 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.891370080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/15.hmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3944393912 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 54140707 ps |
| CPU time | 3.87 seconds |
| Started | Oct 09 07:13:28 AM UTC 24 |
| Finished | Oct 09 07:13:33 AM UTC 24 |
| Peak memory | 217112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3944393912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_ reset.3944393912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/16.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.242192801 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 34367962 ps |
| CPU time | 1 seconds |
| Started | Oct 09 07:13:28 AM UTC 24 |
| Finished | Oct 09 07:13:30 AM UTC 24 |
| Peak memory | 206252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242192801 -assert nopostproc +UVM_TESTNAME=hmac_bas e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.242192801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/16.hmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.2873018984 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 36590637 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 07:13:27 AM UTC 24 |
| Finished | Oct 09 07:13:29 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873018984 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2873018984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/16.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1835215964 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 303457657 ps |
| CPU time | 1.89 seconds |
| Started | Oct 09 07:13:28 AM UTC 24 |
| Finished | Oct 09 07:13:31 AM UTC 24 |
| Peak memory | 206204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835215964 -assert nopostproc +UV M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr_outstanding.1835215964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/16.hmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.2743054010 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 207119808 ps |
| CPU time | 4.53 seconds |
| Started | Oct 09 07:13:27 AM UTC 24 |
| Finished | Oct 09 07:13:33 AM UTC 24 |
| Peak memory | 206868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743054010 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2743054010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/16.hmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.562960773 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 80445620 ps |
| CPU time | 2.45 seconds |
| Started | Oct 09 07:13:27 AM UTC 24 |
| Finished | Oct 09 07:13:31 AM UTC 24 |
| Peak memory | 206884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562960773 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.562960773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/16.hmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1960217763 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 447441774657 ps |
| CPU time | 620.92 seconds |
| Started | Oct 09 07:13:31 AM UTC 24 |
| Finished | Oct 09 07:23:59 AM UTC 24 |
| Peak memory | 219292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1960217763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_ reset.1960217763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/17.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.3955239178 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 78632367 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 07:13:30 AM UTC 24 |
| Finished | Oct 09 07:13:32 AM UTC 24 |
| Peak memory | 206492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955239178 -assert nopostproc +UVM_TESTNAME=hmac_ba se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3955239178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/17.hmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.2857081290 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 48159971 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 07:13:30 AM UTC 24 |
| Finished | Oct 09 07:13:32 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857081290 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2857081290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/17.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2671287885 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 69611735 ps |
| CPU time | 1.5 seconds |
| Started | Oct 09 07:13:30 AM UTC 24 |
| Finished | Oct 09 07:13:32 AM UTC 24 |
| Peak memory | 206088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671287885 -assert nopostproc +UV M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr_outstanding.2671287885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/17.hmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.673004561 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 81429681 ps |
| CPU time | 2.49 seconds |
| Started | Oct 09 07:13:29 AM UTC 24 |
| Finished | Oct 09 07:13:33 AM UTC 24 |
| Peak memory | 206896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673004561 -assert nopostproc +UVM_TESTNAME=hmac_base_t est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.673004561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/17.hmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.3168810187 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 768834217 ps |
| CPU time | 4.32 seconds |
| Started | Oct 09 07:13:29 AM UTC 24 |
| Finished | Oct 09 07:13:35 AM UTC 24 |
| Peak memory | 206896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168810187 -assert nopostproc +UVM_TESTNAM E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3168810187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/17.hmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2329069634 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 30630927 ps |
| CPU time | 2.15 seconds |
| Started | Oct 09 07:13:32 AM UTC 24 |
| Finished | Oct 09 07:13:35 AM UTC 24 |
| Peak memory | 207012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2329069634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_ reset.2329069634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/18.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.365130607 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 146987521 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 07:13:31 AM UTC 24 |
| Finished | Oct 09 07:13:33 AM UTC 24 |
| Peak memory | 206288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365130607 -assert nopostproc +UVM_TESTNAME=hmac_bas e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.365130607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/18.hmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.1963154684 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 38888858 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 07:13:31 AM UTC 24 |
| Finished | Oct 09 07:13:33 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963154684 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1963154684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/18.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.856621380 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 78376145 ps |
| CPU time | 1.64 seconds |
| Started | Oct 09 07:13:32 AM UTC 24 |
| Finished | Oct 09 07:13:35 AM UTC 24 |
| Peak memory | 206280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856621380 -assert nopostproc +UVM _TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr_outstanding.856621380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/18.hmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.1246334486 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 349722775 ps |
| CPU time | 2.31 seconds |
| Started | Oct 09 07:13:31 AM UTC 24 |
| Finished | Oct 09 07:13:34 AM UTC 24 |
| Peak memory | 206868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246334486 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1246334486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/18.hmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.933508166 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 170954116 ps |
| CPU time | 2.86 seconds |
| Started | Oct 09 07:13:31 AM UTC 24 |
| Finished | Oct 09 07:13:35 AM UTC 24 |
| Peak memory | 206760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933508166 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.933508166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/18.hmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1990066283 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 82405272 ps |
| CPU time | 1.75 seconds |
| Started | Oct 09 07:13:33 AM UTC 24 |
| Finished | Oct 09 07:13:36 AM UTC 24 |
| Peak memory | 206076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1990066283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_ reset.1990066283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/19.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.322874932 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 20552692 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 07:13:32 AM UTC 24 |
| Finished | Oct 09 07:13:35 AM UTC 24 |
| Peak memory | 205960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322874932 -assert nopostproc +UVM_TESTNAME=hmac_bas e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.322874932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/19.hmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.4010595962 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 13923680 ps |
| CPU time | 0.8 seconds |
| Started | Oct 09 07:13:32 AM UTC 24 |
| Finished | Oct 09 07:13:34 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010595962 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.4010595962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/19.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.316316186 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 172381546 ps |
| CPU time | 1.44 seconds |
| Started | Oct 09 07:13:33 AM UTC 24 |
| Finished | Oct 09 07:13:36 AM UTC 24 |
| Peak memory | 206260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316316186 -assert nopostproc +UVM _TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_outstanding.316316186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/19.hmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.286665562 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 1748145298 ps |
| CPU time | 3.91 seconds |
| Started | Oct 09 07:13:32 AM UTC 24 |
| Finished | Oct 09 07:13:37 AM UTC 24 |
| Peak memory | 206868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286665562 -assert nopostproc +UVM_TESTNAME=hmac_base_t est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.286665562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/19.hmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.3882220893 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 84518413 ps |
| CPU time | 2.71 seconds |
| Started | Oct 09 07:13:32 AM UTC 24 |
| Finished | Oct 09 07:13:36 AM UTC 24 |
| Peak memory | 207200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882220893 -assert nopostproc +UVM_TESTNAM E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3882220893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/19.hmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.1234293761 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 303187905 ps |
| CPU time | 8.92 seconds |
| Started | Oct 09 07:12:59 AM UTC 24 |
| Finished | Oct 09 07:13:08 AM UTC 24 |
| Peak memory | 206812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234293761 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1234293761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.2355040768 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 3269110998 ps |
| CPU time | 22.5 seconds |
| Started | Oct 09 07:12:57 AM UTC 24 |
| Finished | Oct 09 07:13:21 AM UTC 24 |
| Peak memory | 207216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355040768 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2355040768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.1669381404 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 57940154 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 07:12:57 AM UTC 24 |
| Finished | Oct 09 07:13:00 AM UTC 24 |
| Peak memory | 206372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669381404 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1669381404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3120315379 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 429628998946 ps |
| CPU time | 1051.78 seconds |
| Started | Oct 09 07:12:59 AM UTC 24 |
| Finished | Oct 09 07:30:43 AM UTC 24 |
| Peak memory | 237380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3120315379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_r eset.3120315379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.1265408409 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 87377806 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 07:12:57 AM UTC 24 |
| Finished | Oct 09 07:13:00 AM UTC 24 |
| Peak memory | 206080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265408409 -assert nopostproc +UVM_TESTNAME=hmac_ba se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1265408409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.494222811 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 21040265 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 07:12:56 AM UTC 24 |
| Finished | Oct 09 07:12:58 AM UTC 24 |
| Peak memory | 202952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494222811 -assert nopostproc +UVM_TESTNAME=hmac_base_t est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.494222811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2857923627 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 306392453 ps |
| CPU time | 2.42 seconds |
| Started | Oct 09 07:12:59 AM UTC 24 |
| Finished | Oct 09 07:13:02 AM UTC 24 |
| Peak memory | 207068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857923627 -assert nopostproc +UV M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_outstanding.2857923627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.21826149 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 105392740 ps |
| CPU time | 3.62 seconds |
| Started | Oct 09 07:12:55 AM UTC 24 |
| Finished | Oct 09 07:13:00 AM UTC 24 |
| Peak memory | 207192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21826149 -assert nopostproc +UVM_TESTNAME=hmac_base_te st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.21826149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.4183590546 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 41885862 ps |
| CPU time | 0.76 seconds |
| Started | Oct 09 07:13:33 AM UTC 24 |
| Finished | Oct 09 07:13:35 AM UTC 24 |
| Peak memory | 202896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183590546 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.4183590546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/20.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.1129805995 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 43015509 ps |
| CPU time | 0.75 seconds |
| Started | Oct 09 07:13:34 AM UTC 24 |
| Finished | Oct 09 07:13:35 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129805995 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1129805995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/21.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.554778357 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 57333225 ps |
| CPU time | 0.78 seconds |
| Started | Oct 09 07:13:35 AM UTC 24 |
| Finished | Oct 09 07:13:37 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554778357 -assert nopostproc +UVM_TESTNAME=hmac_base_t est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.554778357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/22.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.4037385837 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 20358650 ps |
| CPU time | 0.71 seconds |
| Started | Oct 09 07:13:35 AM UTC 24 |
| Finished | Oct 09 07:13:36 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037385837 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.4037385837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/23.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.1903223737 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 54020246 ps |
| CPU time | 0.75 seconds |
| Started | Oct 09 07:13:35 AM UTC 24 |
| Finished | Oct 09 07:13:36 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903223737 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1903223737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/24.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.1831969798 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 13331299 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 07:13:35 AM UTC 24 |
| Finished | Oct 09 07:13:37 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831969798 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1831969798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/25.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.2499485383 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 23613549 ps |
| CPU time | 0.7 seconds |
| Started | Oct 09 07:13:35 AM UTC 24 |
| Finished | Oct 09 07:13:37 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499485383 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2499485383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/26.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.3433891258 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 31105520 ps |
| CPU time | 0.79 seconds |
| Started | Oct 09 07:13:35 AM UTC 24 |
| Finished | Oct 09 07:13:37 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433891258 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3433891258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/27.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.3937541476 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 49824159 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 07:13:36 AM UTC 24 |
| Finished | Oct 09 07:13:38 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937541476 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3937541476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/28.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.1990680465 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 32986348 ps |
| CPU time | 0.69 seconds |
| Started | Oct 09 07:13:36 AM UTC 24 |
| Finished | Oct 09 07:13:38 AM UTC 24 |
| Peak memory | 203020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990680465 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1990680465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/29.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.1412303269 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 302722882 ps |
| CPU time | 10.28 seconds |
| Started | Oct 09 07:13:01 AM UTC 24 |
| Finished | Oct 09 07:13:13 AM UTC 24 |
| Peak memory | 206896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412303269 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1412303269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.1524854109 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 2169707808 ps |
| CPU time | 5.62 seconds |
| Started | Oct 09 07:13:01 AM UTC 24 |
| Finished | Oct 09 07:13:08 AM UTC 24 |
| Peak memory | 206888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524854109 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1524854109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.2454281244 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 55068486 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 07:13:01 AM UTC 24 |
| Finished | Oct 09 07:13:03 AM UTC 24 |
| Peak memory | 206252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454281244 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2454281244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.632570766 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 141428151547 ps |
| CPU time | 1031.97 seconds |
| Started | Oct 09 07:13:03 AM UTC 24 |
| Finished | Oct 09 07:30:28 AM UTC 24 |
| Peak memory | 229116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=632570766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_re set.632570766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.1865848879 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 183847988 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 07:13:01 AM UTC 24 |
| Finished | Oct 09 07:13:03 AM UTC 24 |
| Peak memory | 206136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865848879 -assert nopostproc +UVM_TESTNAME=hmac_ba se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1865848879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.3218867641 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 11572496 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 07:13:01 AM UTC 24 |
| Finished | Oct 09 07:13:03 AM UTC 24 |
| Peak memory | 203140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218867641 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3218867641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2841592185 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 44731243 ps |
| CPU time | 1.37 seconds |
| Started | Oct 09 07:13:02 AM UTC 24 |
| Finished | Oct 09 07:13:05 AM UTC 24 |
| Peak memory | 206040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841592185 -assert nopostproc +UV M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_outstanding.2841592185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.2213965666 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 221826712 ps |
| CPU time | 3.26 seconds |
| Started | Oct 09 07:12:59 AM UTC 24 |
| Finished | Oct 09 07:13:03 AM UTC 24 |
| Peak memory | 206864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213965666 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2213965666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.3357467525 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 237290843 ps |
| CPU time | 3.82 seconds |
| Started | Oct 09 07:13:00 AM UTC 24 |
| Finished | Oct 09 07:13:05 AM UTC 24 |
| Peak memory | 207144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357467525 -assert nopostproc +UVM_TESTNAM E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.3357467525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.210139935 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 25479621 ps |
| CPU time | 0.78 seconds |
| Started | Oct 09 07:13:36 AM UTC 24 |
| Finished | Oct 09 07:13:38 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210139935 -assert nopostproc +UVM_TESTNAME=hmac_base_t est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.210139935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/30.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.4143854654 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 19487021 ps |
| CPU time | 0.75 seconds |
| Started | Oct 09 07:13:36 AM UTC 24 |
| Finished | Oct 09 07:13:38 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143854654 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.4143854654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/31.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.3545550901 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 16575267 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 07:13:36 AM UTC 24 |
| Finished | Oct 09 07:13:38 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545550901 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3545550901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/32.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.3668281879 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 45582632 ps |
| CPU time | 0.75 seconds |
| Started | Oct 09 07:13:36 AM UTC 24 |
| Finished | Oct 09 07:13:38 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668281879 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3668281879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/33.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.976525793 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 33785646 ps |
| CPU time | 0.77 seconds |
| Started | Oct 09 07:13:36 AM UTC 24 |
| Finished | Oct 09 07:13:38 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976525793 -assert nopostproc +UVM_TESTNAME=hmac_base_t est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.976525793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/34.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.1506768912 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 13984231 ps |
| CPU time | 0.71 seconds |
| Started | Oct 09 07:13:36 AM UTC 24 |
| Finished | Oct 09 07:13:38 AM UTC 24 |
| Peak memory | 203020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506768912 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1506768912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/35.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.4225540348 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 21769240 ps |
| CPU time | 0.72 seconds |
| Started | Oct 09 07:13:36 AM UTC 24 |
| Finished | Oct 09 07:13:38 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225540348 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.4225540348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/36.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.2740592720 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 31775969 ps |
| CPU time | 0.8 seconds |
| Started | Oct 09 07:13:37 AM UTC 24 |
| Finished | Oct 09 07:13:39 AM UTC 24 |
| Peak memory | 202648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740592720 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2740592720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/37.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.2361170247 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 116546957 ps |
| CPU time | 0.67 seconds |
| Started | Oct 09 07:13:38 AM UTC 24 |
| Finished | Oct 09 07:13:39 AM UTC 24 |
| Peak memory | 202472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361170247 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2361170247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/38.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.438786163 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 19140613 ps |
| CPU time | 0.78 seconds |
| Started | Oct 09 07:13:38 AM UTC 24 |
| Finished | Oct 09 07:13:39 AM UTC 24 |
| Peak memory | 202904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438786163 -assert nopostproc +UVM_TESTNAME=hmac_base_t est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.438786163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/39.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.4011240230 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 662838264 ps |
| CPU time | 6.19 seconds |
| Started | Oct 09 07:13:06 AM UTC 24 |
| Finished | Oct 09 07:13:13 AM UTC 24 |
| Peak memory | 206824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011240230 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.4011240230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.2610633877 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1231520411 ps |
| CPU time | 15.05 seconds |
| Started | Oct 09 07:13:05 AM UTC 24 |
| Finished | Oct 09 07:13:21 AM UTC 24 |
| Peak memory | 207088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610633877 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2610633877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.2832497968 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 54248956 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 07:13:04 AM UTC 24 |
| Finished | Oct 09 07:13:07 AM UTC 24 |
| Peak memory | 206288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832497968 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2832497968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.29139503 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 68694797 ps |
| CPU time | 2.5 seconds |
| Started | Oct 09 07:13:06 AM UTC 24 |
| Finished | Oct 09 07:13:10 AM UTC 24 |
| Peak memory | 207188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=29139503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.29139503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.2341369124 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 40509546 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 07:13:05 AM UTC 24 |
| Finished | Oct 09 07:13:07 AM UTC 24 |
| Peak memory | 206076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341369124 -assert nopostproc +UVM_TESTNAME=hmac_ba se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2341369124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.896394719 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 31123586 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 07:13:04 AM UTC 24 |
| Finished | Oct 09 07:13:06 AM UTC 24 |
| Peak memory | 202952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896394719 -assert nopostproc +UVM_TESTNAME=hmac_base_t est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.896394719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.641012283 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 230263397 ps |
| CPU time | 1.99 seconds |
| Started | Oct 09 07:13:06 AM UTC 24 |
| Finished | Oct 09 07:13:09 AM UTC 24 |
| Peak memory | 206084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641012283 -assert nopostproc +UVM _TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_outstanding.641012283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.60873944 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 216753705 ps |
| CPU time | 3.35 seconds |
| Started | Oct 09 07:13:03 AM UTC 24 |
| Finished | Oct 09 07:13:08 AM UTC 24 |
| Peak memory | 206936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60873944 -assert nopostproc +UVM_TESTNAME=hmac_base_te st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.60873944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.2068570510 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1041269792 ps |
| CPU time | 4.63 seconds |
| Started | Oct 09 07:13:04 AM UTC 24 |
| Finished | Oct 09 07:13:10 AM UTC 24 |
| Peak memory | 206824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068570510 -assert nopostproc +UVM_TESTNAM E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2068570510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.4040971278 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 40893902 ps |
| CPU time | 0.74 seconds |
| Started | Oct 09 07:13:38 AM UTC 24 |
| Finished | Oct 09 07:13:39 AM UTC 24 |
| Peak memory | 203020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040971278 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.4040971278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/40.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.1280087946 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 15611461 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 07:13:38 AM UTC 24 |
| Finished | Oct 09 07:13:40 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280087946 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1280087946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/41.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.2453671574 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 35472344 ps |
| CPU time | 0.77 seconds |
| Started | Oct 09 07:13:38 AM UTC 24 |
| Finished | Oct 09 07:13:40 AM UTC 24 |
| Peak memory | 203020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453671574 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2453671574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/42.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.4157390829 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 32773845 ps |
| CPU time | 0.75 seconds |
| Started | Oct 09 07:13:38 AM UTC 24 |
| Finished | Oct 09 07:13:40 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157390829 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.4157390829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/43.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.594014976 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 44609923 ps |
| CPU time | 0.78 seconds |
| Started | Oct 09 07:13:38 AM UTC 24 |
| Finished | Oct 09 07:13:40 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594014976 -assert nopostproc +UVM_TESTNAME=hmac_base_t est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.594014976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/44.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.1735820784 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 12102668 ps |
| CPU time | 0.76 seconds |
| Started | Oct 09 07:13:38 AM UTC 24 |
| Finished | Oct 09 07:13:40 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735820784 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1735820784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/45.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.3130371422 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 48049416 ps |
| CPU time | 0.77 seconds |
| Started | Oct 09 07:13:38 AM UTC 24 |
| Finished | Oct 09 07:13:40 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130371422 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3130371422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/46.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.2980056160 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 11572549 ps |
| CPU time | 0.81 seconds |
| Started | Oct 09 07:13:39 AM UTC 24 |
| Finished | Oct 09 07:13:41 AM UTC 24 |
| Peak memory | 202704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980056160 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2980056160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/47.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.2672935971 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 19806138 ps |
| CPU time | 0.69 seconds |
| Started | Oct 09 07:13:39 AM UTC 24 |
| Finished | Oct 09 07:13:41 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672935971 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2672935971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/48.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.2177245994 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 14291591 ps |
| CPU time | 0.75 seconds |
| Started | Oct 09 07:13:39 AM UTC 24 |
| Finished | Oct 09 07:13:41 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177245994 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2177245994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/49.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.756415995 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 373351120 ps |
| CPU time | 4.06 seconds |
| Started | Oct 09 07:13:08 AM UTC 24 |
| Finished | Oct 09 07:13:13 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=756415995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_re set.756415995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/5.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.1010609175 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 19809227 ps |
| CPU time | 1 seconds |
| Started | Oct 09 07:13:07 AM UTC 24 |
| Finished | Oct 09 07:13:09 AM UTC 24 |
| Peak memory | 206852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010609175 -assert nopostproc +UVM_TESTNAME=hmac_ba se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1010609175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/5.hmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.2633208435 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 46392280 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 07:13:07 AM UTC 24 |
| Finished | Oct 09 07:13:09 AM UTC 24 |
| Peak memory | 203080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633208435 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2633208435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/5.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.423557610 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 33816528 ps |
| CPU time | 1.99 seconds |
| Started | Oct 09 07:13:08 AM UTC 24 |
| Finished | Oct 09 07:13:11 AM UTC 24 |
| Peak memory | 206032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423557610 -assert nopostproc +UVM _TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_outstanding.423557610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/5.hmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.2248977785 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 57022106 ps |
| CPU time | 4.14 seconds |
| Started | Oct 09 07:13:07 AM UTC 24 |
| Finished | Oct 09 07:13:12 AM UTC 24 |
| Peak memory | 206632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248977785 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2248977785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/5.hmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.2000191383 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 256377954 ps |
| CPU time | 2.88 seconds |
| Started | Oct 09 07:13:07 AM UTC 24 |
| Finished | Oct 09 07:13:11 AM UTC 24 |
| Peak memory | 206884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000191383 -assert nopostproc +UVM_TESTNAM E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2000191383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/5.hmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3225159954 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 111402622 ps |
| CPU time | 3.2 seconds |
| Started | Oct 09 07:13:11 AM UTC 24 |
| Finished | Oct 09 07:13:15 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3225159954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_r eset.3225159954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/6.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.697830530 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 33425270 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 07:13:09 AM UTC 24 |
| Finished | Oct 09 07:13:12 AM UTC 24 |
| Peak memory | 206428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697830530 -assert nopostproc +UVM_TESTNAME=hmac_bas e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.697830530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/6.hmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.1075384516 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 24681074 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 07:13:09 AM UTC 24 |
| Finished | Oct 09 07:13:12 AM UTC 24 |
| Peak memory | 203140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075384516 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1075384516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/6.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4100965465 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 25813713 ps |
| CPU time | 1.53 seconds |
| Started | Oct 09 07:13:11 AM UTC 24 |
| Finished | Oct 09 07:13:13 AM UTC 24 |
| Peak memory | 206024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100965465 -assert nopostproc +UV M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_outstanding.4100965465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/6.hmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.4201282111 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 41701253 ps |
| CPU time | 2.33 seconds |
| Started | Oct 09 07:13:09 AM UTC 24 |
| Finished | Oct 09 07:13:13 AM UTC 24 |
| Peak memory | 207204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201282111 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.4201282111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/6.hmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.3451370145 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 364094458 ps |
| CPU time | 2.29 seconds |
| Started | Oct 09 07:13:09 AM UTC 24 |
| Finished | Oct 09 07:13:13 AM UTC 24 |
| Peak memory | 206812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451370145 -assert nopostproc +UVM_TESTNAM E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3451370145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/6.hmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.454153938 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 186770384091 ps |
| CPU time | 856.99 seconds |
| Started | Oct 09 07:13:13 AM UTC 24 |
| Finished | Oct 09 07:27:40 AM UTC 24 |
| Peak memory | 227072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=454153938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_re set.454153938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/7.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.4116188728 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 98326736 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 07:13:12 AM UTC 24 |
| Finished | Oct 09 07:13:14 AM UTC 24 |
| Peak memory | 206492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116188728 -assert nopostproc +UVM_TESTNAME=hmac_ba se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.4116188728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/7.hmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.569649378 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 26172339 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 07:13:12 AM UTC 24 |
| Finished | Oct 09 07:13:14 AM UTC 24 |
| Peak memory | 202952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569649378 -assert nopostproc +UVM_TESTNAME=hmac_base_t est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.569649378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/7.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1020233388 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 232006643 ps |
| CPU time | 2.66 seconds |
| Started | Oct 09 07:13:13 AM UTC 24 |
| Finished | Oct 09 07:13:17 AM UTC 24 |
| Peak memory | 207140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020233388 -assert nopostproc +UV M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_outstanding.1020233388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/7.hmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.4264155891 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 146112332 ps |
| CPU time | 1.39 seconds |
| Started | Oct 09 07:13:11 AM UTC 24 |
| Finished | Oct 09 07:13:13 AM UTC 24 |
| Peak memory | 206148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264155891 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.4264155891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/7.hmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.3726355544 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 915746978 ps |
| CPU time | 5.61 seconds |
| Started | Oct 09 07:13:12 AM UTC 24 |
| Finished | Oct 09 07:13:18 AM UTC 24 |
| Peak memory | 206812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726355544 -assert nopostproc +UVM_TESTNAM E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3726355544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/7.hmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.4069280675 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 155978112 ps |
| CPU time | 2.67 seconds |
| Started | Oct 09 07:13:14 AM UTC 24 |
| Finished | Oct 09 07:13:18 AM UTC 24 |
| Peak memory | 207144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=4069280675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_r eset.4069280675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/8.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.3821198536 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 41792093 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 07:13:14 AM UTC 24 |
| Finished | Oct 09 07:13:16 AM UTC 24 |
| Peak memory | 206076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821198536 -assert nopostproc +UVM_TESTNAME=hmac_ba se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3821198536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/8.hmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.2899463213 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 33875145 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 07:13:14 AM UTC 24 |
| Finished | Oct 09 07:13:16 AM UTC 24 |
| Peak memory | 203140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899463213 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2899463213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/8.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.872085359 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 56621591 ps |
| CPU time | 1.66 seconds |
| Started | Oct 09 07:13:14 AM UTC 24 |
| Finished | Oct 09 07:13:17 AM UTC 24 |
| Peak memory | 206088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872085359 -assert nopostproc +UVM _TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_outstanding.872085359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/8.hmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.942071716 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 353483301 ps |
| CPU time | 3.48 seconds |
| Started | Oct 09 07:13:13 AM UTC 24 |
| Finished | Oct 09 07:13:18 AM UTC 24 |
| Peak memory | 206936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942071716 -assert nopostproc +UVM_TESTNAME=hmac_base_t est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.942071716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/8.hmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.859619246 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 82837658 ps |
| CPU time | 3.52 seconds |
| Started | Oct 09 07:13:17 AM UTC 24 |
| Finished | Oct 09 07:13:21 AM UTC 24 |
| Peak memory | 223324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=859619246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_re set.859619246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/9.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.1496552980 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 14308961 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 07:13:16 AM UTC 24 |
| Finished | Oct 09 07:13:18 AM UTC 24 |
| Peak memory | 205080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496552980 -assert nopostproc +UVM_TESTNAME=hmac_ba se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1496552980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/9.hmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.1599377476 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 68827392 ps |
| CPU time | 0.73 seconds |
| Started | Oct 09 07:13:15 AM UTC 24 |
| Finished | Oct 09 07:13:16 AM UTC 24 |
| Peak memory | 203140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599377476 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1599377476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/9.hmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.500926611 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 293412809 ps |
| CPU time | 2.53 seconds |
| Started | Oct 09 07:13:16 AM UTC 24 |
| Finished | Oct 09 07:13:19 AM UTC 24 |
| Peak memory | 207196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500926611 -assert nopostproc +UVM _TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_outstanding.500926611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/9.hmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.2674713009 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 234866289 ps |
| CPU time | 4.88 seconds |
| Started | Oct 09 07:13:14 AM UTC 24 |
| Finished | Oct 09 07:13:20 AM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674713009 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2674713009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/9.hmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.2178617337 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 126269475 ps |
| CPU time | 5.36 seconds |
| Started | Oct 09 07:13:14 AM UTC 24 |
| Finished | Oct 09 07:13:21 AM UTC 24 |
| Peak memory | 206832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178617337 -assert nopostproc +UVM_TESTNAM E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2178617337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/9.hmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/0.hmac_back_pressure.1465752865 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 693466298 ps |
| CPU time | 39.76 seconds |
| Started | Oct 09 07:38:04 AM UTC 24 |
| Finished | Oct 09 07:38:45 AM UTC 24 |
| Peak memory | 210300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465752865 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1465752865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/0.hmac_datapath_stress.831407773 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 6358315538 ps |
| CPU time | 1474.94 seconds |
| Started | Oct 09 07:38:05 AM UTC 24 |
| Finished | Oct 09 08:02:58 AM UTC 24 |
| Peak memory | 720152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831407773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.831407773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/0.hmac_long_msg.1983386587 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 34904298995 ps |
| CPU time | 129.72 seconds |
| Started | Oct 09 07:38:04 AM UTC 24 |
| Finished | Oct 09 07:40:16 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983386587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1983386587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/0.hmac_sec_cm.1678776245 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 37566878 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 07:38:10 AM UTC 24 |
| Finished | Oct 09 07:38:12 AM UTC 24 |
| Peak memory | 239584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678776245 -assert nopostproc +UVM_TESTNAME=hmac_b ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hm ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1678776245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/0.hmac_smoke.4217000668 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 77799086 ps |
| CPU time | 1.68 seconds |
| Started | Oct 09 07:38:02 AM UTC 24 |
| Finished | Oct 09 07:38:04 AM UTC 24 |
| Peak memory | 209628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217000668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.4217000668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/0.hmac_test_hmac256_vectors.2932651348 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 23011785608 ps |
| CPU time | 85.55 seconds |
| Started | Oct 09 07:38:07 AM UTC 24 |
| Finished | Oct 09 07:39:35 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932651348 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.2932651348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_test_hmac256_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/0.hmac_test_hmac384_vectors.2649362356 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 9552965398 ps |
| CPU time | 105.85 seconds |
| Started | Oct 09 07:38:07 AM UTC 24 |
| Finished | Oct 09 07:39:56 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649362356 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.2649362356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_test_hmac384_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/0.hmac_test_hmac512_vectors.3621936021 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9412826284 ps |
| CPU time | 82.72 seconds |
| Started | Oct 09 07:38:08 AM UTC 24 |
| Finished | Oct 09 07:39:32 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621936021 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.3621936021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_test_hmac512_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/0.hmac_test_sha384_vectors.3699254433 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1216248067658 ps |
| CPU time | 2675.27 seconds |
| Started | Oct 09 07:38:06 AM UTC 24 |
| Finished | Oct 09 08:23:16 AM UTC 24 |
| Peak memory | 230448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699254433 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.3699254433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_test_sha384_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/0.hmac_test_sha512_vectors.3618573929 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 288009589667 ps |
| CPU time | 2563.95 seconds |
| Started | Oct 09 07:38:06 AM UTC 24 |
| Finished | Oct 09 08:21:20 AM UTC 24 |
| Peak memory | 230376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618573929 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.3618573929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_test_sha512_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/0.hmac_wipe_secret.706336995 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2948490430 ps |
| CPU time | 44.27 seconds |
| Started | Oct 09 07:38:05 AM UTC 24 |
| Finished | Oct 09 07:38:51 AM UTC 24 |
| Peak memory | 210472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706336995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.706336995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/0.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/1.hmac_alert_test.4288365544 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 115746863 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 07:38:32 AM UTC 24 |
| Finished | Oct 09 07:38:34 AM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288365544 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.4288365544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/1.hmac_back_pressure.2260871208 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1494758849 ps |
| CPU time | 58.46 seconds |
| Started | Oct 09 07:38:13 AM UTC 24 |
| Finished | Oct 09 07:39:13 AM UTC 24 |
| Peak memory | 210416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260871208 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2260871208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/1.hmac_datapath_stress.2853529390 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 9708573864 ps |
| CPU time | 839.81 seconds |
| Started | Oct 09 07:38:13 AM UTC 24 |
| Finished | Oct 09 07:52:22 AM UTC 24 |
| Peak memory | 703948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853529390 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2853529390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/1.hmac_long_msg.858838453 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 19083855107 ps |
| CPU time | 81.3 seconds |
| Started | Oct 09 07:38:13 AM UTC 24 |
| Finished | Oct 09 07:39:36 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858838453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.858838453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/1.hmac_smoke.3654476692 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 23233938 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 07:38:13 AM UTC 24 |
| Finished | Oct 09 07:38:15 AM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654476692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3654476692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/1.hmac_stress_all.2509517936 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 973890850 ps |
| CPU time | 26.91 seconds |
| Started | Oct 09 07:38:25 AM UTC 24 |
| Finished | Oct 09 07:38:53 AM UTC 24 |
| Peak memory | 210304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509517936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2509517936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/1.hmac_test_hmac256_vectors.4151441234 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 5352040617 ps |
| CPU time | 58.72 seconds |
| Started | Oct 09 07:38:18 AM UTC 24 |
| Finished | Oct 09 07:39:18 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151441234 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.4151441234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_test_hmac256_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/1.hmac_test_hmac384_vectors.2217924405 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 95778905995 ps |
| CPU time | 106.01 seconds |
| Started | Oct 09 07:38:23 AM UTC 24 |
| Finished | Oct 09 07:40:11 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217924405 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.2217924405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_test_hmac384_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/1.hmac_test_hmac512_vectors.3988165308 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 11058038542 ps |
| CPU time | 139.65 seconds |
| Started | Oct 09 07:38:24 AM UTC 24 |
| Finished | Oct 09 07:40:46 AM UTC 24 |
| Peak memory | 210744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988165308 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.3988165308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_test_hmac512_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/1.hmac_test_sha256_vectors.2063619263 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 162650405410 ps |
| CPU time | 632.53 seconds |
| Started | Oct 09 07:38:16 AM UTC 24 |
| Finished | Oct 09 07:48:57 AM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063619263 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.2063619263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_test_sha256_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/1.hmac_test_sha384_vectors.1366340500 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 140133745696 ps |
| CPU time | 2728.85 seconds |
| Started | Oct 09 07:38:16 AM UTC 24 |
| Finished | Oct 09 08:24:18 AM UTC 24 |
| Peak memory | 224560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366340500 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.1366340500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_test_sha384_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/1.hmac_test_sha512_vectors.2700463352 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 189339467978 ps |
| CPU time | 2638.55 seconds |
| Started | Oct 09 07:38:18 AM UTC 24 |
| Finished | Oct 09 08:22:47 AM UTC 24 |
| Peak memory | 230740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700463352 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2700463352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_test_sha512_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/1.hmac_wipe_secret.1443677506 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 12986780515 ps |
| CPU time | 68.14 seconds |
| Started | Oct 09 07:38:16 AM UTC 24 |
| Finished | Oct 09 07:39:26 AM UTC 24 |
| Peak memory | 210728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443677506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1443677506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/1.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/10.hmac_alert_test.1286340603 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 49828347 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 07:41:56 AM UTC 24 |
| Finished | Oct 09 07:41:57 AM UTC 24 |
| Peak memory | 206976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286340603 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1286340603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/10.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/10.hmac_back_pressure.1341936824 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3532103861 ps |
| CPU time | 110.33 seconds |
| Started | Oct 09 07:41:38 AM UTC 24 |
| Finished | Oct 09 07:43:31 AM UTC 24 |
| Peak memory | 219260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341936824 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1341936824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/10.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/10.hmac_burst_wr.37454841 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 8931181801 ps |
| CPU time | 21.73 seconds |
| Started | Oct 09 07:41:47 AM UTC 24 |
| Finished | Oct 09 07:42:10 AM UTC 24 |
| Peak memory | 210544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37454841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac _burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.37454841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/10.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/10.hmac_datapath_stress.767986482 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 3807499207 ps |
| CPU time | 707.85 seconds |
| Started | Oct 09 07:41:38 AM UTC 24 |
| Finished | Oct 09 07:53:34 AM UTC 24 |
| Peak memory | 728244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767986482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.767986482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/10.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/10.hmac_error.2508234208 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1535594753 ps |
| CPU time | 82.59 seconds |
| Started | Oct 09 07:41:47 AM UTC 24 |
| Finished | Oct 09 07:43:11 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508234208 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2508234208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/10.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/10.hmac_long_msg.2647336203 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 2670059213 ps |
| CPU time | 31.41 seconds |
| Started | Oct 09 07:41:36 AM UTC 24 |
| Finished | Oct 09 07:42:09 AM UTC 24 |
| Peak memory | 210372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647336203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2647336203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/10.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/10.hmac_smoke.733971688 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 2784956434 ps |
| CPU time | 7.97 seconds |
| Started | Oct 09 07:41:36 AM UTC 24 |
| Finished | Oct 09 07:41:45 AM UTC 24 |
| Peak memory | 210688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733971688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 10.hmac_smoke.733971688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/10.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/10.hmac_stress_all.2202968253 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 32414329339 ps |
| CPU time | 2350.13 seconds |
| Started | Oct 09 07:41:53 AM UTC 24 |
| Finished | Oct 09 08:21:28 AM UTC 24 |
| Peak memory | 801956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202968253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2202968253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/10.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/10.hmac_wipe_secret.2571409299 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 2186160475 ps |
| CPU time | 37.04 seconds |
| Started | Oct 09 07:41:53 AM UTC 24 |
| Finished | Oct 09 07:42:31 AM UTC 24 |
| Peak memory | 210352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571409299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2571409299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/10.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/11.hmac_alert_test.1860725526 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 49242242 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 07:42:13 AM UTC 24 |
| Finished | Oct 09 07:42:15 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860725526 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1860725526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/11.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/11.hmac_back_pressure.1570996977 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2472746088 ps |
| CPU time | 37.48 seconds |
| Started | Oct 09 07:41:58 AM UTC 24 |
| Finished | Oct 09 07:42:37 AM UTC 24 |
| Peak memory | 210396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570996977 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1570996977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/11.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/11.hmac_burst_wr.988340434 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 579674234 ps |
| CPU time | 37.83 seconds |
| Started | Oct 09 07:42:01 AM UTC 24 |
| Finished | Oct 09 07:42:41 AM UTC 24 |
| Peak memory | 218780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988340434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.988340434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/11.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/11.hmac_datapath_stress.3292281312 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 3496777845 ps |
| CPU time | 773.14 seconds |
| Started | Oct 09 07:42:01 AM UTC 24 |
| Finished | Oct 09 07:55:04 AM UTC 24 |
| Peak memory | 748844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292281312 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3292281312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/11.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/11.hmac_error.3274986819 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 26996672314 ps |
| CPU time | 203.81 seconds |
| Started | Oct 09 07:42:01 AM UTC 24 |
| Finished | Oct 09 07:45:29 AM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274986819 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3274986819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/11.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/11.hmac_long_msg.3678755399 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 15212220264 ps |
| CPU time | 155.9 seconds |
| Started | Oct 09 07:41:58 AM UTC 24 |
| Finished | Oct 09 07:44:37 AM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678755399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3678755399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/11.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/11.hmac_smoke.4230357308 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 135641557 ps |
| CPU time | 2.1 seconds |
| Started | Oct 09 07:41:56 AM UTC 24 |
| Finished | Oct 09 07:41:59 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230357308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.4230357308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/11.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/11.hmac_stress_all.3999327299 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 164894098205 ps |
| CPU time | 1520.64 seconds |
| Started | Oct 09 07:42:10 AM UTC 24 |
| Finished | Oct 09 08:07:48 AM UTC 24 |
| Peak memory | 664764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999327299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3999327299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/11.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/11.hmac_wipe_secret.3100862429 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 8917943421 ps |
| CPU time | 42.2 seconds |
| Started | Oct 09 07:42:06 AM UTC 24 |
| Finished | Oct 09 07:42:50 AM UTC 24 |
| Peak memory | 210352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100862429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3100862429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/11.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/12.hmac_alert_test.24122064 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 37317068 ps |
| CPU time | 0.91 seconds |
| Started | Oct 09 07:42:34 AM UTC 24 |
| Finished | Oct 09 07:42:36 AM UTC 24 |
| Peak memory | 207208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24122064 -assert nopostproc +UVM_TESTNAME=hmac_ba se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.24122064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/12.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/12.hmac_back_pressure.315762155 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 7802786442 ps |
| CPU time | 122.8 seconds |
| Started | Oct 09 07:42:16 AM UTC 24 |
| Finished | Oct 09 07:44:21 AM UTC 24 |
| Peak memory | 227004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315762155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.315762155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/12.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/12.hmac_burst_wr.708017446 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 866528816 ps |
| CPU time | 52.32 seconds |
| Started | Oct 09 07:42:21 AM UTC 24 |
| Finished | Oct 09 07:43:15 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708017446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.708017446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/12.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/12.hmac_datapath_stress.830632199 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 10455390038 ps |
| CPU time | 549.19 seconds |
| Started | Oct 09 07:42:20 AM UTC 24 |
| Finished | Oct 09 07:51:36 AM UTC 24 |
| Peak memory | 748724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830632199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.830632199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/12.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/12.hmac_error.3375038176 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1014352587 ps |
| CPU time | 17.71 seconds |
| Started | Oct 09 07:42:24 AM UTC 24 |
| Finished | Oct 09 07:42:44 AM UTC 24 |
| Peak memory | 210336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375038176 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3375038176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/12.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/12.hmac_long_msg.1219088113 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 42567580054 ps |
| CPU time | 156.26 seconds |
| Started | Oct 09 07:42:16 AM UTC 24 |
| Finished | Oct 09 07:44:55 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219088113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1219088113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/12.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/12.hmac_smoke.183508377 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 109074308 ps |
| CPU time | 6.65 seconds |
| Started | Oct 09 07:42:13 AM UTC 24 |
| Finished | Oct 09 07:42:21 AM UTC 24 |
| Peak memory | 210584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183508377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 12.hmac_smoke.183508377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/12.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/12.hmac_stress_all.440252443 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 30711410326 ps |
| CPU time | 1857.83 seconds |
| Started | Oct 09 07:42:32 AM UTC 24 |
| Finished | Oct 09 08:13:52 AM UTC 24 |
| Peak memory | 750728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440252443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.440252443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/12.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/12.hmac_wipe_secret.2218424338 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 11759556051 ps |
| CPU time | 36.77 seconds |
| Started | Oct 09 07:42:32 AM UTC 24 |
| Finished | Oct 09 07:43:10 AM UTC 24 |
| Peak memory | 210468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218424338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2218424338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/12.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/13.hmac_alert_test.1396985359 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 22656052 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 07:42:56 AM UTC 24 |
| Finished | Oct 09 07:42:58 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396985359 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1396985359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/13.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/13.hmac_back_pressure.3542807958 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 1545265757 ps |
| CPU time | 92.38 seconds |
| Started | Oct 09 07:42:38 AM UTC 24 |
| Finished | Oct 09 07:44:13 AM UTC 24 |
| Peak memory | 210320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542807958 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3542807958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/13.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/13.hmac_datapath_stress.1775331692 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2305731308 ps |
| CPU time | 434.43 seconds |
| Started | Oct 09 07:42:42 AM UTC 24 |
| Finished | Oct 09 07:50:03 AM UTC 24 |
| Peak memory | 702048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775331692 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1775331692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/13.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/13.hmac_error.1906830274 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 2251477091 ps |
| CPU time | 15.39 seconds |
| Started | Oct 09 07:42:51 AM UTC 24 |
| Finished | Oct 09 07:43:08 AM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906830274 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1906830274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/13.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/13.hmac_long_msg.3298839750 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 4722443824 ps |
| CPU time | 49.64 seconds |
| Started | Oct 09 07:42:38 AM UTC 24 |
| Finished | Oct 09 07:43:30 AM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298839750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3298839750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/13.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/13.hmac_stress_all.3166049413 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 85492066647 ps |
| CPU time | 2730.69 seconds |
| Started | Oct 09 07:42:54 AM UTC 24 |
| Finished | Oct 09 08:28:55 AM UTC 24 |
| Peak memory | 797872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166049413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3166049413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/13.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/13.hmac_wipe_secret.2884167777 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 266440178 ps |
| CPU time | 16.96 seconds |
| Started | Oct 09 07:42:54 AM UTC 24 |
| Finished | Oct 09 07:43:12 AM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884167777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2884167777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/13.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/14.hmac_alert_test.3756910092 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 45352718 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 07:43:17 AM UTC 24 |
| Finished | Oct 09 07:43:19 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756910092 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3756910092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/14.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/14.hmac_back_pressure.1178306850 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 595179897 ps |
| CPU time | 12.39 seconds |
| Started | Oct 09 07:43:09 AM UTC 24 |
| Finished | Oct 09 07:43:23 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178306850 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1178306850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/14.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/14.hmac_burst_wr.2932638342 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1966546837 ps |
| CPU time | 31.25 seconds |
| Started | Oct 09 07:43:13 AM UTC 24 |
| Finished | Oct 09 07:43:45 AM UTC 24 |
| Peak memory | 210608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932638342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2932638342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/14.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/14.hmac_datapath_stress.1504414456 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1678109759 ps |
| CPU time | 378.33 seconds |
| Started | Oct 09 07:43:11 AM UTC 24 |
| Finished | Oct 09 07:49:34 AM UTC 24 |
| Peak memory | 720012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504414456 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1504414456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/14.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/14.hmac_error.1459983614 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 14852626219 ps |
| CPU time | 204.18 seconds |
| Started | Oct 09 07:43:13 AM UTC 24 |
| Finished | Oct 09 07:46:40 AM UTC 24 |
| Peak memory | 210628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459983614 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1459983614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/14.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/14.hmac_long_msg.668699408 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1694946428 ps |
| CPU time | 95.69 seconds |
| Started | Oct 09 07:43:02 AM UTC 24 |
| Finished | Oct 09 07:44:41 AM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668699408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.668699408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/14.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/14.hmac_smoke.577962816 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 147636394 ps |
| CPU time | 9.12 seconds |
| Started | Oct 09 07:42:59 AM UTC 24 |
| Finished | Oct 09 07:43:10 AM UTC 24 |
| Peak memory | 210304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577962816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 14.hmac_smoke.577962816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/14.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/14.hmac_stress_all.404589062 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 67734492035 ps |
| CPU time | 4138.59 seconds |
| Started | Oct 09 07:43:17 AM UTC 24 |
| Finished | Oct 09 08:52:58 AM UTC 24 |
| Peak memory | 838900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404589062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.404589062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/14.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/14.hmac_wipe_secret.4265094977 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 4356411484 ps |
| CPU time | 101.72 seconds |
| Started | Oct 09 07:43:13 AM UTC 24 |
| Finished | Oct 09 07:44:57 AM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265094977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.4265094977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/14.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/15.hmac_alert_test.2001169925 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 14213591 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 07:43:36 AM UTC 24 |
| Finished | Oct 09 07:43:37 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001169925 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2001169925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/15.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/15.hmac_back_pressure.4233314029 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2780775443 ps |
| CPU time | 32.74 seconds |
| Started | Oct 09 07:43:19 AM UTC 24 |
| Finished | Oct 09 07:43:54 AM UTC 24 |
| Peak memory | 210444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233314029 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.4233314029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/15.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/15.hmac_burst_wr.3532706904 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 3497058200 ps |
| CPU time | 61.28 seconds |
| Started | Oct 09 07:43:31 AM UTC 24 |
| Finished | Oct 09 07:44:34 AM UTC 24 |
| Peak memory | 218940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532706904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3532706904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/15.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/15.hmac_datapath_stress.4020658634 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 34214555555 ps |
| CPU time | 1009.05 seconds |
| Started | Oct 09 07:43:24 AM UTC 24 |
| Finished | Oct 09 08:00:24 AM UTC 24 |
| Peak memory | 736792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020658634 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.4020658634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/15.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/15.hmac_error.319992423 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 53856606386 ps |
| CPU time | 215.25 seconds |
| Started | Oct 09 07:43:34 AM UTC 24 |
| Finished | Oct 09 07:47:12 AM UTC 24 |
| Peak memory | 210608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319992423 -assert nopostproc +UVM_TESTNAME=hma c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.319992423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/15.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/15.hmac_long_msg.2193034652 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 11064447477 ps |
| CPU time | 181.16 seconds |
| Started | Oct 09 07:43:17 AM UTC 24 |
| Finished | Oct 09 07:46:22 AM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193034652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2193034652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/15.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/15.hmac_stress_all.777515260 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1277713465017 ps |
| CPU time | 1951.28 seconds |
| Started | Oct 09 07:43:36 AM UTC 24 |
| Finished | Oct 09 08:16:28 AM UTC 24 |
| Peak memory | 675268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777515260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.777515260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/15.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/15.hmac_wipe_secret.3696484738 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 2272432330 ps |
| CPU time | 9.08 seconds |
| Started | Oct 09 07:43:34 AM UTC 24 |
| Finished | Oct 09 07:43:44 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696484738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3696484738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/15.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/16.hmac_alert_test.620672803 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 34873070 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 07:43:53 AM UTC 24 |
| Finished | Oct 09 07:43:55 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620672803 -assert nopostproc +UVM_TESTNAME=hmac_b ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hm ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.620672803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/16.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/16.hmac_back_pressure.1352081711 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 3330797284 ps |
| CPU time | 109.99 seconds |
| Started | Oct 09 07:43:39 AM UTC 24 |
| Finished | Oct 09 07:45:32 AM UTC 24 |
| Peak memory | 210544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352081711 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1352081711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/16.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/16.hmac_burst_wr.2462318845 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 523839878 ps |
| CPU time | 6.86 seconds |
| Started | Oct 09 07:43:44 AM UTC 24 |
| Finished | Oct 09 07:43:51 AM UTC 24 |
| Peak memory | 210272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462318845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2462318845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/16.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/16.hmac_datapath_stress.45503745 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 2931941900 ps |
| CPU time | 438.17 seconds |
| Started | Oct 09 07:43:41 AM UTC 24 |
| Finished | Oct 09 07:51:05 AM UTC 24 |
| Peak memory | 695900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45503745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV M_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.45503745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/16.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/16.hmac_error.2118821486 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 10265772570 ps |
| CPU time | 239.17 seconds |
| Started | Oct 09 07:43:45 AM UTC 24 |
| Finished | Oct 09 07:47:47 AM UTC 24 |
| Peak memory | 210372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118821486 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2118821486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/16.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/16.hmac_long_msg.4273432584 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 2690334744 ps |
| CPU time | 170.44 seconds |
| Started | Oct 09 07:43:39 AM UTC 24 |
| Finished | Oct 09 07:46:33 AM UTC 24 |
| Peak memory | 210384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273432584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.4273432584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/16.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/16.hmac_smoke.1181935710 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 233756057 ps |
| CPU time | 6.23 seconds |
| Started | Oct 09 07:43:36 AM UTC 24 |
| Finished | Oct 09 07:43:43 AM UTC 24 |
| Peak memory | 210356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181935710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1181935710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/16.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/16.hmac_stress_all.3814921377 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 34114914738 ps |
| CPU time | 2843.05 seconds |
| Started | Oct 09 07:43:52 AM UTC 24 |
| Finished | Oct 09 08:31:43 AM UTC 24 |
| Peak memory | 794120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814921377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3814921377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/16.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/16.hmac_wipe_secret.1568434055 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1262551857 ps |
| CPU time | 67.37 seconds |
| Started | Oct 09 07:43:46 AM UTC 24 |
| Finished | Oct 09 07:44:55 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568434055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1568434055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/16.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/17.hmac_alert_test.522355308 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 116079861 ps |
| CPU time | 0.91 seconds |
| Started | Oct 09 07:44:39 AM UTC 24 |
| Finished | Oct 09 07:44:41 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522355308 -assert nopostproc +UVM_TESTNAME=hmac_b ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hm ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.522355308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/17.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/17.hmac_back_pressure.3625944862 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 1594805579 ps |
| CPU time | 117.98 seconds |
| Started | Oct 09 07:44:02 AM UTC 24 |
| Finished | Oct 09 07:46:02 AM UTC 24 |
| Peak memory | 210340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625944862 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3625944862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/17.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/17.hmac_burst_wr.642268751 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1479820627 ps |
| CPU time | 72.18 seconds |
| Started | Oct 09 07:44:13 AM UTC 24 |
| Finished | Oct 09 07:45:27 AM UTC 24 |
| Peak memory | 210260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642268751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.642268751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/17.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/17.hmac_datapath_stress.116001183 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 3425939396 ps |
| CPU time | 741.55 seconds |
| Started | Oct 09 07:44:10 AM UTC 24 |
| Finished | Oct 09 07:56:41 AM UTC 24 |
| Peak memory | 771336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116001183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.116001183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/17.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/17.hmac_error.392730607 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 1619874125 ps |
| CPU time | 59.35 seconds |
| Started | Oct 09 07:44:15 AM UTC 24 |
| Finished | Oct 09 07:45:16 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392730607 -assert nopostproc +UVM_TESTNAME=hma c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.392730607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/17.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/17.hmac_long_msg.495057376 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 7301507789 ps |
| CPU time | 187.24 seconds |
| Started | Oct 09 07:43:56 AM UTC 24 |
| Finished | Oct 09 07:47:07 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495057376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.495057376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/17.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/17.hmac_smoke.2687658454 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1896229795 ps |
| CPU time | 14.76 seconds |
| Started | Oct 09 07:43:56 AM UTC 24 |
| Finished | Oct 09 07:44:12 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687658454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2687658454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/17.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/17.hmac_stress_all.797721747 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 8842861280 ps |
| CPU time | 494.08 seconds |
| Started | Oct 09 07:44:35 AM UTC 24 |
| Finished | Oct 09 07:52:56 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797721747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.797721747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/17.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/17.hmac_wipe_secret.42278310 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 785648311 ps |
| CPU time | 44 seconds |
| Started | Oct 09 07:44:24 AM UTC 24 |
| Finished | Oct 09 07:45:09 AM UTC 24 |
| Peak memory | 210280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42278310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac _wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.42278310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/17.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/18.hmac_alert_test.2441960776 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 23739905 ps |
| CPU time | 0.91 seconds |
| Started | Oct 09 07:45:19 AM UTC 24 |
| Finished | Oct 09 07:45:21 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441960776 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2441960776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/18.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/18.hmac_back_pressure.1780711550 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 1033666434 ps |
| CPU time | 55.47 seconds |
| Started | Oct 09 07:44:52 AM UTC 24 |
| Finished | Oct 09 07:45:49 AM UTC 24 |
| Peak memory | 210336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780711550 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1780711550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/18.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/18.hmac_burst_wr.929715811 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 2775314521 ps |
| CPU time | 22.63 seconds |
| Started | Oct 09 07:44:59 AM UTC 24 |
| Finished | Oct 09 07:45:23 AM UTC 24 |
| Peak memory | 210444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929715811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.929715811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/18.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/18.hmac_datapath_stress.111041275 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 23840720684 ps |
| CPU time | 543.72 seconds |
| Started | Oct 09 07:44:59 AM UTC 24 |
| Finished | Oct 09 07:54:10 AM UTC 24 |
| Peak memory | 648436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111041275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.111041275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/18.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/18.hmac_error.168722455 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 12154839298 ps |
| CPU time | 126.95 seconds |
| Started | Oct 09 07:44:59 AM UTC 24 |
| Finished | Oct 09 07:47:09 AM UTC 24 |
| Peak memory | 210456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168722455 -assert nopostproc +UVM_TESTNAME=hma c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.168722455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/18.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/18.hmac_long_msg.1098565074 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 3050722392 ps |
| CPU time | 212.01 seconds |
| Started | Oct 09 07:44:43 AM UTC 24 |
| Finished | Oct 09 07:48:19 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098565074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1098565074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/18.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/18.hmac_smoke.178576294 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 156158841 ps |
| CPU time | 6.61 seconds |
| Started | Oct 09 07:44:42 AM UTC 24 |
| Finished | Oct 09 07:44:51 AM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178576294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 18.hmac_smoke.178576294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/18.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/18.hmac_stress_all.763099936 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 34764329972 ps |
| CPU time | 2448.44 seconds |
| Started | Oct 09 07:45:11 AM UTC 24 |
| Finished | Oct 09 08:26:26 AM UTC 24 |
| Peak memory | 767248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763099936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.763099936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/18.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/18.hmac_wipe_secret.4155210333 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 4515964305 ps |
| CPU time | 95.23 seconds |
| Started | Oct 09 07:44:59 AM UTC 24 |
| Finished | Oct 09 07:46:37 AM UTC 24 |
| Peak memory | 210764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155210333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.4155210333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/18.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/19.hmac_alert_test.1801015905 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 23156032 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 07:45:49 AM UTC 24 |
| Finished | Oct 09 07:45:51 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801015905 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1801015905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/19.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/19.hmac_back_pressure.3242055810 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1590643626 ps |
| CPU time | 110.24 seconds |
| Started | Oct 09 07:45:24 AM UTC 24 |
| Finished | Oct 09 07:47:17 AM UTC 24 |
| Peak memory | 210280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242055810 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3242055810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/19.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/19.hmac_burst_wr.1012072465 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 351023179 ps |
| CPU time | 18.21 seconds |
| Started | Oct 09 07:45:29 AM UTC 24 |
| Finished | Oct 09 07:45:48 AM UTC 24 |
| Peak memory | 210608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012072465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1012072465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/19.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/19.hmac_datapath_stress.2361258222 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 735897492 ps |
| CPU time | 136.05 seconds |
| Started | Oct 09 07:45:29 AM UTC 24 |
| Finished | Oct 09 07:47:47 AM UTC 24 |
| Peak memory | 650616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361258222 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2361258222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/19.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/19.hmac_error.4046874483 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 7509060944 ps |
| CPU time | 126.42 seconds |
| Started | Oct 09 07:45:30 AM UTC 24 |
| Finished | Oct 09 07:47:40 AM UTC 24 |
| Peak memory | 210460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046874483 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.4046874483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/19.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/19.hmac_long_msg.733983247 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 7212781015 ps |
| CPU time | 24.12 seconds |
| Started | Oct 09 07:45:22 AM UTC 24 |
| Finished | Oct 09 07:45:48 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733983247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.733983247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/19.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/19.hmac_smoke.3238026954 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 4233611538 ps |
| CPU time | 7.39 seconds |
| Started | Oct 09 07:45:19 AM UTC 24 |
| Finished | Oct 09 07:45:28 AM UTC 24 |
| Peak memory | 210408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238026954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3238026954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/19.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/19.hmac_stress_all.1940742960 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 10019912007 ps |
| CPU time | 32.22 seconds |
| Started | Oct 09 07:45:49 AM UTC 24 |
| Finished | Oct 09 07:46:22 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940742960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1940742960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/19.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/19.hmac_wipe_secret.1659913048 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 2969085477 ps |
| CPU time | 87.12 seconds |
| Started | Oct 09 07:45:33 AM UTC 24 |
| Finished | Oct 09 07:47:03 AM UTC 24 |
| Peak memory | 210676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659913048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1659913048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/19.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/2.hmac_alert_test.1751269936 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 29416041 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 07:38:55 AM UTC 24 |
| Finished | Oct 09 07:38:57 AM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751269936 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1751269936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/2.hmac_back_pressure.1831778171 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1606322793 ps |
| CPU time | 84.61 seconds |
| Started | Oct 09 07:38:36 AM UTC 24 |
| Finished | Oct 09 07:40:02 AM UTC 24 |
| Peak memory | 210352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831778171 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1831778171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/2.hmac_datapath_stress.1789966834 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 6208532183 ps |
| CPU time | 275 seconds |
| Started | Oct 09 07:38:36 AM UTC 24 |
| Finished | Oct 09 07:43:14 AM UTC 24 |
| Peak memory | 476404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789966834 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1789966834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/2.hmac_error.417354245 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 59615188035 ps |
| CPU time | 215.83 seconds |
| Started | Oct 09 07:38:39 AM UTC 24 |
| Finished | Oct 09 07:42:18 AM UTC 24 |
| Peak memory | 210672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417354245 -assert nopostproc +UVM_TESTNAME=hma c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.417354245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/2.hmac_long_msg.804478979 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 6662566090 ps |
| CPU time | 208.7 seconds |
| Started | Oct 09 07:38:35 AM UTC 24 |
| Finished | Oct 09 07:42:07 AM UTC 24 |
| Peak memory | 210408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804478979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.804478979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/2.hmac_sec_cm.1530905944 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 176833870 ps |
| CPU time | 1.32 seconds |
| Started | Oct 09 07:38:53 AM UTC 24 |
| Finished | Oct 09 07:38:56 AM UTC 24 |
| Peak memory | 239520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530905944 -assert nopostproc +UVM_TESTNAME=hmac_b ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hm ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1530905944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/2.hmac_smoke.2267230320 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 201368232 ps |
| CPU time | 2.46 seconds |
| Started | Oct 09 07:38:33 AM UTC 24 |
| Finished | Oct 09 07:38:37 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267230320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2267230320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/2.hmac_stress_all.536197782 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 52797503964 ps |
| CPU time | 976.75 seconds |
| Started | Oct 09 07:38:52 AM UTC 24 |
| Finished | Oct 09 07:55:20 AM UTC 24 |
| Peak memory | 689344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536197782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.536197782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/2.hmac_stress_all_with_rand_reset.187366114 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 95162838559 ps |
| CPU time | 157.67 seconds |
| Started | Oct 09 07:38:53 AM UTC 24 |
| Finished | Oct 09 07:41:34 AM UTC 24 |
| Peak memory | 355696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18736611 4 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.187366114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/2.hmac_test_hmac256_vectors.244207018 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 1709762395 ps |
| CPU time | 84.24 seconds |
| Started | Oct 09 07:38:47 AM UTC 24 |
| Finished | Oct 09 07:40:13 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244207018 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.244207018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_test_hmac256_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/2.hmac_test_hmac384_vectors.2814828312 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 9257888088 ps |
| CPU time | 102.9 seconds |
| Started | Oct 09 07:38:48 AM UTC 24 |
| Finished | Oct 09 07:40:33 AM UTC 24 |
| Peak memory | 210508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814828312 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.2814828312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_test_hmac384_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/2.hmac_test_hmac512_vectors.2402969404 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 18770539438 ps |
| CPU time | 67.41 seconds |
| Started | Oct 09 07:38:50 AM UTC 24 |
| Finished | Oct 09 07:39:59 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402969404 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.2402969404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_test_hmac512_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/2.hmac_test_sha256_vectors.3922352944 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 76022653173 ps |
| CPU time | 723.95 seconds |
| Started | Oct 09 07:38:42 AM UTC 24 |
| Finished | Oct 09 07:50:56 AM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922352944 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3922352944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_test_sha256_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/2.hmac_test_sha384_vectors.681965204 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 356678136979 ps |
| CPU time | 2810.5 seconds |
| Started | Oct 09 07:38:43 AM UTC 24 |
| Finished | Oct 09 08:26:08 AM UTC 24 |
| Peak memory | 230520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681965204 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.681965204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_test_sha384_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/2.hmac_test_sha512_vectors.3817968474 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 765958595537 ps |
| CPU time | 2615.5 seconds |
| Started | Oct 09 07:38:45 AM UTC 24 |
| Finished | Oct 09 08:22:50 AM UTC 24 |
| Peak memory | 214356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817968474 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.3817968474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_test_sha512_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/2.hmac_wipe_secret.1535244881 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 6908771083 ps |
| CPU time | 96.83 seconds |
| Started | Oct 09 07:38:41 AM UTC 24 |
| Finished | Oct 09 07:40:20 AM UTC 24 |
| Peak memory | 210732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535244881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1535244881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/2.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/20.hmac_alert_test.2567750759 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 132095327 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 07:46:38 AM UTC 24 |
| Finished | Oct 09 07:46:40 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567750759 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2567750759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/20.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/20.hmac_back_pressure.2866899219 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 7266050428 ps |
| CPU time | 68.19 seconds |
| Started | Oct 09 07:45:56 AM UTC 24 |
| Finished | Oct 09 07:47:06 AM UTC 24 |
| Peak memory | 210464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866899219 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2866899219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/20.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/20.hmac_datapath_stress.3754907357 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 4545839142 ps |
| CPU time | 878.53 seconds |
| Started | Oct 09 07:46:04 AM UTC 24 |
| Finished | Oct 09 08:00:53 AM UTC 24 |
| Peak memory | 681308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754907357 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3754907357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/20.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/20.hmac_error.3265408388 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 2486352680 ps |
| CPU time | 11.28 seconds |
| Started | Oct 09 07:46:24 AM UTC 24 |
| Finished | Oct 09 07:46:37 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265408388 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3265408388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/20.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/20.hmac_long_msg.534794146 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 7790820076 ps |
| CPU time | 71.18 seconds |
| Started | Oct 09 07:45:52 AM UTC 24 |
| Finished | Oct 09 07:47:05 AM UTC 24 |
| Peak memory | 218992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534794146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.534794146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/20.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/20.hmac_smoke.3194250725 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 41011323 ps |
| CPU time | 2.79 seconds |
| Started | Oct 09 07:45:50 AM UTC 24 |
| Finished | Oct 09 07:45:54 AM UTC 24 |
| Peak memory | 210236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194250725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3194250725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/20.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/20.hmac_stress_all.1358476902 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 55931146361 ps |
| CPU time | 4142.45 seconds |
| Started | Oct 09 07:46:38 AM UTC 24 |
| Finished | Oct 09 08:56:20 AM UTC 24 |
| Peak memory | 824440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358476902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1358476902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/20.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/20.hmac_wipe_secret.3547235880 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 3040365325 ps |
| CPU time | 41.45 seconds |
| Started | Oct 09 07:46:34 AM UTC 24 |
| Finished | Oct 09 07:47:17 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547235880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3547235880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/20.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/21.hmac_alert_test.2500508345 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 13202159 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 07:47:09 AM UTC 24 |
| Finished | Oct 09 07:47:12 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500508345 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2500508345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/21.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/21.hmac_back_pressure.2701089431 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 558157766 ps |
| CPU time | 43.33 seconds |
| Started | Oct 09 07:46:47 AM UTC 24 |
| Finished | Oct 09 07:47:32 AM UTC 24 |
| Peak memory | 210300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701089431 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2701089431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/21.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/21.hmac_burst_wr.318023205 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 326083393 ps |
| CPU time | 22.64 seconds |
| Started | Oct 09 07:46:57 AM UTC 24 |
| Finished | Oct 09 07:47:21 AM UTC 24 |
| Peak memory | 210244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318023205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.318023205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/21.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/21.hmac_datapath_stress.1170078727 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1391998301 ps |
| CPU time | 237.34 seconds |
| Started | Oct 09 07:46:54 AM UTC 24 |
| Finished | Oct 09 07:50:55 AM UTC 24 |
| Peak memory | 441776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170078727 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1170078727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/21.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/21.hmac_error.3148473535 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 3201726523 ps |
| CPU time | 205.93 seconds |
| Started | Oct 09 07:47:05 AM UTC 24 |
| Finished | Oct 09 07:50:34 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148473535 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3148473535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/21.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/21.hmac_long_msg.4250808582 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 6659823998 ps |
| CPU time | 92.27 seconds |
| Started | Oct 09 07:46:42 AM UTC 24 |
| Finished | Oct 09 07:48:16 AM UTC 24 |
| Peak memory | 210424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250808582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.4250808582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/21.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/21.hmac_smoke.2580015229 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 419821348 ps |
| CPU time | 3.09 seconds |
| Started | Oct 09 07:46:42 AM UTC 24 |
| Finished | Oct 09 07:46:46 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580015229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2580015229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/21.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/21.hmac_stress_all.3362326143 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 42495288099 ps |
| CPU time | 422.83 seconds |
| Started | Oct 09 07:47:07 AM UTC 24 |
| Finished | Oct 09 07:54:16 AM UTC 24 |
| Peak memory | 219004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362326143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3362326143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/21.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/21.hmac_wipe_secret.3915561941 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1794320375 ps |
| CPU time | 92.3 seconds |
| Started | Oct 09 07:47:07 AM UTC 24 |
| Finished | Oct 09 07:48:42 AM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915561941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3915561941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/21.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/22.hmac_alert_test.582652679 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 54033956 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 07:47:22 AM UTC 24 |
| Finished | Oct 09 07:47:25 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582652679 -assert nopostproc +UVM_TESTNAME=hmac_b ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hm ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.582652679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/22.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/22.hmac_back_pressure.3107619927 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1056047943 ps |
| CPU time | 75.1 seconds |
| Started | Oct 09 07:47:12 AM UTC 24 |
| Finished | Oct 09 07:48:29 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107619927 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3107619927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/22.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/22.hmac_burst_wr.2747907126 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 32120341393 ps |
| CPU time | 66.41 seconds |
| Started | Oct 09 07:47:17 AM UTC 24 |
| Finished | Oct 09 07:48:25 AM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747907126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2747907126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/22.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/22.hmac_datapath_stress.357951846 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 119863969 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 07:47:14 AM UTC 24 |
| Finished | Oct 09 07:47:16 AM UTC 24 |
| Peak memory | 209536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357951846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.357951846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/22.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/22.hmac_error.1160729476 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 5284231905 ps |
| CPU time | 83.74 seconds |
| Started | Oct 09 07:47:19 AM UTC 24 |
| Finished | Oct 09 07:48:45 AM UTC 24 |
| Peak memory | 210684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160729476 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1160729476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/22.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/22.hmac_long_msg.3091844065 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 9890051928 ps |
| CPU time | 98.81 seconds |
| Started | Oct 09 07:47:11 AM UTC 24 |
| Finished | Oct 09 07:48:52 AM UTC 24 |
| Peak memory | 210464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091844065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3091844065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/22.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/22.hmac_smoke.2466139275 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 476475402 ps |
| CPU time | 6.16 seconds |
| Started | Oct 09 07:47:10 AM UTC 24 |
| Finished | Oct 09 07:47:17 AM UTC 24 |
| Peak memory | 210416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466139275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2466139275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/22.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/22.hmac_stress_all.2090793401 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 234525114795 ps |
| CPU time | 2023.06 seconds |
| Started | Oct 09 07:47:20 AM UTC 24 |
| Finished | Oct 09 08:21:24 AM UTC 24 |
| Peak memory | 765256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090793401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2090793401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/22.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/22.hmac_wipe_secret.792157097 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 13218588335 ps |
| CPU time | 36.37 seconds |
| Started | Oct 09 07:47:19 AM UTC 24 |
| Finished | Oct 09 07:47:57 AM UTC 24 |
| Peak memory | 210408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792157097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.792157097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/22.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/23.hmac_alert_test.2407911051 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 13588536 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 07:48:17 AM UTC 24 |
| Finished | Oct 09 07:48:19 AM UTC 24 |
| Peak memory | 207216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407911051 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2407911051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/23.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/23.hmac_back_pressure.3485217570 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 826508374 ps |
| CPU time | 47.58 seconds |
| Started | Oct 09 07:47:41 AM UTC 24 |
| Finished | Oct 09 07:48:30 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485217570 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3485217570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/23.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/23.hmac_burst_wr.2495307172 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 7814865359 ps |
| CPU time | 61.85 seconds |
| Started | Oct 09 07:47:44 AM UTC 24 |
| Finished | Oct 09 07:48:48 AM UTC 24 |
| Peak memory | 210384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495307172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2495307172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/23.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/23.hmac_datapath_stress.2311344239 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 18645141040 ps |
| CPU time | 681.47 seconds |
| Started | Oct 09 07:47:42 AM UTC 24 |
| Finished | Oct 09 07:59:12 AM UTC 24 |
| Peak memory | 720224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311344239 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2311344239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/23.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/23.hmac_error.352471010 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 1423318439 ps |
| CPU time | 76.39 seconds |
| Started | Oct 09 07:47:50 AM UTC 24 |
| Finished | Oct 09 07:49:08 AM UTC 24 |
| Peak memory | 210236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352471010 -assert nopostproc +UVM_TESTNAME=hma c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.352471010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/23.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/23.hmac_long_msg.889539196 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 1964248802 ps |
| CPU time | 8.75 seconds |
| Started | Oct 09 07:47:33 AM UTC 24 |
| Finished | Oct 09 07:47:43 AM UTC 24 |
| Peak memory | 210600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889539196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.889539196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/23.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/23.hmac_smoke.1550116866 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 877754222 ps |
| CPU time | 13.94 seconds |
| Started | Oct 09 07:47:26 AM UTC 24 |
| Finished | Oct 09 07:47:41 AM UTC 24 |
| Peak memory | 210636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550116866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1550116866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/23.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/23.hmac_stress_all.146770383 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 254525157114 ps |
| CPU time | 1757.2 seconds |
| Started | Oct 09 07:47:58 AM UTC 24 |
| Finished | Oct 09 08:17:36 AM UTC 24 |
| Peak memory | 781504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146770383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.146770383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/23.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/23.hmac_wipe_secret.1586035591 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 617275534 ps |
| CPU time | 45.17 seconds |
| Started | Oct 09 07:47:50 AM UTC 24 |
| Finished | Oct 09 07:48:37 AM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586035591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1586035591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/23.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/24.hmac_alert_test.2542862248 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 33121402 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 07:48:43 AM UTC 24 |
| Finished | Oct 09 07:48:45 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542862248 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2542862248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/24.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/24.hmac_back_pressure.2964459357 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 302061180 ps |
| CPU time | 15.96 seconds |
| Started | Oct 09 07:48:26 AM UTC 24 |
| Finished | Oct 09 07:48:44 AM UTC 24 |
| Peak memory | 210340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964459357 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2964459357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/24.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/24.hmac_burst_wr.1942071213 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 4378016616 ps |
| CPU time | 68.03 seconds |
| Started | Oct 09 07:48:31 AM UTC 24 |
| Finished | Oct 09 07:49:41 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942071213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1942071213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/24.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/24.hmac_datapath_stress.3043558475 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2796555593 ps |
| CPU time | 573.29 seconds |
| Started | Oct 09 07:48:31 AM UTC 24 |
| Finished | Oct 09 07:58:11 AM UTC 24 |
| Peak memory | 726280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043558475 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3043558475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/24.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/24.hmac_error.2077981737 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 4307436457 ps |
| CPU time | 63.59 seconds |
| Started | Oct 09 07:48:40 AM UTC 24 |
| Finished | Oct 09 07:49:46 AM UTC 24 |
| Peak memory | 210724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077981737 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2077981737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/24.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/24.hmac_long_msg.2372188144 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 10169513560 ps |
| CPU time | 50.5 seconds |
| Started | Oct 09 07:48:21 AM UTC 24 |
| Finished | Oct 09 07:49:13 AM UTC 24 |
| Peak memory | 226820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372188144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2372188144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/24.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/24.hmac_smoke.3929668547 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 561953787 ps |
| CPU time | 17.58 seconds |
| Started | Oct 09 07:48:21 AM UTC 24 |
| Finished | Oct 09 07:48:40 AM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929668547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3929668547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/24.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/24.hmac_stress_all.4060077224 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 42201375531 ps |
| CPU time | 864.39 seconds |
| Started | Oct 09 07:48:42 AM UTC 24 |
| Finished | Oct 09 08:03:18 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060077224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.4060077224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/24.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/24.hmac_wipe_secret.765900295 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 24968643346 ps |
| CPU time | 115.28 seconds |
| Started | Oct 09 07:48:40 AM UTC 24 |
| Finished | Oct 09 07:50:38 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765900295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.765900295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/24.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/25.hmac_alert_test.380840044 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 47712983 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 07:49:09 AM UTC 24 |
| Finished | Oct 09 07:49:11 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380840044 -assert nopostproc +UVM_TESTNAME=hmac_b ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hm ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.380840044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/25.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/25.hmac_back_pressure.1724158255 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6821297211 ps |
| CPU time | 98.44 seconds |
| Started | Oct 09 07:48:46 AM UTC 24 |
| Finished | Oct 09 07:50:27 AM UTC 24 |
| Peak memory | 210408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724158255 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1724158255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/25.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/25.hmac_burst_wr.2327340453 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1498439007 ps |
| CPU time | 31.08 seconds |
| Started | Oct 09 07:48:54 AM UTC 24 |
| Finished | Oct 09 07:49:26 AM UTC 24 |
| Peak memory | 219136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327340453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2327340453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/25.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/25.hmac_datapath_stress.1561914267 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 14320609375 ps |
| CPU time | 945.43 seconds |
| Started | Oct 09 07:48:49 AM UTC 24 |
| Finished | Oct 09 08:04:47 AM UTC 24 |
| Peak memory | 718052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561914267 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1561914267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/25.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/25.hmac_error.2385153591 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 6803475099 ps |
| CPU time | 171.4 seconds |
| Started | Oct 09 07:48:57 AM UTC 24 |
| Finished | Oct 09 07:51:52 AM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385153591 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2385153591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/25.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/25.hmac_long_msg.3299169691 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 619360987 ps |
| CPU time | 8.1 seconds |
| Started | Oct 09 07:48:46 AM UTC 24 |
| Finished | Oct 09 07:48:56 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299169691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3299169691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/25.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/25.hmac_smoke.3642880841 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 3019948546 ps |
| CPU time | 18.37 seconds |
| Started | Oct 09 07:48:45 AM UTC 24 |
| Finished | Oct 09 07:49:04 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642880841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3642880841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/25.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/25.hmac_stress_all.2255525016 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 31569008928 ps |
| CPU time | 247.7 seconds |
| Started | Oct 09 07:49:05 AM UTC 24 |
| Finished | Oct 09 07:53:16 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255525016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2255525016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/25.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/25.hmac_wipe_secret.3949593068 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 5750849534 ps |
| CPU time | 77.29 seconds |
| Started | Oct 09 07:49:01 AM UTC 24 |
| Finished | Oct 09 07:50:20 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949593068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3949593068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/25.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/26.hmac_alert_test.3997934736 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 36821055 ps |
| CPU time | 0.91 seconds |
| Started | Oct 09 07:49:49 AM UTC 24 |
| Finished | Oct 09 07:49:51 AM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997934736 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3997934736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/26.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/26.hmac_back_pressure.232276789 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 1976492765 ps |
| CPU time | 77.3 seconds |
| Started | Oct 09 07:49:23 AM UTC 24 |
| Finished | Oct 09 07:50:42 AM UTC 24 |
| Peak memory | 210576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232276789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.232276789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/26.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/26.hmac_burst_wr.1700250319 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1553961448 ps |
| CPU time | 19.2 seconds |
| Started | Oct 09 07:49:27 AM UTC 24 |
| Finished | Oct 09 07:49:48 AM UTC 24 |
| Peak memory | 210580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700250319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1700250319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/26.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/26.hmac_datapath_stress.194099741 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 9202242314 ps |
| CPU time | 881.13 seconds |
| Started | Oct 09 07:49:26 AM UTC 24 |
| Finished | Oct 09 08:04:17 AM UTC 24 |
| Peak memory | 791832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194099741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.194099741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/26.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/26.hmac_error.2736666564 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 19964717838 ps |
| CPU time | 293.52 seconds |
| Started | Oct 09 07:49:36 AM UTC 24 |
| Finished | Oct 09 07:54:34 AM UTC 24 |
| Peak memory | 210464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736666564 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2736666564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/26.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/26.hmac_long_msg.3718839553 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 8222392749 ps |
| CPU time | 106.78 seconds |
| Started | Oct 09 07:49:15 AM UTC 24 |
| Finished | Oct 09 07:51:04 AM UTC 24 |
| Peak memory | 210468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718839553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3718839553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/26.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/26.hmac_smoke.2086881467 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 605287415 ps |
| CPU time | 11.07 seconds |
| Started | Oct 09 07:49:12 AM UTC 24 |
| Finished | Oct 09 07:49:25 AM UTC 24 |
| Peak memory | 210304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086881467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2086881467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/26.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/26.hmac_stress_all.1902208428 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 91063479229 ps |
| CPU time | 1544.61 seconds |
| Started | Oct 09 07:49:47 AM UTC 24 |
| Finished | Oct 09 08:15:49 AM UTC 24 |
| Peak memory | 740848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902208428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1902208428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/26.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/26.hmac_wipe_secret.1224918384 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 66561896583 ps |
| CPU time | 132.7 seconds |
| Started | Oct 09 07:49:42 AM UTC 24 |
| Finished | Oct 09 07:51:58 AM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224918384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1224918384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/26.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/27.hmac_alert_test.2521663624 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 58951835 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 07:50:36 AM UTC 24 |
| Finished | Oct 09 07:50:38 AM UTC 24 |
| Peak memory | 207216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521663624 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2521663624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/27.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/27.hmac_back_pressure.2400523722 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1960834662 ps |
| CPU time | 25.67 seconds |
| Started | Oct 09 07:50:04 AM UTC 24 |
| Finished | Oct 09 07:50:32 AM UTC 24 |
| Peak memory | 210244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400523722 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2400523722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/27.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/27.hmac_burst_wr.1604734792 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 1811066441 ps |
| CPU time | 33.66 seconds |
| Started | Oct 09 07:50:16 AM UTC 24 |
| Finished | Oct 09 07:50:51 AM UTC 24 |
| Peak memory | 218868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604734792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1604734792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/27.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/27.hmac_datapath_stress.536585225 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 572037477 ps |
| CPU time | 124.93 seconds |
| Started | Oct 09 07:50:13 AM UTC 24 |
| Finished | Oct 09 07:52:20 AM UTC 24 |
| Peak memory | 684908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536585225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.536585225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/27.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/27.hmac_error.2299430245 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 60354135685 ps |
| CPU time | 99.98 seconds |
| Started | Oct 09 07:50:22 AM UTC 24 |
| Finished | Oct 09 07:52:04 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299430245 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2299430245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/27.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/27.hmac_long_msg.123679001 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 31255163425 ps |
| CPU time | 139.26 seconds |
| Started | Oct 09 07:49:56 AM UTC 24 |
| Finished | Oct 09 07:52:18 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123679001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.123679001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/27.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/27.hmac_smoke.3641034997 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 913694981 ps |
| CPU time | 18.75 seconds |
| Started | Oct 09 07:49:52 AM UTC 24 |
| Finished | Oct 09 07:50:12 AM UTC 24 |
| Peak memory | 210444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641034997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3641034997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/27.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/27.hmac_stress_all.1126275545 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 24057139070 ps |
| CPU time | 1787.13 seconds |
| Started | Oct 09 07:50:32 AM UTC 24 |
| Finished | Oct 09 08:20:41 AM UTC 24 |
| Peak memory | 777468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126275545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1126275545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/27.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/27.hmac_wipe_secret.351002539 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 12114323370 ps |
| CPU time | 63.85 seconds |
| Started | Oct 09 07:50:29 AM UTC 24 |
| Finished | Oct 09 07:51:35 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351002539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.351002539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/27.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/28.hmac_alert_test.864591088 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 14644513 ps |
| CPU time | 0.96 seconds |
| Started | Oct 09 07:51:07 AM UTC 24 |
| Finished | Oct 09 07:51:09 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864591088 -assert nopostproc +UVM_TESTNAME=hmac_b ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hm ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.864591088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/28.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/28.hmac_back_pressure.3297744004 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 3799372858 ps |
| CPU time | 143.46 seconds |
| Started | Oct 09 07:50:44 AM UTC 24 |
| Finished | Oct 09 07:53:10 AM UTC 24 |
| Peak memory | 210416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297744004 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3297744004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/28.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/28.hmac_burst_wr.477283054 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 1073481572 ps |
| CPU time | 28.97 seconds |
| Started | Oct 09 07:50:55 AM UTC 24 |
| Finished | Oct 09 07:51:25 AM UTC 24 |
| Peak memory | 210516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477283054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.477283054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/28.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/28.hmac_datapath_stress.337270131 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 4049950878 ps |
| CPU time | 499.38 seconds |
| Started | Oct 09 07:50:52 AM UTC 24 |
| Finished | Oct 09 07:59:18 AM UTC 24 |
| Peak memory | 703700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337270131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.337270131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/28.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/28.hmac_error.2318439009 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 6647673234 ps |
| CPU time | 110.57 seconds |
| Started | Oct 09 07:50:59 AM UTC 24 |
| Finished | Oct 09 07:52:52 AM UTC 24 |
| Peak memory | 210788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318439009 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2318439009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/28.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/28.hmac_long_msg.2067505988 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 8546422168 ps |
| CPU time | 63.95 seconds |
| Started | Oct 09 07:50:40 AM UTC 24 |
| Finished | Oct 09 07:51:46 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067505988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2067505988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/28.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/28.hmac_smoke.3742827742 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 1794467920 ps |
| CPU time | 12.68 seconds |
| Started | Oct 09 07:50:40 AM UTC 24 |
| Finished | Oct 09 07:50:54 AM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742827742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3742827742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/28.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/28.hmac_stress_all.4054008205 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 261702350595 ps |
| CPU time | 2741.23 seconds |
| Started | Oct 09 07:51:07 AM UTC 24 |
| Finished | Oct 09 08:37:19 AM UTC 24 |
| Peak memory | 777408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054008205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.4054008205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/28.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/28.hmac_wipe_secret.3400751456 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 18552678150 ps |
| CPU time | 75.25 seconds |
| Started | Oct 09 07:50:59 AM UTC 24 |
| Finished | Oct 09 07:52:16 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400751456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3400751456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/28.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/29.hmac_alert_test.2933583849 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 15226719 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 07:52:01 AM UTC 24 |
| Finished | Oct 09 07:52:03 AM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933583849 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2933583849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/29.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/29.hmac_back_pressure.1449151768 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 5931881322 ps |
| CPU time | 103.27 seconds |
| Started | Oct 09 07:51:27 AM UTC 24 |
| Finished | Oct 09 07:53:12 AM UTC 24 |
| Peak memory | 210508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449151768 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1449151768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/29.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/29.hmac_burst_wr.486761121 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 1523751261 ps |
| CPU time | 19.59 seconds |
| Started | Oct 09 07:51:38 AM UTC 24 |
| Finished | Oct 09 07:51:59 AM UTC 24 |
| Peak memory | 210344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486761121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.486761121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/29.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/29.hmac_datapath_stress.3428272645 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 12493826652 ps |
| CPU time | 908.87 seconds |
| Started | Oct 09 07:51:36 AM UTC 24 |
| Finished | Oct 09 08:06:56 AM UTC 24 |
| Peak memory | 769312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428272645 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3428272645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/29.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/29.hmac_error.3210596786 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 30738067436 ps |
| CPU time | 112.3 seconds |
| Started | Oct 09 07:51:47 AM UTC 24 |
| Finished | Oct 09 07:53:42 AM UTC 24 |
| Peak memory | 210636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210596786 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3210596786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/29.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/29.hmac_long_msg.752972539 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 42575321923 ps |
| CPU time | 115.65 seconds |
| Started | Oct 09 07:51:25 AM UTC 24 |
| Finished | Oct 09 07:53:23 AM UTC 24 |
| Peak memory | 221016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752972539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.752972539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/29.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/29.hmac_smoke.716274471 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 561394079 ps |
| CPU time | 12.21 seconds |
| Started | Oct 09 07:51:10 AM UTC 24 |
| Finished | Oct 09 07:51:24 AM UTC 24 |
| Peak memory | 210520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716274471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 29.hmac_smoke.716274471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/29.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/29.hmac_stress_all.3236311484 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 109452591809 ps |
| CPU time | 5408.04 seconds |
| Started | Oct 09 07:51:59 AM UTC 24 |
| Finished | Oct 09 09:23:01 AM UTC 24 |
| Peak memory | 882164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236311484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3236311484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/29.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/29.hmac_wipe_secret.1455783547 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 9120506125 ps |
| CPU time | 63.14 seconds |
| Started | Oct 09 07:51:53 AM UTC 24 |
| Finished | Oct 09 07:52:58 AM UTC 24 |
| Peak memory | 210464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455783547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1455783547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/29.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/3.hmac_alert_test.2738343216 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 20794423 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 07:39:25 AM UTC 24 |
| Finished | Oct 09 07:39:27 AM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738343216 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2738343216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/3.hmac_back_pressure.2162025307 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1046033286 ps |
| CPU time | 15.38 seconds |
| Started | Oct 09 07:39:02 AM UTC 24 |
| Finished | Oct 09 07:39:18 AM UTC 24 |
| Peak memory | 210336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162025307 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2162025307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/3.hmac_burst_wr.1222789074 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 895620000 ps |
| CPU time | 5.06 seconds |
| Started | Oct 09 07:39:05 AM UTC 24 |
| Finished | Oct 09 07:39:12 AM UTC 24 |
| Peak memory | 210444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222789074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1222789074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/3.hmac_datapath_stress.4004615218 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 3607071957 ps |
| CPU time | 662.28 seconds |
| Started | Oct 09 07:39:03 AM UTC 24 |
| Finished | Oct 09 07:50:13 AM UTC 24 |
| Peak memory | 736612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004615218 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.4004615218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/3.hmac_error.1765108022 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 7013588363 ps |
| CPU time | 111.62 seconds |
| Started | Oct 09 07:39:05 AM UTC 24 |
| Finished | Oct 09 07:40:59 AM UTC 24 |
| Peak memory | 210688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765108022 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1765108022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/3.hmac_long_msg.303946560 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 8126780880 ps |
| CPU time | 143.56 seconds |
| Started | Oct 09 07:38:58 AM UTC 24 |
| Finished | Oct 09 07:41:24 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303946560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.303946560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/3.hmac_sec_cm.1510599296 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 70346811 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 07:39:23 AM UTC 24 |
| Finished | Oct 09 07:39:25 AM UTC 24 |
| Peak memory | 239520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510599296 -assert nopostproc +UVM_TESTNAME=hmac_b ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hm ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1510599296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/3.hmac_smoke.239396338 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 288178863 ps |
| CPU time | 3.24 seconds |
| Started | Oct 09 07:38:57 AM UTC 24 |
| Finished | Oct 09 07:39:01 AM UTC 24 |
| Peak memory | 210304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239396338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 3.hmac_smoke.239396338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/3.hmac_stress_all.4065672504 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 29037081835 ps |
| CPU time | 254.07 seconds |
| Started | Oct 09 07:39:19 AM UTC 24 |
| Finished | Oct 09 07:43:37 AM UTC 24 |
| Peak memory | 210472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065672504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.4065672504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/3.hmac_test_hmac256_vectors.304032723 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 7787240904 ps |
| CPU time | 76.83 seconds |
| Started | Oct 09 07:39:15 AM UTC 24 |
| Finished | Oct 09 07:40:33 AM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304032723 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.304032723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_test_hmac256_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/3.hmac_test_hmac384_vectors.2590140588 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 6867965931 ps |
| CPU time | 83.69 seconds |
| Started | Oct 09 07:39:18 AM UTC 24 |
| Finished | Oct 09 07:40:43 AM UTC 24 |
| Peak memory | 210764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590140588 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.2590140588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_test_hmac384_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/3.hmac_test_hmac512_vectors.1231440886 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 11065407750 ps |
| CPU time | 100.19 seconds |
| Started | Oct 09 07:39:19 AM UTC 24 |
| Finished | Oct 09 07:41:02 AM UTC 24 |
| Peak memory | 210472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231440886 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.1231440886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_test_hmac512_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/3.hmac_test_sha256_vectors.2492819043 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 171343429235 ps |
| CPU time | 557.67 seconds |
| Started | Oct 09 07:39:11 AM UTC 24 |
| Finished | Oct 09 07:48:36 AM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492819043 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2492819043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_test_sha256_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/3.hmac_test_sha384_vectors.222707013 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 410930192799 ps |
| CPU time | 2831.81 seconds |
| Started | Oct 09 07:39:12 AM UTC 24 |
| Finished | Oct 09 08:26:59 AM UTC 24 |
| Peak memory | 230484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222707013 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.222707013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_test_sha384_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/3.hmac_test_sha512_vectors.1326097863 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 38023227201 ps |
| CPU time | 2393.57 seconds |
| Started | Oct 09 07:39:13 AM UTC 24 |
| Finished | Oct 09 08:19:36 AM UTC 24 |
| Peak memory | 224624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326097863 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.1326097863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/3.hmac_test_sha512_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/30.hmac_alert_test.502587614 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 15627829 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 07:52:36 AM UTC 24 |
| Finished | Oct 09 07:52:38 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502587614 -assert nopostproc +UVM_TESTNAME=hmac_b ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hm ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.502587614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/30.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/30.hmac_back_pressure.69379458 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1578873833 ps |
| CPU time | 85.42 seconds |
| Started | Oct 09 07:52:07 AM UTC 24 |
| Finished | Oct 09 07:53:35 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69379458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV M_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.69379458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/30.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/30.hmac_burst_wr.916994295 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 6302135967 ps |
| CPU time | 29.53 seconds |
| Started | Oct 09 07:52:18 AM UTC 24 |
| Finished | Oct 09 07:52:49 AM UTC 24 |
| Peak memory | 210408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916994295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.916994295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/30.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/30.hmac_datapath_stress.1111702177 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 2473719952 ps |
| CPU time | 261.56 seconds |
| Started | Oct 09 07:52:15 AM UTC 24 |
| Finished | Oct 09 07:56:41 AM UTC 24 |
| Peak memory | 492728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111702177 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1111702177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/30.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/30.hmac_error.3668252008 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 3438904284 ps |
| CPU time | 169 seconds |
| Started | Oct 09 07:52:19 AM UTC 24 |
| Finished | Oct 09 07:55:11 AM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668252008 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3668252008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/30.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/30.hmac_long_msg.535130820 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 277788079 ps |
| CPU time | 7.99 seconds |
| Started | Oct 09 07:52:05 AM UTC 24 |
| Finished | Oct 09 07:52:14 AM UTC 24 |
| Peak memory | 210300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535130820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.535130820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/30.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/30.hmac_smoke.2170399195 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 74390575 ps |
| CPU time | 1.91 seconds |
| Started | Oct 09 07:52:04 AM UTC 24 |
| Finished | Oct 09 07:52:07 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170399195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2170399195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/30.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/30.hmac_stress_all.787718522 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 7785197499 ps |
| CPU time | 82.74 seconds |
| Started | Oct 09 07:52:24 AM UTC 24 |
| Finished | Oct 09 07:53:50 AM UTC 24 |
| Peak memory | 210468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787718522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.787718522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/30.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/30.hmac_wipe_secret.3986509484 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 657304473 ps |
| CPU time | 13.13 seconds |
| Started | Oct 09 07:52:21 AM UTC 24 |
| Finished | Oct 09 07:52:35 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986509484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3986509484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/30.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/31.hmac_alert_test.4026117035 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 40868302 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 07:53:14 AM UTC 24 |
| Finished | Oct 09 07:53:16 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026117035 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.4026117035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/31.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/31.hmac_back_pressure.2438884256 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1372964701 ps |
| CPU time | 20.63 seconds |
| Started | Oct 09 07:52:50 AM UTC 24 |
| Finished | Oct 09 07:53:12 AM UTC 24 |
| Peak memory | 210564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438884256 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2438884256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/31.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/31.hmac_burst_wr.3555591477 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 9905725896 ps |
| CPU time | 36.57 seconds |
| Started | Oct 09 07:53:00 AM UTC 24 |
| Finished | Oct 09 07:53:38 AM UTC 24 |
| Peak memory | 210448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555591477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3555591477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/31.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/31.hmac_datapath_stress.2794893416 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 20634086602 ps |
| CPU time | 1188.99 seconds |
| Started | Oct 09 07:52:54 AM UTC 24 |
| Finished | Oct 09 08:12:56 AM UTC 24 |
| Peak memory | 718108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794893416 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2794893416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/31.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/31.hmac_error.403627967 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 643098636 ps |
| CPU time | 13.41 seconds |
| Started | Oct 09 07:53:00 AM UTC 24 |
| Finished | Oct 09 07:53:15 AM UTC 24 |
| Peak memory | 210540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403627967 -assert nopostproc +UVM_TESTNAME=hma c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.403627967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/31.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/31.hmac_long_msg.48234750 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 18825372980 ps |
| CPU time | 65.8 seconds |
| Started | Oct 09 07:52:49 AM UTC 24 |
| Finished | Oct 09 07:53:56 AM UTC 24 |
| Peak memory | 210404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48234750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac _long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.48234750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/31.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/31.hmac_smoke.1914502237 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 355030737 ps |
| CPU time | 7.86 seconds |
| Started | Oct 09 07:52:39 AM UTC 24 |
| Finished | Oct 09 07:52:48 AM UTC 24 |
| Peak memory | 210356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914502237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1914502237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/31.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/31.hmac_stress_all.2989867288 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 4461038297 ps |
| CPU time | 82.97 seconds |
| Started | Oct 09 07:53:14 AM UTC 24 |
| Finished | Oct 09 07:54:39 AM UTC 24 |
| Peak memory | 210472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989867288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2989867288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/31.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/31.hmac_wipe_secret.2908822465 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 11075590773 ps |
| CPU time | 76.33 seconds |
| Started | Oct 09 07:53:12 AM UTC 24 |
| Finished | Oct 09 07:54:30 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908822465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2908822465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/31.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/32.hmac_alert_test.2383285941 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 12919778 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 07:53:43 AM UTC 24 |
| Finished | Oct 09 07:53:45 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383285941 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2383285941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/32.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/32.hmac_back_pressure.4107045514 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 3890860164 ps |
| CPU time | 67.02 seconds |
| Started | Oct 09 07:53:18 AM UTC 24 |
| Finished | Oct 09 07:54:27 AM UTC 24 |
| Peak memory | 210468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107045514 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.4107045514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/32.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/32.hmac_burst_wr.4098970815 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 12420326206 ps |
| CPU time | 59.41 seconds |
| Started | Oct 09 07:53:31 AM UTC 24 |
| Finished | Oct 09 07:54:32 AM UTC 24 |
| Peak memory | 210408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098970815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.4098970815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/32.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/32.hmac_datapath_stress.2359086230 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 11754194544 ps |
| CPU time | 530.82 seconds |
| Started | Oct 09 07:53:24 AM UTC 24 |
| Finished | Oct 09 08:02:21 AM UTC 24 |
| Peak memory | 683456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359086230 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2359086230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/32.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/32.hmac_error.3922333109 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 4992083989 ps |
| CPU time | 84.78 seconds |
| Started | Oct 09 07:53:37 AM UTC 24 |
| Finished | Oct 09 07:55:04 AM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922333109 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3922333109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/32.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/32.hmac_long_msg.2181938631 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 11787225950 ps |
| CPU time | 183.67 seconds |
| Started | Oct 09 07:53:18 AM UTC 24 |
| Finished | Oct 09 07:56:25 AM UTC 24 |
| Peak memory | 210372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181938631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2181938631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/32.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/32.hmac_smoke.1883672571 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1225133290 ps |
| CPU time | 12.51 seconds |
| Started | Oct 09 07:53:16 AM UTC 24 |
| Finished | Oct 09 07:53:30 AM UTC 24 |
| Peak memory | 210340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883672571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1883672571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/32.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/32.hmac_stress_all.545160523 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 14471291512 ps |
| CPU time | 169.65 seconds |
| Started | Oct 09 07:53:40 AM UTC 24 |
| Finished | Oct 09 07:56:32 AM UTC 24 |
| Peak memory | 210356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545160523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.545160523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/32.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/32.hmac_wipe_secret.4106448571 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 784752984 ps |
| CPU time | 9.82 seconds |
| Started | Oct 09 07:53:37 AM UTC 24 |
| Finished | Oct 09 07:53:48 AM UTC 24 |
| Peak memory | 210236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106448571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.4106448571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/32.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/33.hmac_alert_test.2861077794 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 29950727 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 07:54:30 AM UTC 24 |
| Finished | Oct 09 07:54:32 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861077794 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2861077794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/33.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/33.hmac_back_pressure.703474379 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 2806726966 ps |
| CPU time | 97.28 seconds |
| Started | Oct 09 07:53:51 AM UTC 24 |
| Finished | Oct 09 07:55:30 AM UTC 24 |
| Peak memory | 210408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703474379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.703474379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/33.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/33.hmac_burst_wr.748166656 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 2477347750 ps |
| CPU time | 46.46 seconds |
| Started | Oct 09 07:53:57 AM UTC 24 |
| Finished | Oct 09 07:54:45 AM UTC 24 |
| Peak memory | 210384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748166656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.748166656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/33.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/33.hmac_datapath_stress.1833112469 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 5013297324 ps |
| CPU time | 1131.38 seconds |
| Started | Oct 09 07:53:54 AM UTC 24 |
| Finished | Oct 09 08:12:58 AM UTC 24 |
| Peak memory | 767524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833112469 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1833112469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/33.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/33.hmac_error.884134022 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 146598703 ps |
| CPU time | 4.83 seconds |
| Started | Oct 09 07:54:12 AM UTC 24 |
| Finished | Oct 09 07:54:18 AM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884134022 -assert nopostproc +UVM_TESTNAME=hma c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.884134022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/33.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/33.hmac_long_msg.114247666 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4574167867 ps |
| CPU time | 100.65 seconds |
| Started | Oct 09 07:53:49 AM UTC 24 |
| Finished | Oct 09 07:55:32 AM UTC 24 |
| Peak memory | 210448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114247666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.114247666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/33.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/33.hmac_smoke.3540389637 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 255440376 ps |
| CPU time | 5.6 seconds |
| Started | Oct 09 07:53:46 AM UTC 24 |
| Finished | Oct 09 07:53:53 AM UTC 24 |
| Peak memory | 210608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540389637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3540389637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/33.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/33.hmac_stress_all.1859605155 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 11602032416 ps |
| CPU time | 226.57 seconds |
| Started | Oct 09 07:54:20 AM UTC 24 |
| Finished | Oct 09 07:58:10 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859605155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1859605155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/33.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/33.hmac_wipe_secret.3232028433 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 5904028168 ps |
| CPU time | 125.44 seconds |
| Started | Oct 09 07:54:20 AM UTC 24 |
| Finished | Oct 09 07:56:28 AM UTC 24 |
| Peak memory | 210472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232028433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3232028433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/33.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/34.hmac_alert_test.4235003750 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 23040605 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 07:54:46 AM UTC 24 |
| Finished | Oct 09 07:54:48 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235003750 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.4235003750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/34.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/34.hmac_back_pressure.2195888394 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 1375170845 ps |
| CPU time | 98.5 seconds |
| Started | Oct 09 07:54:33 AM UTC 24 |
| Finished | Oct 09 07:56:14 AM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195888394 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2195888394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/34.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/34.hmac_burst_wr.988866471 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 5744479992 ps |
| CPU time | 67.91 seconds |
| Started | Oct 09 07:54:36 AM UTC 24 |
| Finished | Oct 09 07:55:46 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988866471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.988866471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/34.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/34.hmac_datapath_stress.4176679045 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 6712380367 ps |
| CPU time | 1557.01 seconds |
| Started | Oct 09 07:54:33 AM UTC 24 |
| Finished | Oct 09 08:20:48 AM UTC 24 |
| Peak memory | 787632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176679045 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.4176679045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/34.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/34.hmac_error.4039768835 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 4799290942 ps |
| CPU time | 108.54 seconds |
| Started | Oct 09 07:54:36 AM UTC 24 |
| Finished | Oct 09 07:56:27 AM UTC 24 |
| Peak memory | 210304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039768835 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.4039768835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/34.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/34.hmac_long_msg.4168576123 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 30328650 ps |
| CPU time | 1.32 seconds |
| Started | Oct 09 07:54:32 AM UTC 24 |
| Finished | Oct 09 07:54:34 AM UTC 24 |
| Peak memory | 209132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168576123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.4168576123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/34.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/34.hmac_smoke.2155735187 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 10115096532 ps |
| CPU time | 14.7 seconds |
| Started | Oct 09 07:54:30 AM UTC 24 |
| Finished | Oct 09 07:54:46 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155735187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2155735187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/34.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/34.hmac_stress_all.2250384247 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 2914779705 ps |
| CPU time | 221.46 seconds |
| Started | Oct 09 07:54:40 AM UTC 24 |
| Finished | Oct 09 07:58:25 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250384247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2250384247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/34.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/34.hmac_wipe_secret.2970145312 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 140262110538 ps |
| CPU time | 138.9 seconds |
| Started | Oct 09 07:54:40 AM UTC 24 |
| Finished | Oct 09 07:57:02 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970145312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2970145312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/34.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/35.hmac_alert_test.2338127866 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 15893011 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 07:55:24 AM UTC 24 |
| Finished | Oct 09 07:55:26 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338127866 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2338127866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/35.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/35.hmac_back_pressure.1957649020 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 647217361 ps |
| CPU time | 24.6 seconds |
| Started | Oct 09 07:54:49 AM UTC 24 |
| Finished | Oct 09 07:55:15 AM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957649020 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1957649020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/35.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/35.hmac_burst_wr.67273564 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 1543769529 ps |
| CPU time | 30.48 seconds |
| Started | Oct 09 07:55:07 AM UTC 24 |
| Finished | Oct 09 07:55:39 AM UTC 24 |
| Peak memory | 210300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67273564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac _burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.67273564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/35.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/35.hmac_datapath_stress.3438502079 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 3315805657 ps |
| CPU time | 133.48 seconds |
| Started | Oct 09 07:55:04 AM UTC 24 |
| Finished | Oct 09 07:57:20 AM UTC 24 |
| Peak memory | 349292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438502079 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3438502079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/35.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/35.hmac_error.3130144646 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 15015748836 ps |
| CPU time | 119.5 seconds |
| Started | Oct 09 07:55:07 AM UTC 24 |
| Finished | Oct 09 07:57:09 AM UTC 24 |
| Peak memory | 210424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130144646 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3130144646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/35.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/35.hmac_long_msg.3196573695 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 34391507434 ps |
| CPU time | 188.51 seconds |
| Started | Oct 09 07:54:47 AM UTC 24 |
| Finished | Oct 09 07:57:59 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196573695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3196573695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/35.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/35.hmac_smoke.2217132600 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 763149463 ps |
| CPU time | 15.01 seconds |
| Started | Oct 09 07:54:47 AM UTC 24 |
| Finished | Oct 09 07:55:03 AM UTC 24 |
| Peak memory | 210416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217132600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2217132600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/35.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/35.hmac_stress_all.2660749914 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 3798287627 ps |
| CPU time | 116.26 seconds |
| Started | Oct 09 07:55:16 AM UTC 24 |
| Finished | Oct 09 07:57:15 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660749914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2660749914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/35.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/35.hmac_wipe_secret.3601165800 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 17681755587 ps |
| CPU time | 122.45 seconds |
| Started | Oct 09 07:55:13 AM UTC 24 |
| Finished | Oct 09 07:57:18 AM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601165800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3601165800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/35.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/36.hmac_alert_test.3683438324 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 43546444 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 07:56:15 AM UTC 24 |
| Finished | Oct 09 07:56:17 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683438324 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3683438324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/36.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/36.hmac_back_pressure.1487607674 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 70331585 ps |
| CPU time | 3.03 seconds |
| Started | Oct 09 07:55:34 AM UTC 24 |
| Finished | Oct 09 07:55:38 AM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487607674 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1487607674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/36.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/36.hmac_burst_wr.2013183513 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 18718837733 ps |
| CPU time | 80.41 seconds |
| Started | Oct 09 07:55:40 AM UTC 24 |
| Finished | Oct 09 07:57:03 AM UTC 24 |
| Peak memory | 210544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013183513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2013183513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/36.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/36.hmac_datapath_stress.3262218306 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 6952482020 ps |
| CPU time | 306.96 seconds |
| Started | Oct 09 07:55:39 AM UTC 24 |
| Finished | Oct 09 08:00:50 AM UTC 24 |
| Peak memory | 685296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262218306 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3262218306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/36.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/36.hmac_error.1112160789 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 796024182 ps |
| CPU time | 62.08 seconds |
| Started | Oct 09 07:55:47 AM UTC 24 |
| Finished | Oct 09 07:56:51 AM UTC 24 |
| Peak memory | 209468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112160789 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1112160789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/36.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/36.hmac_long_msg.980419785 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 9022487836 ps |
| CPU time | 140.04 seconds |
| Started | Oct 09 07:55:32 AM UTC 24 |
| Finished | Oct 09 07:57:55 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980419785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.980419785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/36.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/36.hmac_smoke.4113869266 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 1174012318 ps |
| CPU time | 20.03 seconds |
| Started | Oct 09 07:55:27 AM UTC 24 |
| Finished | Oct 09 07:55:49 AM UTC 24 |
| Peak memory | 210328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113869266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.4113869266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/36.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/36.hmac_stress_all.2268972707 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 57646394768 ps |
| CPU time | 1465.57 seconds |
| Started | Oct 09 07:55:49 AM UTC 24 |
| Finished | Oct 09 08:20:31 AM UTC 24 |
| Peak memory | 756904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268972707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2268972707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/36.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/36.hmac_wipe_secret.1165221347 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 3726944422 ps |
| CPU time | 49.59 seconds |
| Started | Oct 09 07:55:47 AM UTC 24 |
| Finished | Oct 09 07:56:38 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165221347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1165221347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/36.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/37.hmac_alert_test.2416674270 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 12797596 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 07:56:43 AM UTC 24 |
| Finished | Oct 09 07:56:45 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416674270 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2416674270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/37.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/37.hmac_back_pressure.1826523480 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 614618520 ps |
| CPU time | 43.85 seconds |
| Started | Oct 09 07:56:26 AM UTC 24 |
| Finished | Oct 09 07:57:12 AM UTC 24 |
| Peak memory | 210416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826523480 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1826523480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/37.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/37.hmac_burst_wr.2456987312 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 109425064 ps |
| CPU time | 8.09 seconds |
| Started | Oct 09 07:56:30 AM UTC 24 |
| Finished | Oct 09 07:56:39 AM UTC 24 |
| Peak memory | 210508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456987312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2456987312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/37.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/37.hmac_datapath_stress.2133820119 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 14342230032 ps |
| CPU time | 1554.1 seconds |
| Started | Oct 09 07:56:29 AM UTC 24 |
| Finished | Oct 09 08:22:41 AM UTC 24 |
| Peak memory | 795960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133820119 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2133820119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/37.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/37.hmac_error.1740133483 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 7151615378 ps |
| CPU time | 91.15 seconds |
| Started | Oct 09 07:56:35 AM UTC 24 |
| Finished | Oct 09 07:58:08 AM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740133483 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1740133483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/37.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/37.hmac_long_msg.516080635 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 29776417756 ps |
| CPU time | 148.35 seconds |
| Started | Oct 09 07:56:23 AM UTC 24 |
| Finished | Oct 09 07:58:54 AM UTC 24 |
| Peak memory | 210448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516080635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.516080635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/37.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/37.hmac_smoke.3118558382 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 37836636 ps |
| CPU time | 2.51 seconds |
| Started | Oct 09 07:56:19 AM UTC 24 |
| Finished | Oct 09 07:56:22 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118558382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3118558382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/37.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/37.hmac_stress_all.3184047053 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 404504772046 ps |
| CPU time | 1012.73 seconds |
| Started | Oct 09 07:56:39 AM UTC 24 |
| Finished | Oct 09 08:13:44 AM UTC 24 |
| Peak memory | 711872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184047053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3184047053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/37.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/37.hmac_wipe_secret.2113360503 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 58741372 ps |
| CPU time | 4.9 seconds |
| Started | Oct 09 07:56:39 AM UTC 24 |
| Finished | Oct 09 07:56:45 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113360503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2113360503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/37.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/38.hmac_alert_test.1568858029 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 75763174 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 07:57:13 AM UTC 24 |
| Finished | Oct 09 07:57:15 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568858029 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1568858029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/38.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/38.hmac_back_pressure.3587040305 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 2682740432 ps |
| CPU time | 101.42 seconds |
| Started | Oct 09 07:56:47 AM UTC 24 |
| Finished | Oct 09 07:58:30 AM UTC 24 |
| Peak memory | 210540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587040305 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3587040305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/38.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/38.hmac_burst_wr.188914310 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 3492007652 ps |
| CPU time | 19.81 seconds |
| Started | Oct 09 07:56:52 AM UTC 24 |
| Finished | Oct 09 07:57:13 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188914310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.188914310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/38.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/38.hmac_datapath_stress.2338258404 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1511875861 ps |
| CPU time | 53.11 seconds |
| Started | Oct 09 07:56:52 AM UTC 24 |
| Finished | Oct 09 07:57:47 AM UTC 24 |
| Peak memory | 346788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338258404 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2338258404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/38.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/38.hmac_error.22073002 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 9506260973 ps |
| CPU time | 188.23 seconds |
| Started | Oct 09 07:57:03 AM UTC 24 |
| Finished | Oct 09 08:00:14 AM UTC 24 |
| Peak memory | 210624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22073002 -assert nopostproc +UVM_TESTNAME=hmac _base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.22073002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/38.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/38.hmac_long_msg.1098760732 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 12081525100 ps |
| CPU time | 144.62 seconds |
| Started | Oct 09 07:56:47 AM UTC 24 |
| Finished | Oct 09 07:59:14 AM UTC 24 |
| Peak memory | 219216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098760732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1098760732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/38.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/38.hmac_smoke.413558077 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 1610521302 ps |
| CPU time | 6.68 seconds |
| Started | Oct 09 07:56:43 AM UTC 24 |
| Finished | Oct 09 07:56:51 AM UTC 24 |
| Peak memory | 210484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413558077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 38.hmac_smoke.413558077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/38.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/38.hmac_stress_all.4007822232 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 158898366242 ps |
| CPU time | 4080.6 seconds |
| Started | Oct 09 07:57:10 AM UTC 24 |
| Finished | Oct 09 09:05:57 AM UTC 24 |
| Peak memory | 791984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007822232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.4007822232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/38.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/38.hmac_wipe_secret.1365370308 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 1673751796 ps |
| CPU time | 109.58 seconds |
| Started | Oct 09 07:57:03 AM UTC 24 |
| Finished | Oct 09 07:58:55 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365370308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1365370308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/38.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/39.hmac_alert_test.2221174423 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 42615937 ps |
| CPU time | 0.96 seconds |
| Started | Oct 09 07:58:01 AM UTC 24 |
| Finished | Oct 09 07:58:03 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221174423 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2221174423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/39.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/39.hmac_back_pressure.1860379735 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 4823888519 ps |
| CPU time | 82.79 seconds |
| Started | Oct 09 07:57:16 AM UTC 24 |
| Finished | Oct 09 07:58:41 AM UTC 24 |
| Peak memory | 218976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860379735 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1860379735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/39.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/39.hmac_burst_wr.1794381846 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 6801098390 ps |
| CPU time | 64.58 seconds |
| Started | Oct 09 07:57:20 AM UTC 24 |
| Finished | Oct 09 07:58:26 AM UTC 24 |
| Peak memory | 210464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794381846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1794381846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/39.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/39.hmac_datapath_stress.2487207430 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 12439687913 ps |
| CPU time | 1258.88 seconds |
| Started | Oct 09 07:57:20 AM UTC 24 |
| Finished | Oct 09 08:18:31 AM UTC 24 |
| Peak memory | 781536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487207430 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2487207430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/39.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/39.hmac_error.764423667 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 9297378477 ps |
| CPU time | 50.06 seconds |
| Started | Oct 09 07:57:21 AM UTC 24 |
| Finished | Oct 09 07:58:13 AM UTC 24 |
| Peak memory | 210632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764423667 -assert nopostproc +UVM_TESTNAME=hma c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.764423667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/39.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/39.hmac_long_msg.2581025860 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 3862821508 ps |
| CPU time | 125.11 seconds |
| Started | Oct 09 07:57:16 AM UTC 24 |
| Finished | Oct 09 07:59:23 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581025860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2581025860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/39.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/39.hmac_smoke.1691266697 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 83360522 ps |
| CPU time | 3.09 seconds |
| Started | Oct 09 07:57:14 AM UTC 24 |
| Finished | Oct 09 07:57:18 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691266697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1691266697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/39.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/39.hmac_stress_all.3618542031 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2691521325 ps |
| CPU time | 157.96 seconds |
| Started | Oct 09 07:57:57 AM UTC 24 |
| Finished | Oct 09 08:00:38 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618542031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3618542031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/39.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/39.hmac_wipe_secret.3613740625 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 6901625292 ps |
| CPU time | 100.35 seconds |
| Started | Oct 09 07:57:48 AM UTC 24 |
| Finished | Oct 09 07:59:30 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613740625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3613740625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/39.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/4.hmac_alert_test.2437398229 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 105220168 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 07:40:07 AM UTC 24 |
| Finished | Oct 09 07:40:09 AM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437398229 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2437398229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/4.hmac_back_pressure.356273800 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 200526733 ps |
| CPU time | 15.34 seconds |
| Started | Oct 09 07:39:27 AM UTC 24 |
| Finished | Oct 09 07:39:44 AM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356273800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.356273800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/4.hmac_burst_wr.719477671 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 579792298 ps |
| CPU time | 40.92 seconds |
| Started | Oct 09 07:39:34 AM UTC 24 |
| Finished | Oct 09 07:40:17 AM UTC 24 |
| Peak memory | 210304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719477671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.719477671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/4.hmac_datapath_stress.1311960574 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1011664510 ps |
| CPU time | 170.22 seconds |
| Started | Oct 09 07:39:30 AM UTC 24 |
| Finished | Oct 09 07:42:23 AM UTC 24 |
| Peak memory | 662832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311960574 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1311960574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/4.hmac_error.3926626402 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 24460858754 ps |
| CPU time | 215.98 seconds |
| Started | Oct 09 07:39:34 AM UTC 24 |
| Finished | Oct 09 07:43:14 AM UTC 24 |
| Peak memory | 210628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926626402 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3926626402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/4.hmac_long_msg.402053224 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 2509899158 ps |
| CPU time | 144.54 seconds |
| Started | Oct 09 07:39:27 AM UTC 24 |
| Finished | Oct 09 07:41:55 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402053224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.402053224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/4.hmac_sec_cm.1280375811 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 278326937 ps |
| CPU time | 1.31 seconds |
| Started | Oct 09 07:40:04 AM UTC 24 |
| Finished | Oct 09 07:40:07 AM UTC 24 |
| Peak memory | 239584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280375811 -assert nopostproc +UVM_TESTNAME=hmac_b ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hm ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1280375811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/4.hmac_stress_all.4199720138 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 13499207578 ps |
| CPU time | 1196.1 seconds |
| Started | Oct 09 07:39:58 AM UTC 24 |
| Finished | Oct 09 08:00:08 AM UTC 24 |
| Peak memory | 521408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199720138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.4199720138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/4.hmac_test_hmac256_vectors.4284530782 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 17459409743 ps |
| CPU time | 58.37 seconds |
| Started | Oct 09 07:39:44 AM UTC 24 |
| Finished | Oct 09 07:40:44 AM UTC 24 |
| Peak memory | 210460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284530782 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.4284530782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_test_hmac256_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/4.hmac_test_hmac384_vectors.4018756081 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 9446647268 ps |
| CPU time | 125.92 seconds |
| Started | Oct 09 07:39:45 AM UTC 24 |
| Finished | Oct 09 07:41:53 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018756081 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.4018756081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_test_hmac384_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/4.hmac_test_hmac512_vectors.396902654 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 55236202192 ps |
| CPU time | 84.55 seconds |
| Started | Oct 09 07:39:57 AM UTC 24 |
| Finished | Oct 09 07:41:24 AM UTC 24 |
| Peak memory | 210552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396902654 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.396902654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_test_hmac512_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/4.hmac_test_sha256_vectors.2038818700 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 17166253348 ps |
| CPU time | 609.1 seconds |
| Started | Oct 09 07:39:36 AM UTC 24 |
| Finished | Oct 09 07:49:53 AM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038818700 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2038818700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_test_sha256_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/4.hmac_test_sha384_vectors.1935106323 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 823131577236 ps |
| CPU time | 2889.35 seconds |
| Started | Oct 09 07:39:37 AM UTC 24 |
| Finished | Oct 09 08:28:20 AM UTC 24 |
| Peak memory | 224232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935106323 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.1935106323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_test_sha384_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/4.hmac_test_sha512_vectors.3295986289 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 84995703081 ps |
| CPU time | 2446.75 seconds |
| Started | Oct 09 07:39:38 AM UTC 24 |
| Finished | Oct 09 08:20:53 AM UTC 24 |
| Peak memory | 230740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295986289 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.3295986289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_test_sha512_vectors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/4.hmac_wipe_secret.3917435504 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4367074984 ps |
| CPU time | 35.44 seconds |
| Started | Oct 09 07:39:36 AM UTC 24 |
| Finished | Oct 09 07:40:13 AM UTC 24 |
| Peak memory | 210400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917435504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3917435504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/4.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/40.hmac_alert_test.1029715997 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 25261750 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 07:58:27 AM UTC 24 |
| Finished | Oct 09 07:58:29 AM UTC 24 |
| Peak memory | 207216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029715997 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1029715997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/40.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/40.hmac_back_pressure.528536331 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 127769278 ps |
| CPU time | 4.92 seconds |
| Started | Oct 09 07:58:11 AM UTC 24 |
| Finished | Oct 09 07:58:17 AM UTC 24 |
| Peak memory | 210300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528536331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.528536331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/40.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/40.hmac_burst_wr.2386661511 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 1853584628 ps |
| CPU time | 37.65 seconds |
| Started | Oct 09 07:58:14 AM UTC 24 |
| Finished | Oct 09 07:58:53 AM UTC 24 |
| Peak memory | 210244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386661511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2386661511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/40.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/40.hmac_datapath_stress.1045324031 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2408299500 ps |
| CPU time | 459.83 seconds |
| Started | Oct 09 07:58:14 AM UTC 24 |
| Finished | Oct 09 08:05:59 AM UTC 24 |
| Peak memory | 746944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045324031 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1045324031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/40.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/40.hmac_error.3024717990 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 22843948388 ps |
| CPU time | 176.79 seconds |
| Started | Oct 09 07:58:17 AM UTC 24 |
| Finished | Oct 09 08:01:17 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024717990 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3024717990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/40.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/40.hmac_long_msg.1663185771 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 620612989 ps |
| CPU time | 8.06 seconds |
| Started | Oct 09 07:58:09 AM UTC 24 |
| Finished | Oct 09 07:58:18 AM UTC 24 |
| Peak memory | 210272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663185771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1663185771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/40.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/40.hmac_smoke.2375065632 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 639581733 ps |
| CPU time | 11.08 seconds |
| Started | Oct 09 07:58:04 AM UTC 24 |
| Finished | Oct 09 07:58:16 AM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375065632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2375065632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/40.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/40.hmac_stress_all.1255173150 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 20107598041 ps |
| CPU time | 1800.58 seconds |
| Started | Oct 09 07:58:19 AM UTC 24 |
| Finished | Oct 09 08:28:38 AM UTC 24 |
| Peak memory | 728348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255173150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1255173150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/40.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/40.hmac_wipe_secret.2742397019 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 8758693683 ps |
| CPU time | 83.5 seconds |
| Started | Oct 09 07:58:18 AM UTC 24 |
| Finished | Oct 09 07:59:44 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742397019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2742397019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/40.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/41.hmac_alert_test.98339113 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 43810456 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 07:59:11 AM UTC 24 |
| Finished | Oct 09 07:59:13 AM UTC 24 |
| Peak memory | 207208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98339113 -assert nopostproc +UVM_TESTNAME=hmac_ba se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.98339113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/41.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/41.hmac_back_pressure.1365770810 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 706380461 ps |
| CPU time | 43.7 seconds |
| Started | Oct 09 07:58:33 AM UTC 24 |
| Finished | Oct 09 07:59:18 AM UTC 24 |
| Peak memory | 210304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365770810 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1365770810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/41.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/41.hmac_burst_wr.1368806597 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 4503665923 ps |
| CPU time | 67.5 seconds |
| Started | Oct 09 07:58:43 AM UTC 24 |
| Finished | Oct 09 07:59:52 AM UTC 24 |
| Peak memory | 218976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368806597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1368806597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/41.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/41.hmac_datapath_stress.3175485088 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 21973187505 ps |
| CPU time | 1116.83 seconds |
| Started | Oct 09 07:58:35 AM UTC 24 |
| Finished | Oct 09 08:17:25 AM UTC 24 |
| Peak memory | 703736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175485088 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3175485088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/41.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/41.hmac_error.1340626775 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 41382316191 ps |
| CPU time | 296.81 seconds |
| Started | Oct 09 07:58:54 AM UTC 24 |
| Finished | Oct 09 08:03:55 AM UTC 24 |
| Peak memory | 210360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340626775 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1340626775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/41.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/41.hmac_long_msg.2775792308 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 5475807139 ps |
| CPU time | 186.4 seconds |
| Started | Oct 09 07:58:31 AM UTC 24 |
| Finished | Oct 09 08:01:40 AM UTC 24 |
| Peak memory | 210468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775792308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2775792308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/41.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/41.hmac_smoke.3895022488 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 494915095 ps |
| CPU time | 5.06 seconds |
| Started | Oct 09 07:58:27 AM UTC 24 |
| Finished | Oct 09 07:58:34 AM UTC 24 |
| Peak memory | 210424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895022488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3895022488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/41.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/41.hmac_stress_all.54528169 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 296247180487 ps |
| CPU time | 1364.78 seconds |
| Started | Oct 09 07:58:57 AM UTC 24 |
| Finished | Oct 09 08:21:57 AM UTC 24 |
| Peak memory | 219296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54528169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.54528169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/41.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/41.hmac_wipe_secret.172192058 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 1923883608 ps |
| CPU time | 12.6 seconds |
| Started | Oct 09 07:58:56 AM UTC 24 |
| Finished | Oct 09 07:59:10 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172192058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.172192058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/41.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/42.hmac_alert_test.3251290039 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 15137800 ps |
| CPU time | 0.95 seconds |
| Started | Oct 09 07:59:32 AM UTC 24 |
| Finished | Oct 09 07:59:34 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251290039 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3251290039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/42.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/42.hmac_back_pressure.918194107 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 959457116 ps |
| CPU time | 14.3 seconds |
| Started | Oct 09 07:59:15 AM UTC 24 |
| Finished | Oct 09 07:59:31 AM UTC 24 |
| Peak memory | 210448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918194107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.918194107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/42.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/42.hmac_burst_wr.941562610 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 16881704941 ps |
| CPU time | 78.85 seconds |
| Started | Oct 09 07:59:20 AM UTC 24 |
| Finished | Oct 09 08:00:40 AM UTC 24 |
| Peak memory | 210676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941562610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.941562610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/42.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/42.hmac_datapath_stress.2803810249 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 18602891955 ps |
| CPU time | 1008.74 seconds |
| Started | Oct 09 07:59:20 AM UTC 24 |
| Finished | Oct 09 08:16:19 AM UTC 24 |
| Peak memory | 785688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803810249 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2803810249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/42.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/42.hmac_error.2761715222 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1054626966 ps |
| CPU time | 29.6 seconds |
| Started | Oct 09 07:59:25 AM UTC 24 |
| Finished | Oct 09 07:59:56 AM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761715222 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2761715222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/42.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/42.hmac_long_msg.2854742544 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 21546753249 ps |
| CPU time | 114.59 seconds |
| Started | Oct 09 07:59:15 AM UTC 24 |
| Finished | Oct 09 08:01:12 AM UTC 24 |
| Peak memory | 210732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854742544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2854742544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/42.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/42.hmac_smoke.795728571 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1280240514 ps |
| CPU time | 10.77 seconds |
| Started | Oct 09 07:59:15 AM UTC 24 |
| Finished | Oct 09 07:59:27 AM UTC 24 |
| Peak memory | 210344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795728571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 42.hmac_smoke.795728571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/42.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/42.hmac_stress_all.1100247432 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 69625441668 ps |
| CPU time | 5522.35 seconds |
| Started | Oct 09 07:59:32 AM UTC 24 |
| Finished | Oct 09 09:32:35 AM UTC 24 |
| Peak memory | 861716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100247432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1100247432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/42.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/42.hmac_wipe_secret.253983388 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 9036820365 ps |
| CPU time | 110.36 seconds |
| Started | Oct 09 07:59:28 AM UTC 24 |
| Finished | Oct 09 08:01:20 AM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253983388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.253983388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/42.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/43.hmac_alert_test.4173993083 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 39722746 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 08:00:40 AM UTC 24 |
| Finished | Oct 09 08:00:42 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173993083 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.4173993083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/43.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/43.hmac_back_pressure.1707881694 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1236517050 ps |
| CPU time | 76.21 seconds |
| Started | Oct 09 07:59:45 AM UTC 24 |
| Finished | Oct 09 08:01:03 AM UTC 24 |
| Peak memory | 210296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707881694 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1707881694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/43.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/43.hmac_burst_wr.3966701955 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 3282943649 ps |
| CPU time | 40.82 seconds |
| Started | Oct 09 07:59:57 AM UTC 24 |
| Finished | Oct 09 08:00:41 AM UTC 24 |
| Peak memory | 210416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966701955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3966701955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/43.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/43.hmac_datapath_stress.439923216 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 10920787344 ps |
| CPU time | 1128.43 seconds |
| Started | Oct 09 07:59:53 AM UTC 24 |
| Finished | Oct 09 08:18:55 AM UTC 24 |
| Peak memory | 713960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439923216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.439923216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/43.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/43.hmac_error.1032722223 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 81997106713 ps |
| CPU time | 275.3 seconds |
| Started | Oct 09 08:00:14 AM UTC 24 |
| Finished | Oct 09 08:04:53 AM UTC 24 |
| Peak memory | 210364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032722223 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1032722223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/43.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/43.hmac_long_msg.1062369984 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 34217590190 ps |
| CPU time | 110.96 seconds |
| Started | Oct 09 07:59:39 AM UTC 24 |
| Finished | Oct 09 08:01:32 AM UTC 24 |
| Peak memory | 210540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062369984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1062369984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/43.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/43.hmac_smoke.398046818 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 16612526 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 07:59:35 AM UTC 24 |
| Finished | Oct 09 07:59:38 AM UTC 24 |
| Peak memory | 208680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398046818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 43.hmac_smoke.398046818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/43.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/43.hmac_stress_all.2684924882 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 25943326204 ps |
| CPU time | 110.8 seconds |
| Started | Oct 09 08:00:27 AM UTC 24 |
| Finished | Oct 09 08:02:20 AM UTC 24 |
| Peak memory | 210452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684924882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2684924882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/43.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/43.hmac_wipe_secret.2550776732 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 6475775334 ps |
| CPU time | 73.91 seconds |
| Started | Oct 09 08:00:16 AM UTC 24 |
| Finished | Oct 09 08:01:32 AM UTC 24 |
| Peak memory | 210464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550776732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2550776732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/43.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/44.hmac_alert_test.2112127573 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 34661932 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 08:01:18 AM UTC 24 |
| Finished | Oct 09 08:01:20 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112127573 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2112127573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/44.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/44.hmac_back_pressure.1033427416 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 2327858719 ps |
| CPU time | 82.09 seconds |
| Started | Oct 09 08:00:43 AM UTC 24 |
| Finished | Oct 09 08:02:07 AM UTC 24 |
| Peak memory | 210544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033427416 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1033427416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/44.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/44.hmac_burst_wr.3195033270 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 466274841 ps |
| CPU time | 31.21 seconds |
| Started | Oct 09 08:00:56 AM UTC 24 |
| Finished | Oct 09 08:01:28 AM UTC 24 |
| Peak memory | 210448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195033270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3195033270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/44.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/44.hmac_datapath_stress.4285422474 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 5260855523 ps |
| CPU time | 1025.85 seconds |
| Started | Oct 09 08:00:52 AM UTC 24 |
| Finished | Oct 09 08:18:10 AM UTC 24 |
| Peak memory | 718136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285422474 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.4285422474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/44.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/44.hmac_error.1696552367 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 6007864981 ps |
| CPU time | 99.31 seconds |
| Started | Oct 09 08:00:59 AM UTC 24 |
| Finished | Oct 09 08:02:40 AM UTC 24 |
| Peak memory | 210688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696552367 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1696552367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/44.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/44.hmac_long_msg.3215031612 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 30182285027 ps |
| CPU time | 107.96 seconds |
| Started | Oct 09 08:00:42 AM UTC 24 |
| Finished | Oct 09 08:02:32 AM UTC 24 |
| Peak memory | 227132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215031612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3215031612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/44.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/44.hmac_smoke.1571921460 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 993795046 ps |
| CPU time | 14.96 seconds |
| Started | Oct 09 08:00:42 AM UTC 24 |
| Finished | Oct 09 08:00:58 AM UTC 24 |
| Peak memory | 210552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571921460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1571921460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/44.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/44.hmac_stress_all.2449567593 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 6433324456 ps |
| CPU time | 371.37 seconds |
| Started | Oct 09 08:01:13 AM UTC 24 |
| Finished | Oct 09 08:07:30 AM UTC 24 |
| Peak memory | 221124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449567593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2449567593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/44.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/44.hmac_wipe_secret.2180858147 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 6223474758 ps |
| CPU time | 103.07 seconds |
| Started | Oct 09 08:01:05 AM UTC 24 |
| Finished | Oct 09 08:02:50 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180858147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2180858147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/44.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/45.hmac_alert_test.4157786560 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 14071603 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 08:01:49 AM UTC 24 |
| Finished | Oct 09 08:01:51 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157786560 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.4157786560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/45.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/45.hmac_back_pressure.162405444 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 1550200217 ps |
| CPU time | 91.2 seconds |
| Started | Oct 09 08:01:29 AM UTC 24 |
| Finished | Oct 09 08:03:02 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162405444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.162405444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/45.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/45.hmac_burst_wr.742035469 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 4526127017 ps |
| CPU time | 48.77 seconds |
| Started | Oct 09 08:01:33 AM UTC 24 |
| Finished | Oct 09 08:02:24 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742035469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.742035469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/45.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/45.hmac_datapath_stress.4140141287 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 11657477110 ps |
| CPU time | 661.47 seconds |
| Started | Oct 09 08:01:30 AM UTC 24 |
| Finished | Oct 09 08:12:40 AM UTC 24 |
| Peak memory | 718340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140141287 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.4140141287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/45.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/45.hmac_error.3914959938 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 59973777 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 08:01:33 AM UTC 24 |
| Finished | Oct 09 08:01:35 AM UTC 24 |
| Peak memory | 207148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914959938 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3914959938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/45.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/45.hmac_long_msg.893964735 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 4479476303 ps |
| CPU time | 127.41 seconds |
| Started | Oct 09 08:01:22 AM UTC 24 |
| Finished | Oct 09 08:03:32 AM UTC 24 |
| Peak memory | 210468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893964735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.893964735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/45.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/45.hmac_smoke.777877833 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 98521186 ps |
| CPU time | 5.93 seconds |
| Started | Oct 09 08:01:22 AM UTC 24 |
| Finished | Oct 09 08:01:29 AM UTC 24 |
| Peak memory | 210524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777877833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 45.hmac_smoke.777877833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/45.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/45.hmac_stress_all.2553384436 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 298722342329 ps |
| CPU time | 526.69 seconds |
| Started | Oct 09 08:01:43 AM UTC 24 |
| Finished | Oct 09 08:10:36 AM UTC 24 |
| Peak memory | 431356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553384436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2553384436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/45.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/45.hmac_wipe_secret.4209022984 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1792479318 ps |
| CPU time | 9.79 seconds |
| Started | Oct 09 08:01:36 AM UTC 24 |
| Finished | Oct 09 08:01:47 AM UTC 24 |
| Peak memory | 210416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209022984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.4209022984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/45.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/46.hmac_alert_test.1071139729 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 30408901 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 08:02:51 AM UTC 24 |
| Finished | Oct 09 08:02:53 AM UTC 24 |
| Peak memory | 207216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071139729 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1071139729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/46.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/46.hmac_back_pressure.3045762349 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 1895013343 ps |
| CPU time | 112.64 seconds |
| Started | Oct 09 08:02:09 AM UTC 24 |
| Finished | Oct 09 08:04:04 AM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045762349 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3045762349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/46.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/46.hmac_burst_wr.2080128098 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 13209000980 ps |
| CPU time | 81.12 seconds |
| Started | Oct 09 08:02:24 AM UTC 24 |
| Finished | Oct 09 08:03:47 AM UTC 24 |
| Peak memory | 210404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080128098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2080128098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/46.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/46.hmac_datapath_stress.1948810374 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 3338798602 ps |
| CPU time | 591.21 seconds |
| Started | Oct 09 08:02:21 AM UTC 24 |
| Finished | Oct 09 08:12:19 AM UTC 24 |
| Peak memory | 673036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948810374 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1948810374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/46.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/46.hmac_error.1900736112 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 28039870765 ps |
| CPU time | 140.57 seconds |
| Started | Oct 09 08:02:25 AM UTC 24 |
| Finished | Oct 09 08:04:48 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900736112 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1900736112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/46.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/46.hmac_long_msg.2505241144 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 5973539028 ps |
| CPU time | 98.44 seconds |
| Started | Oct 09 08:01:59 AM UTC 24 |
| Finished | Oct 09 08:03:39 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505241144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2505241144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/46.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/46.hmac_smoke.4243954048 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 414986014 ps |
| CPU time | 4.56 seconds |
| Started | Oct 09 08:01:52 AM UTC 24 |
| Finished | Oct 09 08:01:58 AM UTC 24 |
| Peak memory | 210448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243954048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.4243954048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/46.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/46.hmac_stress_all.613566864 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 42707085301 ps |
| CPU time | 875.02 seconds |
| Started | Oct 09 08:02:42 AM UTC 24 |
| Finished | Oct 09 08:17:27 AM UTC 24 |
| Peak memory | 683256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613566864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.613566864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/46.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/46.hmac_wipe_secret.4153192628 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 5018871662 ps |
| CPU time | 143.74 seconds |
| Started | Oct 09 08:02:33 AM UTC 24 |
| Finished | Oct 09 08:05:00 AM UTC 24 |
| Peak memory | 210544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153192628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.4153192628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/46.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/47.hmac_alert_test.797029141 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 46784947 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 08:03:43 AM UTC 24 |
| Finished | Oct 09 08:03:45 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797029141 -assert nopostproc +UVM_TESTNAME=hmac_b ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hm ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.797029141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/47.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/47.hmac_back_pressure.2072824855 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 3054465188 ps |
| CPU time | 61.12 seconds |
| Started | Oct 09 08:03:04 AM UTC 24 |
| Finished | Oct 09 08:04:07 AM UTC 24 |
| Peak memory | 210424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072824855 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2072824855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/47.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/47.hmac_burst_wr.3236936227 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 7972970168 ps |
| CPU time | 103.89 seconds |
| Started | Oct 09 08:03:20 AM UTC 24 |
| Finished | Oct 09 08:05:07 AM UTC 24 |
| Peak memory | 219084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236936227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3236936227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/47.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/47.hmac_datapath_stress.201936336 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 133237345693 ps |
| CPU time | 1564.28 seconds |
| Started | Oct 09 08:03:04 AM UTC 24 |
| Finished | Oct 09 08:29:25 AM UTC 24 |
| Peak memory | 745028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201936336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.201936336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/47.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/47.hmac_error.3888319383 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 6515355160 ps |
| CPU time | 52.6 seconds |
| Started | Oct 09 08:03:34 AM UTC 24 |
| Finished | Oct 09 08:04:28 AM UTC 24 |
| Peak memory | 210404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888319383 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3888319383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/47.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/47.hmac_long_msg.222618652 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 1260260954 ps |
| CPU time | 33.43 seconds |
| Started | Oct 09 08:03:02 AM UTC 24 |
| Finished | Oct 09 08:03:37 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222618652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.222618652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/47.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/47.hmac_smoke.3048436117 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 451837926 ps |
| CPU time | 4.84 seconds |
| Started | Oct 09 08:02:54 AM UTC 24 |
| Finished | Oct 09 08:03:01 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048436117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3048436117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/47.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/47.hmac_stress_all.3161951581 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 328022851515 ps |
| CPU time | 2480.07 seconds |
| Started | Oct 09 08:03:42 AM UTC 24 |
| Finished | Oct 09 08:45:30 AM UTC 24 |
| Peak memory | 744636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161951581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3161951581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/47.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/47.hmac_wipe_secret.1360608519 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 21078006 ps |
| CPU time | 1.79 seconds |
| Started | Oct 09 08:03:38 AM UTC 24 |
| Finished | Oct 09 08:03:42 AM UTC 24 |
| Peak memory | 210448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360608519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1360608519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/47.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/48.hmac_alert_test.2873096124 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 13077753 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 08:04:32 AM UTC 24 |
| Finished | Oct 09 08:04:34 AM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873096124 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2873096124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/48.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/48.hmac_back_pressure.998078960 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 408118776 ps |
| CPU time | 30.52 seconds |
| Started | Oct 09 08:03:57 AM UTC 24 |
| Finished | Oct 09 08:04:29 AM UTC 24 |
| Peak memory | 210580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998078960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.998078960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/48.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/48.hmac_burst_wr.2217708392 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 5762560245 ps |
| CPU time | 66.21 seconds |
| Started | Oct 09 08:04:05 AM UTC 24 |
| Finished | Oct 09 08:05:13 AM UTC 24 |
| Peak memory | 210408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217708392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2217708392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/48.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/48.hmac_datapath_stress.3475907820 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 3146620927 ps |
| CPU time | 693.3 seconds |
| Started | Oct 09 08:03:57 AM UTC 24 |
| Finished | Oct 09 08:15:39 AM UTC 24 |
| Peak memory | 732344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475907820 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3475907820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/48.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/48.hmac_error.1331086453 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 16317653127 ps |
| CPU time | 221.15 seconds |
| Started | Oct 09 08:04:08 AM UTC 24 |
| Finished | Oct 09 08:07:53 AM UTC 24 |
| Peak memory | 210568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331086453 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1331086453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/48.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/48.hmac_long_msg.2113852483 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 5580558817 ps |
| CPU time | 96.05 seconds |
| Started | Oct 09 08:03:48 AM UTC 24 |
| Finished | Oct 09 08:05:26 AM UTC 24 |
| Peak memory | 210408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113852483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2113852483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/48.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/48.hmac_smoke.2012827174 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1612550950 ps |
| CPU time | 8.3 seconds |
| Started | Oct 09 08:03:46 AM UTC 24 |
| Finished | Oct 09 08:03:55 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012827174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2012827174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/48.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/48.hmac_stress_all.1622933442 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 19972855817 ps |
| CPU time | 3926.44 seconds |
| Started | Oct 09 08:04:32 AM UTC 24 |
| Finished | Oct 09 09:10:40 AM UTC 24 |
| Peak memory | 789784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622933442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1622933442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/48.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/48.hmac_wipe_secret.3441108340 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 20693751803 ps |
| CPU time | 157.34 seconds |
| Started | Oct 09 08:04:19 AM UTC 24 |
| Finished | Oct 09 08:06:59 AM UTC 24 |
| Peak memory | 210508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441108340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3441108340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/48.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/49.hmac_alert_test.2743691862 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 13979136 ps |
| CPU time | 0.81 seconds |
| Started | Oct 09 08:05:08 AM UTC 24 |
| Finished | Oct 09 08:05:09 AM UTC 24 |
| Peak memory | 207220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743691862 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2743691862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/49.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/49.hmac_back_pressure.300125303 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 120656374 ps |
| CPU time | 5.18 seconds |
| Started | Oct 09 08:04:40 AM UTC 24 |
| Finished | Oct 09 08:04:47 AM UTC 24 |
| Peak memory | 210596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300125303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.300125303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/49.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/49.hmac_burst_wr.2482335222 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 6982097064 ps |
| CPU time | 82.07 seconds |
| Started | Oct 09 08:04:50 AM UTC 24 |
| Finished | Oct 09 08:06:14 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482335222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2482335222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/49.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/49.hmac_datapath_stress.1848828940 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 16400134821 ps |
| CPU time | 855.93 seconds |
| Started | Oct 09 08:04:50 AM UTC 24 |
| Finished | Oct 09 08:19:16 AM UTC 24 |
| Peak memory | 765392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848828940 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1848828940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/49.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/49.hmac_error.4213633559 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 54988134789 ps |
| CPU time | 285.12 seconds |
| Started | Oct 09 08:04:50 AM UTC 24 |
| Finished | Oct 09 08:09:39 AM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213633559 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.4213633559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/49.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/49.hmac_long_msg.1626518528 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 49809188080 ps |
| CPU time | 191.64 seconds |
| Started | Oct 09 08:04:34 AM UTC 24 |
| Finished | Oct 09 08:07:49 AM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626518528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1626518528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/49.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/49.hmac_smoke.882528457 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 828012834 ps |
| CPU time | 6.32 seconds |
| Started | Oct 09 08:04:32 AM UTC 24 |
| Finished | Oct 09 08:04:40 AM UTC 24 |
| Peak memory | 210320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882528457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 49.hmac_smoke.882528457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/49.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/49.hmac_stress_all.1995817800 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 24027759812 ps |
| CPU time | 289.09 seconds |
| Started | Oct 09 08:05:01 AM UTC 24 |
| Finished | Oct 09 08:09:55 AM UTC 24 |
| Peak memory | 210472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995817800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1995817800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/49.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/49.hmac_wipe_secret.4096268142 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 6032834628 ps |
| CPU time | 139.54 seconds |
| Started | Oct 09 08:04:56 AM UTC 24 |
| Finished | Oct 09 08:07:18 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096268142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.4096268142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/49.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/5.hmac_alert_test.4103069581 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 46253014 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 07:40:22 AM UTC 24 |
| Finished | Oct 09 07:40:24 AM UTC 24 |
| Peak memory | 207212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103069581 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.4103069581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/5.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/5.hmac_back_pressure.1478732220 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2497087440 ps |
| CPU time | 21.61 seconds |
| Started | Oct 09 07:40:14 AM UTC 24 |
| Finished | Oct 09 07:40:38 AM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478732220 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1478732220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/5.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/5.hmac_burst_wr.3239284528 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1100133843 ps |
| CPU time | 25.25 seconds |
| Started | Oct 09 07:40:15 AM UTC 24 |
| Finished | Oct 09 07:40:41 AM UTC 24 |
| Peak memory | 210300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239284528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3239284528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/5.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/5.hmac_datapath_stress.2196933635 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1748512850 ps |
| CPU time | 194.83 seconds |
| Started | Oct 09 07:40:15 AM UTC 24 |
| Finished | Oct 09 07:43:33 AM UTC 24 |
| Peak memory | 412844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196933635 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2196933635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/5.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/5.hmac_error.3789064744 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 5982790922 ps |
| CPU time | 94.16 seconds |
| Started | Oct 09 07:40:18 AM UTC 24 |
| Finished | Oct 09 07:41:54 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789064744 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3789064744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/5.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/5.hmac_long_msg.2886969498 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 647959957 ps |
| CPU time | 48.4 seconds |
| Started | Oct 09 07:40:13 AM UTC 24 |
| Finished | Oct 09 07:41:03 AM UTC 24 |
| Peak memory | 210448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886969498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2886969498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/5.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/5.hmac_smoke.185024874 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 5550426034 ps |
| CPU time | 16.42 seconds |
| Started | Oct 09 07:40:10 AM UTC 24 |
| Finished | Oct 09 07:40:29 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185024874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 5.hmac_smoke.185024874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/5.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/5.hmac_stress_all.268394518 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 624652026576 ps |
| CPU time | 2050.07 seconds |
| Started | Oct 09 07:40:18 AM UTC 24 |
| Finished | Oct 09 08:14:52 AM UTC 24 |
| Peak memory | 738504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268394518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.268394518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/5.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/5.hmac_wipe_secret.3528150000 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 3010831878 ps |
| CPU time | 42.93 seconds |
| Started | Oct 09 07:40:18 AM UTC 24 |
| Finished | Oct 09 07:41:02 AM UTC 24 |
| Peak memory | 210628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528150000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3528150000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/5.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/6.hmac_alert_test.1347313415 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 15918023 ps |
| CPU time | 0.93 seconds |
| Started | Oct 09 07:40:39 AM UTC 24 |
| Finished | Oct 09 07:40:41 AM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347313415 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1347313415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/6.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/6.hmac_back_pressure.443139524 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 5593739780 ps |
| CPU time | 80.23 seconds |
| Started | Oct 09 07:40:28 AM UTC 24 |
| Finished | Oct 09 07:41:50 AM UTC 24 |
| Peak memory | 219224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443139524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.443139524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/6.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/6.hmac_datapath_stress.1561856906 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 621047432 ps |
| CPU time | 87.89 seconds |
| Started | Oct 09 07:40:30 AM UTC 24 |
| Finished | Oct 09 07:42:00 AM UTC 24 |
| Peak memory | 394392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561856906 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1561856906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/6.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/6.hmac_error.2473781595 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1773612595 ps |
| CPU time | 67.56 seconds |
| Started | Oct 09 07:40:35 AM UTC 24 |
| Finished | Oct 09 07:41:45 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473781595 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2473781595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/6.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/6.hmac_long_msg.2931204569 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 16451544 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 07:40:25 AM UTC 24 |
| Finished | Oct 09 07:40:27 AM UTC 24 |
| Peak memory | 207208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931204569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2931204569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/6.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/6.hmac_smoke.2394953955 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 510822500 ps |
| CPU time | 11.2 seconds |
| Started | Oct 09 07:40:25 AM UTC 24 |
| Finished | Oct 09 07:40:38 AM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394953955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2394953955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/6.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/6.hmac_stress_all.3916565136 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 109349812313 ps |
| CPU time | 371.63 seconds |
| Started | Oct 09 07:40:36 AM UTC 24 |
| Finished | Oct 09 07:46:55 AM UTC 24 |
| Peak memory | 679272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916565136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3916565136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/6.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/6.hmac_wipe_secret.3358718832 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 9661609177 ps |
| CPU time | 41.89 seconds |
| Started | Oct 09 07:40:35 AM UTC 24 |
| Finished | Oct 09 07:41:19 AM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358718832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3358718832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/6.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/7.hmac_alert_test.4205160339 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 144056934 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 07:40:54 AM UTC 24 |
| Finished | Oct 09 07:40:56 AM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205160339 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.4205160339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/7.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/7.hmac_back_pressure.3932554258 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 2069754402 ps |
| CPU time | 65.27 seconds |
| Started | Oct 09 07:40:42 AM UTC 24 |
| Finished | Oct 09 07:41:49 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932554258 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3932554258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/7.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/7.hmac_burst_wr.3869442145 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 3277940316 ps |
| CPU time | 40.43 seconds |
| Started | Oct 09 07:40:44 AM UTC 24 |
| Finished | Oct 09 07:41:26 AM UTC 24 |
| Peak memory | 210404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869442145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3869442145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/7.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/7.hmac_datapath_stress.1364417364 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 16822888675 ps |
| CPU time | 813.41 seconds |
| Started | Oct 09 07:40:44 AM UTC 24 |
| Finished | Oct 09 07:54:27 AM UTC 24 |
| Peak memory | 744684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364417364 -assert nopostproc +UVM_TESTNAME=hmac_base_test + UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hma c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1364417364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/7.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/7.hmac_error.2750158510 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 34044588747 ps |
| CPU time | 244.99 seconds |
| Started | Oct 09 07:40:46 AM UTC 24 |
| Finished | Oct 09 07:44:55 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750158510 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2750158510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/7.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/7.hmac_long_msg.2192375424 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 755392760 ps |
| CPU time | 43.81 seconds |
| Started | Oct 09 07:40:42 AM UTC 24 |
| Finished | Oct 09 07:41:28 AM UTC 24 |
| Peak memory | 210340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192375424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2192375424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/7.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/7.hmac_smoke.1627839722 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 71530954 ps |
| CPU time | 2.46 seconds |
| Started | Oct 09 07:40:39 AM UTC 24 |
| Finished | Oct 09 07:40:43 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627839722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1627839722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/7.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/7.hmac_stress_all.2438968143 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 36148223823 ps |
| CPU time | 1401.43 seconds |
| Started | Oct 09 07:40:47 AM UTC 24 |
| Finished | Oct 09 08:04:25 AM UTC 24 |
| Peak memory | 447940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438968143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2438968143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/7.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/7.hmac_wipe_secret.3058550802 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 7021457847 ps |
| CPU time | 70.79 seconds |
| Started | Oct 09 07:40:46 AM UTC 24 |
| Finished | Oct 09 07:41:59 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058550802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3058550802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/7.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/8.hmac_alert_test.1177481329 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 20092166 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 07:41:21 AM UTC 24 |
| Finished | Oct 09 07:41:23 AM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177481329 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1177481329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/8.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/8.hmac_burst_wr.2244517297 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 120010710 ps |
| CPU time | 2.99 seconds |
| Started | Oct 09 07:41:05 AM UTC 24 |
| Finished | Oct 09 07:41:09 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244517297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2244517297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/8.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/8.hmac_datapath_stress.69259740 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 3807712795 ps |
| CPU time | 810.53 seconds |
| Started | Oct 09 07:41:03 AM UTC 24 |
| Finished | Oct 09 07:54:43 AM UTC 24 |
| Peak memory | 779828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69259740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV M_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.69259740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/8.hmac_datapath_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/8.hmac_error.2037490620 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 49716002668 ps |
| CPU time | 244.18 seconds |
| Started | Oct 09 07:41:09 AM UTC 24 |
| Finished | Oct 09 07:45:17 AM UTC 24 |
| Peak memory | 210364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037490620 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2037490620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/8.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/8.hmac_long_msg.3529162069 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 12694531236 ps |
| CPU time | 130.17 seconds |
| Started | Oct 09 07:41:01 AM UTC 24 |
| Finished | Oct 09 07:43:14 AM UTC 24 |
| Peak memory | 210544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529162069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3529162069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/8.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/8.hmac_smoke.2091946999 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 663891076 ps |
| CPU time | 11.5 seconds |
| Started | Oct 09 07:40:57 AM UTC 24 |
| Finished | Oct 09 07:41:09 AM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091946999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2091946999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/8.hmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/8.hmac_stress_all.1311267298 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2394538407 ps |
| CPU time | 5.87 seconds |
| Started | Oct 09 07:41:11 AM UTC 24 |
| Finished | Oct 09 07:41:18 AM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311267298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1311267298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/8.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/8.hmac_stress_all_with_rand_reset.566395328 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 7318644360 ps |
| CPU time | 130.49 seconds |
| Started | Oct 09 07:41:19 AM UTC 24 |
| Finished | Oct 09 07:43:32 AM UTC 24 |
| Peak memory | 410556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56639532 8 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.566395328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/8.hmac_wipe_secret.842507549 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 5480461167 ps |
| CPU time | 79.51 seconds |
| Started | Oct 09 07:41:10 AM UTC 24 |
| Finished | Oct 09 07:42:31 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842507549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.842507549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/8.hmac_wipe_secret/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/9.hmac_alert_test.3314360088 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 36570478 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 07:41:36 AM UTC 24 |
| Finished | Oct 09 07:41:38 AM UTC 24 |
| Peak memory | 207140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314360088 -assert nopostproc +UVM_TESTNAME=hmac_ base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/h mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3314360088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/9.hmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/9.hmac_back_pressure.938019328 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1013203739 ps |
| CPU time | 35.41 seconds |
| Started | Oct 09 07:41:26 AM UTC 24 |
| Finished | Oct 09 07:42:03 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938019328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.938019328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/9.hmac_back_pressure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/9.hmac_burst_wr.831456377 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4577219389 ps |
| CPU time | 85.83 seconds |
| Started | Oct 09 07:41:28 AM UTC 24 |
| Finished | Oct 09 07:42:56 AM UTC 24 |
| Peak memory | 210576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831456377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.831456377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/9.hmac_burst_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/9.hmac_error.3113061289 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 14661193084 ps |
| CPU time | 139.34 seconds |
| Started | Oct 09 07:41:28 AM UTC 24 |
| Finished | Oct 09 07:43:50 AM UTC 24 |
| Peak memory | 210420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113061289 -assert nopostproc +UVM_TESTNAME=hm ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3113061289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/9.hmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/9.hmac_long_msg.739470887 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 9546582866 ps |
| CPU time | 133.66 seconds |
| Started | Oct 09 07:41:24 AM UTC 24 |
| Finished | Oct 09 07:43:40 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739470887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.739470887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/9.hmac_long_msg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/9.hmac_stress_all.3263798501 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 30369126474 ps |
| CPU time | 776.99 seconds |
| Started | Oct 09 07:41:30 AM UTC 24 |
| Finished | Oct 09 07:54:37 AM UTC 24 |
| Peak memory | 443552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263798501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ= hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3263798501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/9.hmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/9.hmac_stress_all_with_rand_reset.2147450040 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 2871386579 ps |
| CPU time | 146.4 seconds |
| Started | Oct 09 07:41:31 AM UTC 24 |
| Finished | Oct 09 07:44:00 AM UTC 24 |
| Peak memory | 218964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_08/hmac-s im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21474500 40 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.2147450040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/default/9.hmac_wipe_secret.1809737515 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 16512709336 ps |
| CPU time | 65.1 seconds |
| Started | Oct 09 07:41:30 AM UTC 24 |
| Finished | Oct 09 07:42:37 AM UTC 24 |
| Peak memory | 210448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809737515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1809737515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/9.hmac_wipe_secret/latest |
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