Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39658837	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37012517

1

T1

2819

T2

5

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36714148	1			T1	3019		T2	1		T3	1
values[0x0]	18755560	1			T1	1216		T2	2		T4	2759
values[0x1]	21201646	1			T1	1359		T2	4		T4	3119

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30602386	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

46068968

1

T1

3520

T2

5

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	537146	1			T4	99		T5	19		T8	75
valid_sources[0x01]	212384	1			T4	40		T5	10		T8	84
valid_sources[0x02]	217914	1			T4	49		T5	1		T8	98
valid_sources[0x03]	213260	1			T4	64		T5	23		T8	92
valid_sources[0x04]	213401	1			T4	68		T8	58		T10	74
valid_sources[0x05]	412300	1			T4	37		T5	19		T8	40
valid_sources[0x06]	217774	1			T4	59		T5	12		T8	29
valid_sources[0x07]	242664	1			T4	31		T8	51		T10	63
valid_sources[0x08]	1094570	1			T4	29		T5	7		T8	90
valid_sources[0x09]	218045	1			T4	29		T5	3		T8	76
valid_sources[0x0a]	215038	1			T4	78		T5	17		T8	21
valid_sources[0x0b]	211882	1			T4	52		T5	1		T8	79
valid_sources[0x0c]	236269	1			T4	85		T5	5		T8	85
valid_sources[0x0d]	215226	1			T4	37		T5	28		T8	74
valid_sources[0x0e]	245879	1			T4	34		T5	4		T8	31
valid_sources[0x0f]	213414	1			T4	30		T5	1		T8	102
valid_sources[0x10]	215399	1			T2	1		T4	42		T5	12
valid_sources[0x11]	722138	1			T4	59		T5	6		T8	48
valid_sources[0x12]	518183	1			T4	59		T5	7		T8	93
valid_sources[0x13]	276257	1			T4	52		T5	2		T8	79
valid_sources[0x14]	212619	1			T4	43		T8	52		T10	74
valid_sources[0x15]	214003	1			T4	35		T5	11		T8	91
valid_sources[0x16]	227463	1			T4	58		T5	26		T8	85
valid_sources[0x17]	214142	1			T4	34		T5	7		T8	80
valid_sources[0x18]	299359	1			T4	25		T5	12		T8	59
valid_sources[0x19]	213980	1			T4	56		T5	2		T8	60
valid_sources[0x1a]	234335	1			T4	13		T5	8		T8	60
valid_sources[0x1b]	215171	1			T4	51		T5	3		T8	28
valid_sources[0x1c]	213207	1			T4	22		T5	5		T8	33
valid_sources[0x1d]	212405	1			T4	62		T5	2		T8	60
valid_sources[0x1e]	214721	1			T4	64		T8	23		T10	95
valid_sources[0x1f]	215241	1			T4	19		T8	105		T10	90
valid_sources[0x20]	211674	1			T4	60		T5	15		T8	116
valid_sources[0x21]	338550	1			T4	38		T5	8		T8	102
valid_sources[0x22]	216867	1			T4	64		T5	17		T8	143
valid_sources[0x23]	213037	1			T4	62		T5	12		T8	52
valid_sources[0x24]	272171	1			T4	64		T5	5		T8	46
valid_sources[0x25]	212499	1			T4	38		T5	4		T8	49
valid_sources[0x26]	338620	1			T4	1		T5	17		T8	109
valid_sources[0x27]	212820	1			T4	23		T8	72		T10	46
valid_sources[0x28]	255730	1			T4	27		T5	10		T8	73
valid_sources[0x29]	237551	1			T4	14		T5	2		T8	71
valid_sources[0x2a]	213197	1			T4	7		T5	18		T8	72
valid_sources[0x2b]	215124	1			T4	69		T5	2		T8	106
valid_sources[0x2c]	210247	1			T4	44		T5	17		T8	59
valid_sources[0x2d]	694343	1			T4	37		T5	4		T8	161
valid_sources[0x2e]	211373	1			T4	59		T5	15		T8	99
valid_sources[0x2f]	411836	1			T4	18		T5	11		T8	67
valid_sources[0x30]	214797	1			T4	37		T5	6		T8	38
valid_sources[0x31]	213764	1			T4	49		T5	4		T8	58
valid_sources[0x32]	211983	1			T4	17		T5	4		T8	62
valid_sources[0x33]	219418	1			T1	5594		T4	16		T5	11
valid_sources[0x34]	216696	1			T4	34		T5	12		T8	96
valid_sources[0x35]	227976	1			T4	60		T5	6		T8	69
valid_sources[0x36]	254769	1			T4	50		T5	4		T8	48
valid_sources[0x37]	213131	1			T4	40		T8	75		T10	108
valid_sources[0x38]	214976	1			T4	43		T5	4		T8	60
valid_sources[0x39]	653831	1			T2	1		T4	11		T5	10
valid_sources[0x3a]	214344	1			T4	27		T5	12		T8	63
valid_sources[0x3b]	212321	1			T4	34		T5	31		T8	127
valid_sources[0x3c]	214147	1			T4	29		T5	39		T8	69
valid_sources[0x3d]	461233	1			T4	62		T5	8		T8	67
valid_sources[0x3e]	215317	1			T4	8		T5	8		T8	112
valid_sources[0x3f]	212933	1			T4	12		T5	5		T8	33
valid_sources[0x40]	215650	1			T4	50		T5	8		T8	69
valid_sources[0x41]	213616	1			T4	46		T5	4		T8	80
valid_sources[0x42]	451679	1			T4	35		T5	9		T8	121
valid_sources[0x43]	216223	1			T4	57		T5	1		T8	64
valid_sources[0x44]	237733	1			T4	89		T5	6		T8	32
valid_sources[0x45]	212945	1			T4	49		T5	9		T8	64
valid_sources[0x46]	212632	1			T4	46		T5	10		T8	59
valid_sources[0x47]	212020	1			T4	29		T8	82		T10	87
valid_sources[0x48]	212420	1			T4	32		T5	9		T8	56
valid_sources[0x49]	214622	1			T4	33		T5	17		T8	68
valid_sources[0x4a]	267872	1			T4	33		T5	8		T8	53
valid_sources[0x4b]	1172303	1			T4	47		T5	9		T8	109
valid_sources[0x4c]	330445	1			T4	40		T5	3		T8	53
valid_sources[0x4d]	214602	1			T4	17		T5	10		T8	78
valid_sources[0x4e]	214372	1			T4	28		T5	10		T8	119
valid_sources[0x4f]	213629	1			T2	1		T4	116		T5	4
valid_sources[0x50]	248685	1			T4	31		T5	9		T8	98
valid_sources[0x51]	210690	1			T4	37		T5	1		T8	51
valid_sources[0x52]	404556	1			T4	56		T5	30		T8	55
valid_sources[0x53]	212027	1			T4	13		T5	6		T8	37
valid_sources[0x54]	291415	1			T4	35		T8	80		T10	53
valid_sources[0x55]	232543	1			T4	45		T5	8		T8	83
valid_sources[0x56]	215749	1			T4	69		T5	4		T8	100
valid_sources[0x57]	261765	1			T4	88		T5	9		T8	141
valid_sources[0x58]	215865	1			T4	56		T5	24		T8	60
valid_sources[0x59]	571546	1			T4	18		T5	2		T8	102
valid_sources[0x5a]	213448	1			T2	1		T4	26		T5	3
valid_sources[0x5b]	224295	1			T4	29		T5	26		T8	70
valid_sources[0x5c]	211767	1			T4	11		T5	4		T8	68
valid_sources[0x5d]	212467	1			T4	68		T5	1		T8	125
valid_sources[0x5e]	277862	1			T4	38		T5	7		T8	48
valid_sources[0x5f]	421321	1			T4	36		T5	1		T8	97
valid_sources[0x60]	222081	1			T4	57		T5	16		T8	32
valid_sources[0x61]	216072	1			T4	29		T5	5		T8	131
valid_sources[0x62]	215915	1			T4	48		T5	5		T8	94
valid_sources[0x63]	214138	1			T4	76		T5	8		T8	81
valid_sources[0x64]	212892	1			T4	55		T8	112		T10	32
valid_sources[0x65]	213441	1			T4	42		T5	8		T8	76
valid_sources[0x66]	214889	1			T4	55		T5	1		T8	57
valid_sources[0x67]	217942	1			T4	24		T5	4		T8	76
valid_sources[0x68]	256051	1			T4	79		T5	11		T8	40
valid_sources[0x69]	215317	1			T4	65		T5	7		T8	135
valid_sources[0x6a]	217305	1			T4	40		T5	6		T8	49
valid_sources[0x6b]	520846	1			T4	32		T5	4		T8	71
valid_sources[0x6c]	215755	1			T4	7		T5	6		T8	64
valid_sources[0x6d]	214662	1			T4	27		T5	23		T8	78
valid_sources[0x6e]	217113	1			T4	74		T5	6		T8	39
valid_sources[0x6f]	211954	1			T4	54		T5	9		T8	163
valid_sources[0x70]	218011	1			T4	30		T5	3		T8	45
valid_sources[0x71]	428730	1			T4	75		T5	1		T8	93
valid_sources[0x72]	273078	1			T4	35		T5	2		T8	121
valid_sources[0x73]	212378	1			T4	75		T5	4		T8	95
valid_sources[0x74]	2133087	1			T4	44		T8	39		T10	28
valid_sources[0x75]	219662	1			T4	19		T5	16		T8	39
valid_sources[0x76]	211833	1			T4	26		T5	15		T8	58
valid_sources[0x77]	213848	1			T4	90		T5	3		T8	46
valid_sources[0x78]	1302954	1			T4	26		T5	3		T8	54
valid_sources[0x79]	1184883	1			T4	68		T5	6		T8	50
valid_sources[0x7a]	212889	1			T4	25		T5	8		T8	74
valid_sources[0x7b]	212657	1			T4	47		T5	1		T8	88
valid_sources[0x7c]	212212	1			T4	38		T5	4		T8	106
valid_sources[0x7d]	218077	1			T4	58		T5	1		T8	53
valid_sources[0x7e]	249493	1			T4	56		T5	12		T7	3722
valid_sources[0x7f]	212535	1			T4	16		T5	11		T8	70
valid_sources[0x80]	210918	1			T4	67		T5	11		T8	37

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18131382

1

T1

1348

T2

1

T3

1

values[0x0]

all_enables

biggest_size

10192944

1

T1

767

T2

2

T4

1324

values[0x1]

all_enables

biggest_size

8688191

1

T1

704

T2

2

T4

1009