Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

40376758

1

T1

2775

T2

2

T4

6622

full_word

37059725

1

T1

2819

T2

5

T3

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	77436113	1			T1	5594		T2	7		T3	1
auto[TlIntgErrCmd]	130	1			T56	5		T57	4		T58	1
auto[TlIntgErrData]	109	1			T56	3		T57	5		T58	3
auto[TlIntgErrBoth]	131	1			T56	2		T57	1		T58	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36956260

1

T1

3019

T2

1

T3

1

auto[1]

40480223

1

T1

2575

T2

6

T4

5878

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18806208	1			T1	1671		T4	3077		T5	492
auto[TlIntgErrNone]	partial	auto[1]	21570213	1			T1	1104		T2	2		T4	3545
auto[TlIntgErrNone]	full_word	auto[0]	18149879	1			T1	1348		T2	1		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	18909813	1			T1	1471		T2	4		T4	2333
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T56	2		T57	1		T135	5
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T56	3		T57	2		T135	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T57	1		T60	1		T141	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T58	1		T142	1		T143	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T57	4		T58	1		T135	3
auto[TlIntgErrData]	partial	auto[1]	41	1			T56	2		T57	1		T58	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T58	1		T140	1		T59	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T56	1		T135	1		T139	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T56	1		T58	3		T135	2
auto[TlIntgErrBoth]	partial	auto[1]	73	1			T56	1		T57	1		T58	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T135	2		T138	1		T139	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T138	1		T144	1		-	-