Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	425944570	1033585	0	0
intr_enable_rd_A	425944570	3550	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425944570	1033585	0	0
T20	912188	11239	0	0
T21	0	14637	0	0
T22	207171	2250	0	0
T23	0	2894	0	0
T31	0	8200	0	0
T61	0	6	0	0
T65	0	15414	0	0
T66	0	4499	0	0
T67	0	713	0	0
T68	0	679	0	0
T69	24863	0	0	0
T70	103322	0	0	0
T71	335360	0	0	0
T72	794	0	0	0
T73	312020	0	0	0
T74	288033	0	0	0
T75	396443	0	0	0
T76	137249	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425944570	3550	0	0
T20	912188	48	0	0
T22	207171	0	0	0
T69	24863	0	0	0
T70	103322	0	0	0
T71	335360	0	0	0
T72	794	0	0	0
T73	312020	0	0	0
T74	288033	0	0	0
T75	396443	0	0	0
T76	137249	0	0	0
T77	0	14	0	0
T78	0	34	0	0
T79	0	28	0	0
T80	0	41	0	0
T81	0	19	0	0
T82	0	14	0	0
T83	0	66	0	0
T84	0	62	0	0
T85	0	35	0	0