I2C Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	42.900s	2.343ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	10.070s	1.505ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.720s	30.047us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.690s	28.136us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.470s	336.670us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	0.980s	64.475us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.780s	33.779us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.690s	28.136us	20	20	100.00
		i2c_csr_aliasing	0.980s	64.475us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	1.440s	74.225us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	20.327m	32.807ms	50	50	100.00
V2	host_perf	i2c_host_perf	1.100m	6.831ms	50	50	100.00
V2	host_override	i2c_host_override	0.680s	23.672us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.080m	7.919ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	4.504m	7.926ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.030s	209.010us	50	50	100.00
		i2c_host_fifo_fmt_empty	7.080s	606.668us	50	50	100.00
		i2c_host_fifo_reset_rx	4.050s	236.313us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.288m	3.768ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	14.420s	1.467ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample	2.091m	3.939ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.044m	3.754ms	50	50	100.00
V2	target_error_intr	i2c_target_unexp_stop	5.840s	1.922ms	50	50	100.00
V2	target_glitch	i2c_target_glitch	3.980s	1.417ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	31.905m	66.540ms	50	50	100.00
V2	target_perf	i2c_target_perf	3.350s	834.576us	50	50	100.00
V2	target_fifo_overflow	i2c_target_tx_ovf	2.670m	5.445ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	9.300s	997.772us	50	50	100.00
		i2c_target_intr_smoke	4.520s	1.588ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	34.870s	10.166ms	50	50	100.00
		i2c_target_fifo_reset_tx	41.330s	10.065ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.668m	14.461ms	50	50	100.00
		i2c_target_stress_rd	9.300s	997.772us	50	50	100.00
		i2c_target_intr_stress_wr	24.940s	5.106ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	8.100s	2.856ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	1.436m	6.282ms	50	50	100.00
V2	bad_address	i2c_target_bad_addr	3.980s	1.520ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	2.550s	825.344us	50	50	100.00
V2	alert_test	i2c_alert_test	0.640s	19.976us	50	50	100.00
V2	intr_test	i2c_intr_test	0.710s	24.422us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.410s	97.279us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.410s	97.279us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.720s	30.047us	5	5	100.00
		i2c_csr_rw	0.690s	28.136us	20	20	100.00
		i2c_csr_aliasing	0.980s	64.475us	5	5	100.00
		i2c_same_csr_outstanding	0.920s	48.993us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.720s	30.047us	5	5	100.00
		i2c_csr_rw	0.690s	28.136us	20	20	100.00
		i2c_csr_aliasing	0.980s	64.475us	5	5	100.00
		i2c_same_csr_outstanding	0.920s	48.993us	20	20	100.00
V2		TOTAL			1492	1492	100.00
V2S	tl_intg_err	i2c_tl_intg_err	1.390s	114.886us	20	20	100.00
		i2c_sec_cm	0.880s	62.618us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.390s	114.886us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset			0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	5.870s	583.258us	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	100	0.00
		TOTAL			1672	1772	94.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	32	32	32	100.00
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.12	98.93	91.44	99.76	91.30	97.69	98.39	81.30

Failure Buckets

• Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 50 failures:
  • Test i2c_host_stress_all_with_rand_reset has 50 failures.

    • 0.i2c_host_stress_all_with_rand_reset.21656844631855792034613022807884217398241950019935004573780575231733165199322
      Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:b85db36c-84f0-4b20-b766-e049d8a9fb7a
      

    • 1.i2c_host_stress_all_with_rand_reset.9887463100391288637029652273777944070693509649417007764745642185952492122569
      Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:579db29c-82ce-46ad-b21e-f564aa9988fd
      

    • ... and 48 more failures.

• UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 50 failures:
  • Test i2c_target_stress_all_with_rand_reset has 50 failures.

    • 0.i2c_target_stress_all_with_rand_reset.16861789212555716061755188678691992420262431599733346686771482836179075159016
      Line 211, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 583257766 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x3ba36a94) == 0x0
        UVM_INFO @ 583257766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.i2c_target_stress_all_with_rand_reset.45839305412295770124492945308291470890831027036110520162001595725953636252285
      Line 211, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 583257766 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x3ba36a94) == 0x0
        UVM_INFO @ 583257766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 48 more failures.

Past Results

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