I2C Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: `41bc3e0c7f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.513m	1.693ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	1.057m	5.994ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.720s	61.026us	5	5	100.00
V1	csr_rw	i2c_csr_rw	12.600s	13.561ms	16	20	80.00
V1	csr_bit_bash	i2c_csr_bit_bash	6.230s	5.196ms	4	5	80.00
V1	csr_aliasing	i2c_csr_aliasing	2.130s	404.795us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.520s	32.742us	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	12.600s	13.561ms	16	20	80.00
		i2c_csr_aliasing	2.130s	404.795us	5	5	100.00
V1		TOTAL			147	155	94.84
V2	host_error_intr	i2c_host_error_intr	2.070s	929.964us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	57.947m	60.863ms	48	50	96.00
V2	host_maxperf	i2c_host_perf	54.018m	48.766ms	50	50	100.00
V2	host_override	i2c_host_override	0.740s	314.445us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	5.742m	20.398ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.656m	4.399ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.290s	158.689us	50	50	100.00
		i2c_host_fifo_fmt_empty	22.920s	888.805us	50	50	100.00
		i2c_host_fifo_reset_rx	9.620s	1.758ms	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.791m	2.263ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	42.210s	905.607us	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.832m	30.897ms	50	50	100.00
V2	target_error_intr	i2c_target_unexp_stop	7.420s	1.914ms	7	50	14.00
V2	target_glitch	i2c_target_glitch	9.040s	7.850ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	23.837m	72.903ms	1	50	2.00
V2	target_maxperf	i2c_target_perf	1.050s	344.346us	0	50	0.00
V2	target_fifo_empty	i2c_target_stress_rd	1.250m	15.386ms	50	50	100.00
		i2c_target_intr_smoke	7.770s	1.642ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.348m	10.040ms	50	50	100.00
		i2c_target_fifo_reset_tx	1.550m	10.053ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	39.014m	62.387ms	50	50	100.00
		i2c_target_stress_rd	1.250m	15.386ms	50	50	100.00
		i2c_target_intr_stress_wr	8.871m	24.340ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	8.070s	3.236ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	59.410m	28.983ms	48	50	96.00
V2	bad_address	i2c_target_bad_addr	5.910s	2.656ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	3.000s	1.033ms	50	50	100.00
V2	target_fifo_watermark	i2c_host_fifo_watermark	5.742m	20.398ms	50	50	100.00
V2	host_mode_config_perf	host_mode_config_perf			0	0	--
V2	host_mode_clock_stretching	host_mode_clock_stretching			0	0	--
V2	target_mode_txrst_on_cond	target_mode_txrst_on_cond			0	0	--
V2	target_mode_nack_generation	target_mode_nack_generation			0	0	--
V2	host_mode_halt_on_nak	host_mode_halt_on_nak			0	0	--
V2	alert_test	i2c_alert_test	0.690s	42.514us	50	50	100.00
V2	intr_test	i2c_intr_test	0.830s	16.412us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.930s	551.083us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.930s	551.083us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.720s	61.026us	5	5	100.00
		i2c_csr_rw	12.600s	13.561ms	16	20	80.00
		i2c_csr_aliasing	2.130s	404.795us	5	5	100.00
		i2c_same_csr_outstanding	1.130s	382.840us	8	20	40.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.720s	61.026us	5	5	100.00
		i2c_csr_rw	12.600s	13.561ms	16	20	80.00
		i2c_csr_aliasing	2.130s	404.795us	5	5	100.00
		i2c_same_csr_outstanding	1.130s	382.840us	8	20	40.00
V2		TOTAL			1234	1392	88.65
V2S	tl_intg_err	i2c_tl_intg_err	2.380s	145.403us	17	20	85.00
		i2c_sec_cm	0.970s	275.245us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.380s	145.403us	17	20	85.00
V2S		TOTAL			22	25	88.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	14.419m	154.571ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	7.164m	61.783ms	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	100	0.00
	Unmapped tests	i2c_host_may_nack	20.630s	508.108us	50	50	100.00
		TOTAL			1453	1722	84.38

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	7	7	4	57.14
V2	36	30	24	66.67
V2S	2	2	1	50.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.57	97.19	91.83	97.66	83.74	94.53	98.67	91.39

Failure Buckets

UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 96 failures:
- Test i2c_target_perf has 49 failures.
  - 0.i2c_target_perf.72444074246366432934321723335966870847777046934950613463730599571035964936220
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
```
  UVM_ERROR @ 130466347 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 130466347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_perf.114350281963137092182063322976447225821199743526874920818662779422062275926199
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  20270107 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  20270107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 47 more failures.
- Test i2c_target_stress_all has 29 failures.
  - 0.i2c_target_stress_all.97686882105123560892006985207626890565554160072374192119505330814800475288225
    Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 23324178813 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 23324178813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_stress_all.61807713991006851736298796590580119549282365949498136492179347344830593967967
    Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 14680831274 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 14680831274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
- Test i2c_target_stress_all_with_rand_reset has 18 failures.
  - 0.i2c_target_stress_all_with_rand_reset.67935151958071373612030780910468640245868576593961332923881328135510878311179
    Line 277, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8345108147 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 8345108147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.i2c_target_stress_all_with_rand_reset.74481206725920221773977723115323963930752322699940605523378380912604506737794
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 440452156 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 440452156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 16 more failures.
UVM_ERROR (i2c_base_vseq.sv:985) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 62 failures:
- Test i2c_target_unexp_stop has 43 failures.
  - 0.i2c_target_unexp_stop.102301689021743349048114556736330407199879433612152118761531692768542127201982
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 748260066 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 748260066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_unexp_stop.88695227997851367443172531341006532380807697714130322694949649149807116065755
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 4480339665 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 4480339665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 41 more failures.
- Test i2c_target_stress_all has 19 failures.
  - 4.i2c_target_stress_all.104178527450499143704412450997391225181162977273454669358625162534770778538951
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 791530620 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 791530620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.i2c_target_stress_all.113148751745037222787054560337405152003479477201983921849514422016579539273875
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 10197447556 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 10197447556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.

UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 53 failures:

Test i2c_host_stress_all_with_rand_reset has 43 failures.

0.i2c_host_stress_all_with_rand_reset.13840710560846993811490906074709362407080026151611285603926925554235605035657
Line 2407, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 17186555535 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 17186555535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.89947242125329718812914266748209628565591703795415515477468442326998762337211
Line 1582, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2497621322 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2497621322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 41 more failures.

Test i2c_target_stress_all_with_rand_reset has 10 failures.

2.i2c_target_stress_all_with_rand_reset.79424874318394718080568461926198363678748557309921175261870637263274513450864
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3598066107 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3598066107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_target_stress_all_with_rand_reset.45352903139686040422953279499479263900824630870613137850363567483132710858058
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1533423823 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1533423823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_ERROR (cip_base_vseq.sv:250) [i2c_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 11 failures:
- Test i2c_same_csr_outstanding has 11 failures.
  - 0.i2c_same_csr_outstanding.24833304958459233096510109872788980795008182388064720103593267326865760325658
    Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @  21134057 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x2b605ff0 read out mismatch
  UVM_INFO @  21134057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_same_csr_outstanding.47846932720029334289774606732397680123317860234107089852127683348605525267988
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @  11285668 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (3 [0x3] vs 0 [0x0]) addr 0x43a265f0 read out mismatch
  UVM_INFO @  11285668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 10 failures:
- Test i2c_target_stress_all_with_rand_reset has 10 failures.
  - 1.i2c_target_stress_all_with_rand_reset.41534694918818916978250532999706168812593572711185666856151408089722074672411
    Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 3144999514 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 3144999514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 3.i2c_target_stress_all_with_rand_reset.67593785890911408628922208074217221031598460890156640333957411430668660467040
    Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 1545714074 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 1545714074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 8 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:
- Test i2c_host_stress_all_with_rand_reset has 5 failures.
  - 2.i2c_host_stress_all_with_rand_reset.76395093450289105024377574966310489406690842378185166944576487569093808346812
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:f8f14ca0-9dde-437e-a33e-dbf6657cc46a
```
  - 5.i2c_host_stress_all_with_rand_reset.35034910224114486181646350023207617803084735385299407014259319836523943925237
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3f4c1272-2853-49b9-b1df-6d205967dfd0
```
  - ... and 3 more failures.
- Test i2c_host_stress_all has 2 failures.
  - 5.i2c_host_stress_all.58579536446863901917205341873131220133931758050576956693257523369225463673253
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:8135936c-263b-47a1-b0e0-80b46bc06c95
```
  - 13.i2c_host_stress_all.48249613237430617357710524792361628526619794008123154220290833346185129687577
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:ba9ef3da-5ed4-462a-8274-d5e3c809e584
```
- Test i2c_target_stretch has 2 failures.
  - 28.i2c_target_stretch.80796855591968119747748272501464825909324118799922938079701034354976410558205
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_stretch/latest/run.log
```
  Job ID: smart:da159dff-7273-41d0-9b54-74eeaa3cf60c
```
  - 45.i2c_target_stretch.92123145356303222388107217885061119138895903187662987490102805053856842924636
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_target_stretch/latest/run.log
```
  Job ID: smart:f08ce4d5-66c9-43b9-8336-89a736fcfbce
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 35.i2c_target_stress_all_with_rand_reset.70724151689136869455343784634281936507660064852719458131294320074953283922670
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:793b66e5-2e08-467a-9708-717ce62e5ff6
```

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.acq_fifo_next_data reset value: * has 5 failures:

Test i2c_tl_intg_err has 3 failures.

3.i2c_tl_intg_err.29867664807145429506448662873203822547303422509433967881464067093376882435242
Line 318, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_tl_intg_err/latest/run.log

  UVM_ERROR @  33077694 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
  UVM_INFO @  33077694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_tl_intg_err.88892725392135878446677692524690966009986726380019941287710261893484096426907
Line 367, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_tl_intg_err/latest/run.log

  UVM_ERROR @  95645196 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
  UVM_INFO @  95645196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test i2c_csr_mem_rw_with_rand_reset has 2 failures.

3.i2c_csr_mem_rw_with_rand_reset.8721959948338405436489331786534263285823393916664716167606840079925284290960
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @  18764096 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
  UVM_INFO @  18764096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.i2c_csr_mem_rw_with_rand_reset.42336591316007171409248356291668804872722211905131840379231548580545893607720
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @   2101467 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0
  UVM_INFO @   2101467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.acq_fifo_next_data.acq_fifo_next_data reset value: * has 5 failures:

Test i2c_csr_rw has 4 failures.

6.i2c_csr_rw.51159390939677556732243089898395972847006374361831241985057166212104305173731
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_csr_rw/latest/run.log

  UVM_ERROR @   3360993 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data.acq_fifo_next_data reset value: 0x0
  UVM_INFO @   3360993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.i2c_csr_rw.7685446723700036265602703945825325165078703700367720470193730561164216412825
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_csr_rw/latest/run.log

  UVM_ERROR @   3229653 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data.acq_fifo_next_data reset value: 0x0
  UVM_INFO @   3229653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test i2c_csr_mem_rw_with_rand_reset has 1 failures.

7.i2c_csr_mem_rw_with_rand_reset.112088187230024503760478026841428916174386983319783786744825846976071061696911
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @   5605039 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data.acq_fifo_next_data reset value: 0x0
  UVM_INFO @   5605039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 3 failures:
- Test i2c_target_stress_all has 1 failures.
  - 8.i2c_target_stress_all.92813626352133157942623119790676748302368343708514824197395704997651642744913
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 2340417588 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (3 [0x3] vs 1 [0x1])
  UVM_INFO @ 2340417588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 12.i2c_target_stress_all_with_rand_reset.61886665253777317501612332139368874559432288529076846496260130972153176952563
    Line 406, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 61783414260 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (13 [0xd] vs 6 [0x6])
  UVM_INFO @ 61783414260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.i2c_target_stress_all_with_rand_reset.83733808006750866918549441888724055179943546042132413266858772183668715409691
    Line 287, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10833799881 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (23 [0x17] vs 21 [0x15])
  UVM_INFO @ 10833799881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred! has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 3 failures.
  - 8.i2c_target_stress_all_with_rand_reset.26158820075959162601785823147018760844404446472806634126878061303262644200962
    Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 15174814538 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 15174814538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.i2c_target_stress_all_with_rand_reset.5605905465956171778050500923042159342171771066868542800127041569059441393265
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10781957163 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 10781957163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 3 failures:
- Test i2c_target_perf has 1 failures.
  - 33.i2c_target_perf.10685315643393636342564454624490916441507201561106127108271396832926016509368
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_perf/latest/run.log
```
  UVM_ERROR @ 215573612 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 215573612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 34.i2c_target_stress_all_with_rand_reset.112945823347518487247596358213171015192613139436017975487187644694345634244926
    Line 330, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28954520803 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 28954520803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.i2c_target_stress_all_with_rand_reset.81402622903393157491786395057760033425458518130860518523869671218248983473150
    Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2673591618 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 2673591618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 23.i2c_target_stress_all_with_rand_reset.45323330204876759026747946283539764942478290454647258592459167937894272895431
    Line 325, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16144953784 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (58 [0x3a] vs 246 [0xf6])
  UVM_INFO @ 16144953784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.i2c_target_stress_all_with_rand_reset.94682233770389114319128762695654730243446197642854899773348705536530443605024
    Line 348, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26165754829 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (199 [0xc7] vs 132 [0x84])
  UVM_INFO @ 26165754829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 30.i2c_target_stress_all_with_rand_reset.16697351287131326729879457987675337655374454998754355517872437109807950869078
    Line 355, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 34230598408 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x6a096214) == 0x0
  UVM_INFO @ 34230598408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.i2c_target_stress_all_with_rand_reset.54369316531502124568660954052241891050337673563136099838003671001434702988021
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11318394772 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x8b93f994) == 0x0
  UVM_INFO @ 11318394772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.acq_fifo_next_data reset value: * Wrote i2c_reg_block.acq_fifo_next_data[*]: * has 1 failures:
- Test i2c_csr_bit_bash has 1 failures.
  - 1.i2c_csr_bit_bash.109005591374465788837822007122727466237548230150747368003851263241356817942259
    Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_csr_bit_bash/latest/run.log
```
  UVM_ERROR @ 1358285171 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0 Wrote i2c_reg_block.acq_fifo_next_data[0]: 1
  UVM_INFO @ 1358285171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_host_perf_vseq.sv:206) virtual_sequencer [i2c_host_perf_vseq] DUT not working as expected has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 12.i2c_host_stress_all_with_rand_reset.40208143364850644255744787633999086885160655917910755903755851843737196314390
    Line 4276, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 46738654704 ps: (i2c_host_perf_vseq.sv:206) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_host_perf_vseq] DUT not working as expected
  UVM_INFO @ 46738654704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:503) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
- Test i2c_same_csr_outstanding has 1 failures.
  - 13.i2c_same_csr_outstanding.79601503846466845968900274285235850976386087059116419904954344993386942297680
    Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @  26175407 ps: (cip_base_vseq.sv:503) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @  26175407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 20.i2c_host_stress_all_with_rand_reset.78397966644550817631563044980161701185293577782971211574237762159090371492341
    Line 9670, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36115253136 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  direction  READ item mismatch!
  --> EXP:
  -----------------------------------------------
  Name              Type          Size  Value
```