9f20940d49| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.780m | 4.399ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 56.370s | 1.543ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 1.120s | 45.862us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 1.200s | 20.696us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.610s | 1.033ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.520s | 157.465us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 2.260s | 36.896us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 1.200s | 20.696us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.520s | 157.465us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 12.000s | 261.454us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 53.374m | 52.926ms | 18 | 50 | 36.00 |
| V2 | host_maxperf | i2c_host_perf | 56.885m | 27.678ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 1.120s | 30.219us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.141m | 19.871ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.730m | 42.336ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.100s | 161.900us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 28.750s | 511.026us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 16.650s | 581.113us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.806m | 47.389ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 52.720s | 4.280ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 13.070s | 976.384us | 20 | 50 | 40.00 |
| V2 | target_glitch | i2c_target_glitch | 12.920s | 7.687ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 35.086m | 73.323ms | 49 | 50 | 98.00 |
| V2 | target_maxperf | i2c_target_perf | 10.930s | 4.469ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.391m | 7.685ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 12.850s | 2.037ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 2.760s | 509.253us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 3.250s | 314.012us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 42.010m | 68.084ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.391m | 7.685ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 9.569m | 22.810ms | 49 | 50 | 98.00 | ||
| V2 | target_timeout | i2c_target_timeout | 12.430s | 6.018ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 1.526m | 2.131ms | 41 | 50 | 82.00 |
| V2 | bad_address | i2c_target_bad_addr | 11.950s | 11.738ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 53.520s | 10.228ms | 26 | 50 | 52.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 5.540s | 14.169ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 2.470s | 489.406us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 56.885m | 27.678ms | 49 | 50 | 98.00 |
| i2c_host_perf_precise | 4.056m | 24.817ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 52.720s | 4.280ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 11.530s | 617.980us | 49 | 50 | 98.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 6.230s | 1.150ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 5.130s | 2.113ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 2.760s | 806.874us | 34 | 50 | 68.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 33.570s | 737.384us | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 4.500s | 1.745ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 1.040s | 27.238us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 1.140s | 25.613us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.990s | 520.852us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.990s | 520.852us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 1.120s | 45.862us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.200s | 20.696us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.520s | 157.465us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.770s | 61.428us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 1.120s | 45.862us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.200s | 20.696us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.520s | 157.465us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.770s | 61.428us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1676 | 1792 | 93.53 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 3.260s | 158.030us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.400s | 107.132us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 3.260s | 158.030us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 9.201m | 23.482ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.940s | 225.718us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 9.177m | 64.484ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1856 | 2042 | 90.89 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 28 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.27 | 97.27 | 89.61 | 97.22 | 72.02 | 94.33 | 98.44 | 90.00 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 42 failures:
1.i2c_host_mode_toggle.15386826704307381181312456597584751580588990626104697599146964273138030119965
Line 72, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 287169094 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @18244
4.i2c_host_mode_toggle.34792729944857969867662912453206812362948892170373835031189390606878005328285
Line 72, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 734538612 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @71852
... and 15 more failures.
3.i2c_host_stress_all.63021038442685974334626906150475552617452810668818030985898520921140863066051
Line 177, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 13930704702 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @1069163
4.i2c_host_stress_all.34452738227236395133399185111576331379509685335323134817560740690783444892271
Line 240, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 24219524488 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @22176849
... and 23 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 32 failures:
0.i2c_target_unexp_stop.18604531147387231439016714358747322053869590673911812905552431955463537169722
Line 65, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 472013869 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 148 [0x94])
UVM_INFO @ 472013869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.13999198563880662075984064235712755686268324175682497409830196024558984113
Line 65, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1409032332 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 218 [0xda])
UVM_INFO @ 1409032332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 28 more failures.
5.i2c_target_stress_all_with_rand_reset.12045086253308865592884575805494800724693837243941876557879597259822998755994
Line 122, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 56657598622 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 243 [0xf3])
UVM_INFO @ 56657598622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all_with_rand_reset.23469578987239058768690710433924312295140959271160919909529075464432458421806
Line 338, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 64483992698 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 155 [0x9b])
UVM_INFO @ 64483992698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 24 failures:
0.i2c_target_hrst.54079584046943302259407308170111547177091001643283058637693531625566097786615
Line 66, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 11182935525 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 11182935525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_hrst.14785962831404533649206972256959823964727933866971414537708299228649846503953
Line 66, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10146675124 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10146675124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 16 failures:
0.i2c_target_nack_txstretch.93631359685291249459543546631647851598589250295178610506001491845435439923668
Line 65, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 150166235 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 150166235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_nack_txstretch.5915478367683119144238324021696972760952779714510444084855095839246187642416
Line 65, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 1334449154 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 1334449154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 16 failures:
3.i2c_target_unexp_stop.81706733503019778603294349024491933391458706118096672012102569791066883787481
Line 65, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 44880132 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 44880132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_unexp_stop.69323566213037825856089398693075749192519713524412724125818149252076073816034
Line 65, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 372741332 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 372741332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
0.i2c_host_stress_all_with_rand_reset.39032525195502504803438034288081416848662249241811443354288980423679878277435
Line 124, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 22702489499 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 22702489499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.55846647739269576057648121555155560368035378469023914609514013967577452133743
Line 192, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6873897734 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6873897734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
0.i2c_target_stress_all_with_rand_reset.106364973622604349567021852278104214822685404439608003609791530970741012506609
Line 129, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 32042128599 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 32042128599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.58207347109395867199656218326112939057531676981862960250019451955099118542721
Line 74, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3068147524 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3068147524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 11 failures:
0.i2c_host_mode_toggle.1320719631441464588690410206849013642830566121699235784788495570587648307712
Line 74, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 250224207 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
2.i2c_host_mode_toggle.73503144949987492054788805662401398222012129515268139337252630112247277434128
Line 74, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 214669935 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 9 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 9 failures:
8.i2c_target_stretch.30822457693509699160664233909847964510069948799670852578644105128004116684547
Line 65, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10007836381 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10007836381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.i2c_target_stretch.43038748047508323517933899786849824286587286209125816877781933611176212448154
Line 65, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10002943633 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10002943633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Job timed out after * minutes has 7 failures:
Test i2c_target_stress_all_with_rand_reset has 2 failures.
2.i2c_target_stress_all_with_rand_reset.62747163215300170344270989248654200752782499526429798845432005596426490435543
Log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
Job timed out after 20 minutes
3.i2c_target_stress_all_with_rand_reset.31699188362581123869983963497322378852035428782980427226698785809700887047705
Log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
Job timed out after 20 minutes
Test i2c_host_perf has 1 failures.
6.i2c_host_perf.101531600560513176666718798696220414259104138306081469946487081216556353282053
Log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_host_perf/latest/run.log
Job timed out after 60 minutes
Test i2c_host_stress_all has 3 failures.
10.i2c_host_stress_all.14820358014514304000108423451962865116366025314579976244305257551243348230366
Log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
33.i2c_host_stress_all.114241225513849518830998262132420457494982294934939946885011096646751786288323
Log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
... and 1 more failures.
Test i2c_target_stress_all has 1 failures.
29.i2c_target_stress_all.98236249449096085727342892226106327479272100229625714248858413830917876250889
Log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_target_stress_all/latest/run.log
Job timed out after 60 minutes
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 4 failures:
2.i2c_host_stress_all.112516906981008858298355551861542245475586301539323213737511964467598929489301
Line 249, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 7661795176 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @7592505
5.i2c_host_stress_all.71292432198090348541294433398914874200929049039971509534608642248171113700065
Line 155, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 62819018163 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @18496987
... and 2 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 4 failures:
4.i2c_target_unexp_stop.8284620912853698706831097714709035250327781365077375069094784900565343281455
Line 66, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 255368020 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 255368020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.i2c_target_unexp_stop.98815217451868001183437788882925353870296590878852624545801960511701421044959
Line 66, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 414795483 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 414795483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
Test i2c_target_tx_stretch_ctrl has 1 failures.
6.i2c_target_tx_stretch_ctrl.37992210432613450080840409417744693143451555195741067499325483409861721021026
Line 117, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_fifo_watermarks_tx has 1 failures.
16.i2c_target_fifo_watermarks_tx.9391411505640719088316830562918070179238966748402131744192398871067193048676
Line 108, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
3.i2c_host_mode_toggle.6381504682256388785248460513840170512926109317417471891615646734244999377742
Line 66, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 104626467 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x8e7df814, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 104626467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:755) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
4.i2c_target_stress_all_with_rand_reset.38154923789410403902195262093350853971756809878391379070886604767458441400647
Line 72, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 568322025 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 568322025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
8.i2c_host_stress_all_with_rand_reset.105562082777755543067911892129652335682991111329507875446498655905383459061662
Line 216, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 100301749183 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (10 [0xa] vs 3 [0x3])
UVM_INFO @ 100301749183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access has 1 failures:
11.i2c_host_mode_toggle.62028567823943715995391826844134389963958587017856919803645213065568809633444
Line 73, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
41.i2c_target_intr_stress_wr.58098715843356793692654229601296468678279618446068260443281024456290678429083
Line 65, in log /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 31219527433 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 31219527433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---