12e3b8572e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.883m | 8.558ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 48.420s | 4.653ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 1.260s | 35.293us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 1.250s | 20.232us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 7.300s | 4.327ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.650s | 96.781us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 2.160s | 100.851us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 1.250s | 20.232us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.650s | 96.781us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 10.740s | 199.942us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 58.790m | 230.442ms | 18 | 50 | 36.00 |
| V2 | host_maxperf | i2c_host_perf | 54.111m | 70.202ms | 48 | 50 | 96.00 |
| V2 | host_override | i2c_host_override | 1.160s | 28.357us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 5.759m | 4.405ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.118m | 2.497ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.360s | 312.861us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 37.230s | 535.999us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 17.200s | 446.677us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.130m | 32.554ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 52.010s | 4.236ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 12.350s | 511.040us | 19 | 50 | 38.00 |
| V2 | target_glitch | i2c_target_glitch | 17.880s | 3.530ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 34.128m | 84.156ms | 49 | 50 | 98.00 |
| V2 | target_maxperf | i2c_target_perf | 10.280s | 3.057ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.628m | 7.097ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 16.810s | 6.510ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 3.620s | 313.914us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 3.210s | 257.477us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 23.782m | 68.162ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.628m | 7.097ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 6.111m | 24.282ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 15.010s | 1.457ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 1.828m | 2.808ms | 41 | 50 | 82.00 |
| V2 | bad_address | i2c_target_bad_addr | 14.660s | 6.768ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 1.119m | 10.015ms | 22 | 50 | 44.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 5.930s | 6.396ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 2.770s | 598.602us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 54.111m | 70.202ms | 48 | 50 | 96.00 |
| i2c_host_perf_precise | 9.829m | 24.223ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 52.010s | 4.236ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 19.950s | 1.017ms | 44 | 50 | 88.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 6.040s | 613.326us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 5.480s | 1.105ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 3.030s | 4.086ms | 28 | 50 | 56.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 26.160s | 984.754us | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 5.090s | 601.219us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 1.070s | 26.223us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 1.200s | 19.764us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 4.380s | 125.052us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 4.380s | 125.052us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 1.260s | 35.293us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.250s | 20.232us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.650s | 96.781us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.870s | 53.008us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 1.260s | 35.293us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.250s | 20.232us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.650s | 96.781us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.870s | 53.008us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1659 | 1792 | 92.58 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 3.740s | 147.974us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.490s | 163.286us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 3.740s | 147.974us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 59.950s | 823.858us | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 4.290s | 1.588ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 39.300s | 1.078ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1839 | 2042 | 90.06 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 28 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.39 | 97.29 | 89.69 | 97.22 | 72.62 | 94.37 | 98.47 | 90.11 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 37 failures:
0.i2c_host_stress_all.56526142398031737278670314911074552796566737383859204377375767976129399801856
Line 204, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 58461286949 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @13422387
1.i2c_host_stress_all.46663945245868981419580328603255950245059254399996541823794449371183082742429
Line 200, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 108396271306 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @15541029
... and 24 more failures.
4.i2c_host_mode_toggle.37079686383008410645819341446250168931306533640974276068459758409612249509998
Line 72, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 199759877 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @24002
7.i2c_host_mode_toggle.4452510242416591465348697603235388212174157146682437572349796528440719630361
Line 72, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 101262670 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @7904
... and 9 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 35 failures:
0.i2c_target_unexp_stop.37043442506560727942898008455616413463360297373029526077762489794468238153314
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 497701154 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 250 [0xfa])
UVM_INFO @ 497701154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.54312135182498153507040536055878739817097132837915926616417265331066382754929
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 174377068 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 78 [0x4e])
UVM_INFO @ 174377068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 32 more failures.
8.i2c_target_stress_all_with_rand_reset.1446006761040545722511827404981103997354951803588211600978455413383535542735
Line 98, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2790476625 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (11 [0xb] vs 0 [0x0])
UVM_INFO @ 2790476625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 28 failures:
0.i2c_target_hrst.642737596638494735271612007056565597084931403311830187767059528367079406141
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10162413362 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10162413362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_hrst.22422479221440302318975150137548877686144688864415248435341445607436388250259
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10012885112 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10012885112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 22 failures:
0.i2c_target_nack_txstretch.38495780428229922752160425744349800872881099364841472555722109046634062764554
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 2554666152 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 2554666152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_nack_txstretch.84629461765072801374690663762387963197948926841925502828627625441999553080081
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 403530686 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 403530686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 20 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
0.i2c_host_stress_all_with_rand_reset.39920000498907618747653716564545383924045675537132994323456777420120983858671
Line 75, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1609155167 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1609155167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.59666722341210885382626915799449461663692431276001936881330399467154751162221
Line 83, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 206862894 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 206862894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.41188157923236632638497617317975527144646805714744121604947941230361902780369
Line 80, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7915715543 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7915715543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.30538178296574405543794100434528478374117737119728627291664107757849134470850
Line 103, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2968473260 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2968473260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 13 failures:
0.i2c_host_mode_toggle.34671255096349922771243904802307930713477955892724666444967624147236612551480
Line 74, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 207357115 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
12.i2c_host_mode_toggle.66215447291484667046012062535463200687284131717260108320123074453860707941413
Line 74, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 272265414 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 10 more failures.
26.i2c_host_perf.98677690567586179569465508858978053148365226483459470546603681959539823361372
Line 69, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_host_perf/latest/run.log
UVM_ERROR @ 8396140282 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 11 failures:
4.i2c_target_unexp_stop.31693976266680934085110706602338789660616640677429599556024629582695801364640
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 174021312 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 174021312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_unexp_stop.95531405067396163205578985768057321638672974702898516051226775143949769573515
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 66222139 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 66222139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 9 failures:
4.i2c_target_stretch.32546273476287747802832858181414591259489708609593412420134583719996957951148
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10005163863 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10005163863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_target_stretch.87722444986903120583072495939049284011995767716361519737408947990905597892115
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10004791390 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10004791390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 7 failures:
2.i2c_target_tx_stretch_ctrl.67533047422236802071634376334195471270655821385311442798755450588999888869310
Line 111, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
8.i2c_target_tx_stretch_ctrl.38760104559155983536954868178808371087022576210087065020801071786010468460512
Line 111, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 4 more failures.
49.i2c_target_fifo_watermarks_tx.6225306111503910386466264236243923109976914132268262473269325658836699955967
Line 108, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 7 failures:
5.i2c_host_mode_toggle.64653901958869980907450655518017987315639381136250010238980128124924838516425
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 86889497 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xb5292e94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 86889497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_host_mode_toggle.35391860996326697494419935328570640412620239305119018808917183510903386102161
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 103307935 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xb2155994, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 103307935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 5 failures:
2.i2c_target_unexp_stop.109092880327647994677812407300861981306234104695365169986819654762516313094932
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 445372274 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 445372274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_unexp_stop.95736860863148961612799729838356651784733025706365186552961058079351355374199
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 384385815 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 384385815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 4 failures:
9.i2c_host_stress_all.84203803545966998913638914759248800157375549067273322210798771685363255265122
Line 118, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 41424383673 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @5219921
37.i2c_host_stress_all.81343061431631217018520318165611041758798420876272636619865868892594280213453
Line 114, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 5627339976 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @1107411
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:771) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
1.i2c_target_stress_all_with_rand_reset.108650501570488560957240519820706545238166828484784872455698808091401832234030
Line 82, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1139017014 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1139017014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all_with_rand_reset.110426094031164317932091268596391261023148602240038643083082448775989511310962
Line 74, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1613352957 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1613352957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test i2c_host_stress_all has 1 failures.
12.i2c_host_stress_all.51691665978261602823065031513226997736380253133958619475819969632668265355544
Line 78, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_host_perf has 1 failures.
17.i2c_host_perf.29886650491872750787265901304473708795814690301244177409892556010774127119285
Line 67, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_host_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
5.i2c_target_stress_all_with_rand_reset.87116718278153016048634111447327109296256720415297389071283573982470455787523
Line 133, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3112551953 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 3112551953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:501) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
15.i2c_same_csr_outstanding.86158549812099535664358148595301167849466724955872265344830210522157982682283
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 674448030 ps: (cip_base_vseq.sv:501) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 674448030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access has 1 failures:
25.i2c_host_mode_toggle.79439072584295408982909777166283676669483177372345334078737783536074994244093
Line 73, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
Job timed out after * minutes has 1 failures:
46.i2c_host_stress_all.89669810264357375829028924046605537388661324652794718083611136397303228773175
Log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
48.i2c_target_stress_all.9372924987833578665322920913900968183045156528674310350193714634993743516771
Line 92, in log /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 39155705001 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 39155705001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---