I2C Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: `877a77116`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	2.384m	2.587ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	53.450s	8.966ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.680s	22.120us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.780s	30.168us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.210s	428.118us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.250s	124.013us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.400s	247.148us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.780s	30.168us	20	20	100.00
		i2c_csr_aliasing	1.250s	124.013us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	17.150s	1.551ms	48	50	96.00
V2	host_stress_all	i2c_host_stress_all	47.185m	218.559ms	32	50	64.00
V2	host_perf	i2c_host_perf	41.644m	52.722ms	46	50	92.00
V2	host_override	i2c_host_override	0.680s	18.627us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	13.313m	24.812ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	16.354m	6.923ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.210s	270.728us	50	50	100.00
		i2c_host_fifo_fmt_empty	29.160s	3.051ms	49	50	98.00
		i2c_host_fifo_reset_rx	15.860s	531.510us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	4.897m	12.928ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	53.020s	5.695ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample	4.158m	2.796ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.558m	18.428ms	50	50	100.00
V2	target_error_intr	i2c_target_unexp_stop	9.690s	18.000ms	50	50	100.00
V2	target_glitch	i2c_target_glitch	3.740s	839.077us	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	44.985m	40.878ms	40	50	80.00
V2	target_perf	i2c_target_perf	5.740s	12.108ms	50	50	100.00
V2	target_fifo_overflow	i2c_target_tx_ovf	5.041m	13.701ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.311m	2.121ms	50	50	100.00
		i2c_target_intr_smoke	8.750s	8.417ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.199m	10.160ms	50	50	100.00
		i2c_target_fifo_reset_tx	1.349m	10.113ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	58.978m	55.054ms	47	50	94.00
		i2c_target_stress_rd	1.311m	2.121ms	50	50	100.00
		i2c_target_intr_stress_wr	23.855m	26.006ms	49	50	98.00
V2	target_timeout	i2c_target_timeout	8.840s	12.241ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	51.551m	37.900ms	45	50	90.00
V2	bad_address	i2c_target_bad_addr	6.090s	6.810ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	3.310s	763.751us	50	50	100.00
V2	alert_test	i2c_alert_test	0.690s	56.132us	50	50	100.00
V2	intr_test	i2c_intr_test	0.720s	21.920us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.600s	135.214us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.600s	135.214us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.680s	22.120us	5	5	100.00
		i2c_csr_rw	0.780s	30.168us	20	20	100.00
		i2c_csr_aliasing	1.250s	124.013us	5	5	100.00
		i2c_same_csr_outstanding	0.970s	39.574us	19	20	95.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.680s	22.120us	5	5	100.00
		i2c_csr_rw	0.780s	30.168us	20	20	100.00
		i2c_csr_aliasing	1.250s	124.013us	5	5	100.00
		i2c_same_csr_outstanding	0.970s	39.574us	19	20	95.00
V2		TOTAL			1447	1492	96.98
V2S	tl_intg_err	i2c_tl_intg_err	1.890s	108.459us	20	20	100.00
		i2c_sec_cm	0.920s	77.916us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.890s	108.459us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	19.772m	13.789ms	7	50	14.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	0.800s	31.622us	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			7	100	7.00
		TOTAL			1634	1772	92.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	32	32	23	71.88
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.00	99.22	96.60	100.00	71.23	97.90	100.00	93.07

Failure Buckets

Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 78 failures:
- Test i2c_host_stress_all_with_rand_reset has 41 failures.
  - 0.i2c_host_stress_all_with_rand_reset.3173865077
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:bc1b7437-f4db-4e79-812e-9b111b3a81b6
```
  - 2.i2c_host_stress_all_with_rand_reset.1736547185
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:d9e37847-03b5-4375-9dd9-fbee77a7dbcf
```
  - ... and 39 more failures.
- Test i2c_host_perf has 3 failures.
  - 2.i2c_host_perf.1913837580
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_perf/latest/run.log
```
  Job ID: smart:29c675db-28e1-4eab-962d-0da9ca963c88
```
  - 31.i2c_host_perf.2805004466
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_host_perf/latest/run.log
```
  Job ID: smart:b54c0a31-8f2e-47d3-b3a3-e5255341f9df
```
  - ... and 1 more failures.
- Test i2c_target_stretch has 5 failures.
  - 2.i2c_target_stretch.4125865658
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stretch/latest/run.log
```
  Job ID: smart:416f0cb0-a860-4c9f-9451-734cedcedcd3
```
  - 6.i2c_target_stretch.3777828883
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stretch/latest/run.log
```
  Job ID: smart:7649a73d-0d62-4141-a881-f625e024aeee
```
  - ... and 3 more failures.
- Test i2c_host_stress_all has 16 failures.
  - 3.i2c_host_stress_all.3746278554
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:050f5fdd-5437-4a84-a012-3116f25eec4b
```
  - 4.i2c_host_stress_all.2713653436
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:d5dffc92-8d16-463c-8d35-f0632f01e011
```
  - ... and 14 more failures.
- Test i2c_target_stress_all has 9 failures.
  - 4.i2c_target_stress_all.1326662152
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:5f317a43-a267-444e-a5d7-de5f2d1c999a
```
  - 8.i2c_target_stress_all.1599537549
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:7501297b-6d16-4fad-92a0-297af13de2c4
```
  - ... and 7 more failures.
- ... and 2 more tests.

UVM_FATAL (i2c_driver.sv:183) driver [driver] has 50 failures:

Test i2c_target_stress_all_with_rand_reset has 50 failures.

0.i2c_target_stress_all_with_rand_reset.3767614571
Line 223, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @   2596854 ps: (i2c_driver.sv:183) uvm_test_top.env.m_i2c_agent.driver [uvm_test_top.env.m_i2c_agent.driver]
    device_driver, received invalid request
  UVM_INFO @   2596854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_stress_all_with_rand_reset.1801829267
Line 223, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  22380840 ps: (i2c_driver.sv:183) uvm_test_top.env.m_i2c_agent.driver [uvm_test_top.env.m_i2c_agent.driver]
    device_driver, received invalid request
  UVM_INFO @  22380840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 48 more failures.

UVM_ERROR (i2c_host_perf_vseq.sv:168) virtual_sequencer [i2c_host_perf_vseq] DUT not working as expected has 3 failures:

Test i2c_host_stress_all has 2 failures.

17.i2c_host_stress_all.1744917842
Line 2160, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 54211745496 ps: (i2c_host_perf_vseq.sv:168) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_host_perf_vseq] DUT not working as expected
  UVM_INFO @ 54211745496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.i2c_host_stress_all.2738658059
Line 235, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 5654402524 ps: (i2c_host_perf_vseq.sv:168) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_host_perf_vseq] DUT not working as expected
  UVM_INFO @ 5654402524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_host_perf has 1 failures.

24.i2c_host_perf.1113914607
Line 227, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_host_perf/latest/run.log

  UVM_ERROR @ 783442268 ps: (i2c_host_perf_vseq.sv:168) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_host_perf_vseq] DUT not working as expected
  UVM_INFO @ 783442268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (i2c_scoreboard.sv:698) scoreboard [scoreboard] has 2 failures:

Test i2c_host_error_intr has 2 failures.

1.i2c_host_error_intr.1997837271
Line 1144, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 293865770 ps: (i2c_scoreboard.sv:698) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  direction WRITE item mismatch!
  --> EXP:
  ------------------------------------------------
  Name              Type          Size  Value

26.i2c_host_error_intr.4278744600
Line 1030, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 720507208 ps: (i2c_scoreboard.sv:698) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  direction WRITE item mismatch!
  --> EXP:
  ------------------------------------------------
  Name              Type          Size  Value

Offending 'scl_i' has 2 failures:

Test i2c_host_stress_all_with_rand_reset has 2 failures.

28.i2c_host_stress_all_with_rand_reset.2357606701
Line 11572, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_host_stress_all_with_rand_reset/latest/run.log

      Offending 'scl_i'
  UVM_ERROR @ 296326720744 ps: (i2c_fsm.sv:1343) [ASSERT FAILED] SclInputGlitch_A
  UVM_INFO @ 296326720744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

32.i2c_host_stress_all_with_rand_reset.3873451795
Line 4333, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_host_stress_all_with_rand_reset/latest/run.log

      Offending 'scl_i'
  UVM_ERROR @ 89450064430 ps: (i2c_fsm.sv:1343) [ASSERT FAILED] SclInputGlitch_A
  UVM_INFO @ 89450064430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:483) [i2c_common_vseq] Check failed data == * (* [*] vs * [*]) has 1 failures:
- Test i2c_same_csr_outstanding has 1 failures.
  - 5.i2c_same_csr_outstanding.1034108068
    Line 217, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @  15977406 ps: (cip_base_vseq.sv:483) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @  15977406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_host_fifo_fmt_empty has 1 failures.
  - 18.i2c_host_fifo_fmt_empty.3119717286
    Line 977, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_host_fifo_fmt_empty/latest/run.log
```
  UVM_FATAL @ 10000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_if.sv:314) [i2c_if] Cannot begin host_stop when both scl and sda are high has 1 failures:
- Test i2c_target_stress_all has 1 failures.
  - 48.i2c_target_stress_all.3218625415
    Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 30181963147 ps: (i2c_if.sv:314) [i2c_if] Cannot begin host_stop when both scl and sda are high
  UVM_INFO @ 30181963147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```