I2C Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: 877a77116

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 host_smoke i2c_host_smoke 2.384m 2.587ms 50 50 100.00
V1 target_smoke i2c_target_smoke 53.450s 8.966ms 50 50 100.00
V1 csr_hw_reset i2c_csr_hw_reset 0.680s 22.120us 5 5 100.00
V1 csr_rw i2c_csr_rw 0.780s 30.168us 20 20 100.00
V1 csr_bit_bash i2c_csr_bit_bash 4.210s 428.118us 5 5 100.00
V1 csr_aliasing i2c_csr_aliasing 1.250s 124.013us 5 5 100.00
V1 csr_mem_rw_with_rand_reset i2c_csr_mem_rw_with_rand_reset 1.400s 247.148us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr i2c_csr_rw 0.780s 30.168us 20 20 100.00
i2c_csr_aliasing 1.250s 124.013us 5 5 100.00
V1 TOTAL 155 155 100.00
V2 host_error_intr i2c_host_error_intr 17.150s 1.551ms 48 50 96.00
V2 host_stress_all i2c_host_stress_all 47.185m 218.559ms 32 50 64.00
V2 host_perf i2c_host_perf 41.644m 52.722ms 46 50 92.00
V2 host_override i2c_host_override 0.680s 18.627us 50 50 100.00
V2 host_fifo_watermark i2c_host_fifo_watermark 13.313m 24.812ms 50 50 100.00
V2 host_fifo_overflow i2c_host_fifo_overflow 16.354m 6.923ms 50 50 100.00
V2 host_fifo_reset i2c_host_fifo_reset_fmt 1.210s 270.728us 50 50 100.00
i2c_host_fifo_fmt_empty 29.160s 3.051ms 49 50 98.00
i2c_host_fifo_reset_rx 15.860s 531.510us 50 50 100.00
V2 host_fifo_full i2c_host_fifo_full 4.897m 12.928ms 50 50 100.00
V2 host_timeout i2c_host_stretch_timeout 53.020s 5.695ms 50 50 100.00
V2 host_rx_oversample i2c_host_rx_oversample 4.158m 2.796ms 50 50 100.00
V2 i2c_host_mode_toggle i2c_host_mode_toggle 2.558m 18.428ms 50 50 100.00
V2 target_error_intr i2c_target_unexp_stop 9.690s 18.000ms 50 50 100.00
V2 target_glitch i2c_target_glitch 3.740s 839.077us 2 2 100.00
V2 target_stress_all i2c_target_stress_all 44.985m 40.878ms 40 50 80.00
V2 target_perf i2c_target_perf 5.740s 12.108ms 50 50 100.00
V2 target_fifo_overflow i2c_target_tx_ovf 5.041m 13.701ms 50 50 100.00
V2 target_fifo_empty i2c_target_stress_rd 1.311m 2.121ms 50 50 100.00
i2c_target_intr_smoke 8.750s 8.417ms 50 50 100.00
V2 target_fifo_reset i2c_target_fifo_reset_acq 1.199m 10.160ms 50 50 100.00
i2c_target_fifo_reset_tx 1.349m 10.113ms 50 50 100.00
V2 target_fifo_full i2c_target_stress_wr 58.978m 55.054ms 47 50 94.00
i2c_target_stress_rd 1.311m 2.121ms 50 50 100.00
i2c_target_intr_stress_wr 23.855m 26.006ms 49 50 98.00
V2 target_timeout i2c_target_timeout 8.840s 12.241ms 50 50 100.00
V2 target_clock_stretch i2c_target_stretch 51.551m 37.900ms 45 50 90.00
V2 bad_address i2c_target_bad_addr 6.090s 6.810ms 50 50 100.00
V2 target_mode_glitch i2c_target_hrst 3.310s 763.751us 50 50 100.00
V2 alert_test i2c_alert_test 0.690s 56.132us 50 50 100.00
V2 intr_test i2c_intr_test 0.720s 21.920us 50 50 100.00
V2 tl_d_oob_addr_access i2c_tl_errors 2.600s 135.214us 20 20 100.00
V2 tl_d_illegal_access i2c_tl_errors 2.600s 135.214us 20 20 100.00
V2 tl_d_outstanding_access i2c_csr_hw_reset 0.680s 22.120us 5 5 100.00
i2c_csr_rw 0.780s 30.168us 20 20 100.00
i2c_csr_aliasing 1.250s 124.013us 5 5 100.00
i2c_same_csr_outstanding 0.970s 39.574us 19 20 95.00
V2 tl_d_partial_access i2c_csr_hw_reset 0.680s 22.120us 5 5 100.00
i2c_csr_rw 0.780s 30.168us 20 20 100.00
i2c_csr_aliasing 1.250s 124.013us 5 5 100.00
i2c_same_csr_outstanding 0.970s 39.574us 19 20 95.00
V2 TOTAL 1447 1492 96.98
V2S tl_intg_err i2c_tl_intg_err 1.890s 108.459us 20 20 100.00
i2c_sec_cm 0.920s 77.916us 5 5 100.00
V2S sec_cm_bus_integrity i2c_tl_intg_err 1.890s 108.459us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 host_stress_all_with_rand_reset i2c_host_stress_all_with_rand_reset 19.772m 13.789ms 7 50 14.00
V3 target_stress_all_with_rand_reset i2c_target_stress_all_with_rand_reset 0.800s 31.622us 0 50 0.00
V3 target_loopback 0 0 --
V3 TOTAL 7 100 7.00
TOTAL 1634 1772 92.21

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 32 32 23 71.88
V2S 2 2 2 100.00
V3 3 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.00 99.22 96.60 100.00 71.23 97.90 100.00 93.07

Failure Buckets

Past Results