Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

216168

1

T7

172

T8

512

T10

88

ack

18051

1

T7

19

T8

3

T9

40

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	834	1			T8	2		T10	1		T11	7
high	47807	1			T7	52		T8	103		T9	2
med	87105	1			T7	67		T8	217		T9	6
sml	97543	1			T7	72		T8	192		T9	32
all_zero	930	1			T8	1		T11	9		T41	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117036

1

T7

104

T8

267

T9

18

auto[1]

117183

1

T7

87

T8

248

T9

22

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

159975

1

T7

125

T8

347

T9

23

auto[1]

74244

1

T7

66

T8

168

T9

17

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

223928

1

T7

191

T8

512

T9

12

auto[1]

10291

1

T8

3

T9

28

T10

10

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

221054

1

T7

172

T8

512

T9

28

auto[1]

13165

1

T7

19

T8

3

T9

12

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

222732

1

T7

172

T8

514

T9

29

auto[1]

11487

1

T7

19

T8

1

T9

11

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117036

1

T7

104

T8

267

T9

18

auto[1]

117183

1

T7

87

T8

248

T9

22

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

159975

1

T7

125

T8

347

T9

23

auto[1]

74244

1

T7

66

T8

168

T9

17

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

223928

1

T7

191

T8

512

T9

12

auto[1]

10291

1

T8

3

T9

28

T10

10

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

221054

1

T7

172

T8

512

T9

28

auto[1]

13165

1

T7

19

T8

3

T9

12

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

222732

1

T7

172

T8

514

T9

29

auto[1]

11487

1

T7

19

T8

1

T9

11

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

10

1

T167

1

T168

1

T169

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T170

1

T171

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

5

1

T172

1

T173

1

T174

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

588

1

T10

1

T11

4

T41

5

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

282

1

T10

1

T11

3

T41

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

317

1

T10

2

T11

2

T41

3

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1024

1

T8

1

T10

1

T11

6

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

506

1

T11

1

T41

4

T55

4

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

524

1

T10

1

T11

3

T41

2

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1072

1

T10

1

T11

7

T41

11

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

521

1

T10

1

T11

3

T41

5

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

556

1

T10

1

T11

6

T41

7

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

15

1

T175

1

T176

1

T177

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

6

1

T178

1

T179

1

T180

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

8

1

T175

1

T181

1

T52

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	68238	1			T7	52		T8	185		T10	23
write_address_byte	13165	1			T7	19		T8	3		T9	12
read_with_ack	3612	1			T8	2		T9	17		T11	39
read_with_nack	6679	1			T8	1		T9	11		T10	10
stop_byte	11487	1			T7	19		T8	1		T9	11
write_address_byte_nak	8512	1			T8	2		T10	12		T11	59
data_byte_nack	216168	1			T7	172		T8	512		T10	88
stop_byte_nack	8246	1			T7	19		T8	1		T10	13
nakok_byte_nack	108120	1			T7	76		T8	246		T10	44
nakok_addr_byte_nack	4249	1			T8	1		T10	8		T11	28