Group : tb.dut.u_i2c_protocol_cov::i2c_protocol_cov_cg
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Group : tb.dut.u_i2c_protocol_cov::i2c_protocol_cov_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
91.30 91.30 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_protocol_cov_cg 91.30 1 100 1 64 64



Group Instance : i2c_protocol_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
91.30 1 100 1 64 64



Summary for Group Instance i2c_protocol_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 47 3 44 93.62
Crosses 68 7 61 89.71


Variables for Group Instance i2c_protocol_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
RStart_before_read_data_ACK_cp 1 0 1 100.00 100 1 1 0
RStart_during_address_Ack_cp 1 0 1 100.00 100 1 1 0
RStart_during_address_transmission_cp 1 0 1 100.00 100 1 1 0
RStart_during_read_data_cp 1 0 1 100.00 100 1 1 0
RStart_during_rw_bit_cp 1 1 0 0.00 100 1 1 0
RStart_during_write_data_cp 1 0 1 100.00 100 1 1 0
Read_data_ack_before_stop_cp 1 0 1 100.00 100 1 1 0
Rstart_after_Address_Ack_cp 1 0 1 100.00 100 1 1 0
Rstart_after_Address_Nack_cp 1 0 1 100.00 100 1 1 0
Start_followed_by_Rstart_cp 1 0 1 100.00 100 1 1 2
Stop_after_read_data_Nack_cp 1 0 1 100.00 100 1 1 0
Stop_after_read_data_ack_cp 1 0 1 100.00 100 1 1 0
Stop_after_write_data_Nack_cp 1 0 1 100.00 100 1 1 0
Stop_after_write_data_ack_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_addr_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_data_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_read_cp 1 1 0 0.00 100 1 1 0
Stop_without_ACK_after_write_cp 1 0 1 100.00 100 1 1 0
bus_state_cp 17 1 16 94.12 100 1 1 0
ip_mode_cp 2 0 2 100.00 100 1 1 0
num_rd_bytes_cp 5 0 5 100.00 100 1 1 0
num_wr_bytes_cp 5 0 5 100.00 100 1 1 0


Crosses for Group Instance i2c_protocol_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
bus_state_x_ip_mode_cp 34 3 31 91.18 100 1 1 0
num_rd_bytes_x_ip_mode_cp 10 0 10 100.00 100 1 1 0
num_wr_bytes_x_ip_mode_cp 10 0 10 100.00 100 1 1 0
Stop_after_write_data_ack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Stop_after_read_data_ack_x_ip_mode_cp 2 1 1 50.00 100 1 1 0
Stop_after_write_data_Nack_x_ip_mode_cp 2 1 1 50.00 100 1 1 0
Stop_after_read_data_Nack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Rstart_after_Address_Ack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Rstart_after_Address_Nack_x_ip_mode_cp 2 1 1 50.00 100 1 1 0
Start_followed_by_Rstart_cp_x_ip_mode_cp 2 1 1 50.00 100 1 1 0


Summary for Variable RStart_before_read_data_ACK_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_before_read_data_ACK_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_before_read_data_ACK_Nack 24618 1 T2 23 T3 20 T16 50


Summary for Variable RStart_during_address_Ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_address_Ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Start_during_address_Acknowledge 4 1 T59 2 T60 2


Summary for Variable RStart_during_address_transmission_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_address_transmission_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_during_address_transmission 13 1 T146 1 T147 1 T148 1


Summary for Variable RStart_during_read_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_read_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_during_read_data 850 1 T32 12 T46 5 T47 10


Summary for Variable RStart_during_rw_bit_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for RStart_during_rw_bit_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Start_during_rw_bit 0 1 1


Summary for Variable RStart_during_write_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_write_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_during_write_data 21611 1 T1 19 T2 28 T3 24


Summary for Variable Read_data_ack_before_stop_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Read_data_ack_before_stop_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Read_data_ack_before_stop 386 1 T32 11 T46 4 T47 5


Summary for Variable Rstart_after_Address_Ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Rstart_after_Address_Ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Ack 14 1 T52 1 T149 1 T59 5


Summary for Variable Rstart_after_Address_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Rstart_after_Address_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Rstart_after_Address_Nack 4 1 T59 2 T60 2


Summary for Variable Start_followed_by_Rstart_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for Start_followed_by_Rstart_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
unused 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 10 1 T150 4 T151 2 T152 3


Summary for Variable Stop_after_read_data_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_read_data_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_Nack 18825 1 T2 1 T3 5 T16 20


Summary for Variable Stop_after_read_data_ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_read_data_ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_ack 386 1 T32 11 T46 4 T47 5


Summary for Variable Stop_after_write_data_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_write_data_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
Stop_after_write_data_Nack 1 1 T140 1


Summary for Variable Stop_after_write_data_ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_write_data_ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_ack 12667 1 T2 2 T3 8 T7 18


Summary for Variable Stop_without_ACK_after_addr_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_without_ACK_after_addr_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_without_ACK_after_addr 7 1 T153 1 T154 1 T155 1


Summary for Variable Stop_without_ACK_after_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_without_ACK_after_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_without_ACK_after_data 7589 1 T2 2 T3 8 T16 5


Summary for Variable Stop_without_ACK_after_read_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_without_ACK_after_read_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_without_ACK_after_read 0 1 1


Summary for Variable Stop_without_ACK_after_write_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_without_ACK_after_write_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Stop_without_ACK_after_write 8 1 T59 4 T60 4


Summary for Variable bus_state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 17 1 16 94.12


User Defined Bins for bus_state_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
read_addr_nack 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
idle 183183 1 T22 1 T23 6 T24 3
stop 32400 1 T2 3 T3 13 T7 18
write_data_nack 6767 1 T140 486 T156 6277 T59 2
write_data_ack 1614035 1 T1 424 T2 990 T3 695
read_data_nack 194452 1 T2 77 T3 84 T16 234
read_data_ack 1763421 1 T2 758 T3 573 T16 1155
write_data 10778958 1 T1 3108 T2 7047 T3 5071
read_data 14735120 1 T2 5874 T3 4510 T16 11155
write_addr_nack 4 1 T59 2 T60 2 - -
write_addr_ack 124819 1 T1 69 T2 101 T3 110
read_addr_ack 158774 1 T2 85 T3 95 T16 253
write 145114 1 T1 80 T2 120 T3 128
read 136571 1 T2 75 T3 78 T16 213
addr 1675113 1 T104 3 T1 460 T2 1220
rstart 124500 1 T1 57 T2 135 T3 108
start 85065 1 T25 1 T104 2 T1 3


Summary for Variable ip_mode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for ip_mode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device 16438595 1 T22 1 T23 6 T29 4
host 15319701 1 T24 3 T25 2 T29 2


Summary for Variable num_rd_bytes_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for num_rd_bytes_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sixtyfour 46475 1 T9 50 T17 48 T11 226
high 1667243 1 T9 1708 T17 984 T32 753
mid 2937945 1 T2 717 T3 292 T16 292
low 8765508 1 T2 4937 T3 3813 T16 9237
one 1009726 1 T2 531 T3 512 T16 1508


Summary for Variable num_wr_bytes_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for num_wr_bytes_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sixtyfour 36104 1 T8 48 T32 28 T11 324
high 1276435 1 T8 976 T32 833 T11 14220
mid 1919308 1 T1 220 T2 594 T3 32
low 6798414 1 T1 2379 T2 5934 T3 4199
one 882086 1 T1 450 T2 774 T3 763


Summary for Cross bus_state_x_ip_mode_cp

Samples crossed: bus_state_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 34 3 31 91.18 3


Automatically Generated Cross Bins for bus_state_x_ip_mode_cp

Element holes
bus_state_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
[read_addr_nack] * -- -- 2


Uncovered bins
bus_state_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
[write_addr_nack] [host] 0 1 1


Covered bins
bus_state_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
idle device 180976 1 T22 1 T23 6 T29 4
idle host 2207 1 T24 3 T25 1 T29 2
stop device 16037 1 T2 3 T3 13 T16 25
stop host 16363 1 T7 18 T12 2 T8 1
write_data_nack device 4 1 T59 2 T60 2 - -
write_data_nack host 6763 1 T140 486 T156 6277 - -
write_data_ack device 856470 1 T1 424 T2 990 T3 695
write_data_ack host 757565 1 T7 604 T8 1782 T10 311
read_data_nack device 107628 1 T2 77 T3 84 T16 234
read_data_nack host 86824 1 T8 4 T9 160 T10 52
read_data_ack device 817301 1 T2 758 T3 573 T16 1155
read_data_ack host 946120 1 T8 79 T9 1895 T10 284
write_data device 6236933 1 T1 3108 T2 7047 T3 5071
write_data host 4542025 1 T7 3622 T8 10776 T10 1860
read_data device 6266177 1 T2 5874 T3 4510 T16 11155
read_data host 8468943 1 T8 572 T9 18712 T10 2731
write_addr_nack device 4 1 T59 2 T60 2 - -
write_addr_ack device 100405 1 T1 69 T2 101 T3 110
write_addr_ack host 24414 1 T7 63 T8 7 T10 44
read_addr_ack device 120092 1 T2 85 T3 95 T16 253
read_addr_ack host 38682 1 T8 4 T9 141 T10 46
write device 116569 1 T1 80 T2 120 T3 128
write host 28545 1 T7 76 T8 8 T42 4
read device 103098 1 T2 75 T3 78 T16 213
read host 33473 1 T12 4 T8 3 T42 3
addr device 1353970 1 T104 3 T1 460 T2 1220
addr host 321143 1 T7 334 T12 41 T8 54
rstart device 120854 1 T1 57 T2 135 T3 108
rstart host 3646 1 T12 2 T8 3 T11 12
start device 42077 1 T104 2 T1 3 T2 10
start host 42988 1 T25 1 T7 44 T12 10


Summary for Cross num_rd_bytes_x_ip_mode_cp

Samples crossed: ip_mode_cp num_rd_bytes_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 0 10 100.00


Automatically Generated Cross Bins for num_rd_bytes_x_ip_mode_cp

Bins
ip_mode_cpnum_rd_bytes_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device sixtyfour 2493 1 T17 48 T157 166 T158 260
device high 84026 1 T17 984 T32 753 T67 168
device mid 452865 1 T2 717 T3 292 T16 292
device low 5001588 1 T2 4937 T3 3813 T16 9237
device one 735301 1 T2 531 T3 512 T16 1508
host sixtyfour 43982 1 T9 50 T11 226 T41 30
host high 1583217 1 T9 1708 T11 16298 T41 569
host mid 2485080 1 T8 33 T9 4712 T10 303
host low 3763920 1 T8 572 T9 11454 T10 2255
host one 274425 1 T8 28 T9 925 T10 200


Summary for Cross num_wr_bytes_x_ip_mode_cp

Samples crossed: ip_mode_cp num_wr_bytes_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 0 10 100.00


Automatically Generated Cross Bins for num_wr_bytes_x_ip_mode_cp

Bins
ip_mode_cpnum_wr_bytes_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device sixtyfour 2380 1 T32 28 T34 24 T157 116
device high 87499 1 T32 833 T61 242 T159 82
device mid 446568 1 T1 220 T2 594 T3 32
device low 4936840 1 T1 2379 T2 5934 T3 4199
device one 727578 1 T1 450 T2 774 T3 763
host sixtyfour 33724 1 T8 48 T11 324 T13 240
host high 1188936 1 T8 976 T11 14220 T13 4870
host mid 1472740 1 T7 689 T8 1080 T10 251
host low 1861574 1 T7 2773 T8 974 T10 1408
host one 154508 1 T7 365 T8 48 T10 236


Summary for Cross Stop_after_write_data_ack_x_ip_mode_cp

Samples crossed: Stop_after_write_data_ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Stop_after_write_data_ack_x_ip_mode_cp

Bins
Stop_after_write_data_ack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_ack device 7180 1 T2 2 T3 8 T16 5
Stop_after_write_data_ack host 5487 1 T7 18 T10 13 T11 35


Summary for Cross Stop_after_read_data_ack_x_ip_mode_cp

Samples crossed: Stop_after_read_data_ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Stop_after_read_data_ack_x_ip_mode_cp

Element holes
Stop_after_read_data_ack_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [host] 0 1 1


Covered bins
Stop_after_read_data_ack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_ack device 386 1 T32 11 T46 4 T47 5


Summary for Cross Stop_after_write_data_Nack_x_ip_mode_cp

Samples crossed: Stop_after_write_data_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Stop_after_write_data_Nack_x_ip_mode_cp

Element holes
Stop_after_write_data_Nack_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [device] 0 1 1


Covered bins
Stop_after_write_data_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNT
Stop_after_write_data_Nack host 1 1 T140 1


Summary for Cross Stop_after_read_data_Nack_x_ip_mode_cp

Samples crossed: Stop_after_read_data_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Stop_after_read_data_Nack_x_ip_mode_cp

Bins
Stop_after_read_data_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_Nack device 8149 1 T2 1 T3 5 T16 20
Stop_after_read_data_Nack host 10676 1 T8 1 T9 39 T10 12


Summary for Cross Rstart_after_Address_Ack_x_ip_mode_cp

Samples crossed: Rstart_after_Address_Ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Rstart_after_Address_Ack_x_ip_mode_cp

Bins
Rstart_after_Address_Ack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Ack device 11 1 T59 5 T60 6 - -
Rstart_after_Address_Ack host 3 1 T52 1 T149 1 T160 1


Summary for Cross Rstart_after_Address_Nack_x_ip_mode_cp

Samples crossed: Rstart_after_Address_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Rstart_after_Address_Nack_x_ip_mode_cp

Element holes
Rstart_after_Address_Nack_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [host] 0 1 1


Covered bins
Rstart_after_Address_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Rstart_after_Address_Nack device 4 1 T59 2 T60 2


Summary for Cross Start_followed_by_Rstart_cp_x_ip_mode_cp

Samples crossed: Start_followed_by_Rstart_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Start_followed_by_Rstart_cp_x_ip_mode_cp

Element holes
Start_followed_by_Rstart_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [device] 0 1 1


Excluded/Illegal bins
Start_followed_by_Rstart_cpip_mode_cpCOUNTSTATUS
[auto[0]] [device , host] -- Excluded (2 bins)


Covered bins
Start_followed_by_Rstart_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] host 10 1 T150 4 T151 2 T152 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%