Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45680181	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16233827

1

T22

100

T23

318

T24

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54404016	1			T22	53		T23	135		T24	40
values[0x0]	3754632	1			T22	39		T23	84		T24	10
values[0x1]	3755360	1			T22	53		T23	99		T24	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33579340	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

28334668

1

T22

117

T23

318

T24

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	184397	1			T22	1		T27	1		T28	1
valid_sources[0x01]	226370	1			T22	1		T23	10		T27	1
valid_sources[0x02]	197580	1			T22	2		T25	2		T30	1
valid_sources[0x03]	226052	1			T22	2		T31	11		T117	7
valid_sources[0x04]	193234	1			T22	1		T27	2		T31	2
valid_sources[0x05]	207581	1			T22	1		T27	1		T31	14
valid_sources[0x06]	205473	1			T22	1		T104	6		T117	24
valid_sources[0x07]	189948	1			T25	4		T26	1		T27	1
valid_sources[0x08]	251504	1			T29	29		T31	2		T117	21
valid_sources[0x09]	201916	1			T24	3		T27	2		T28	2
valid_sources[0x0a]	218018	1			T23	1		T26	1		T27	1
valid_sources[0x0b]	205565	1			T27	1		T117	9		T76	3
valid_sources[0x0c]	205471	1			T23	2		T25	1		T27	3
valid_sources[0x0d]	828340	1			T27	3		T104	6		T117	5
valid_sources[0x0e]	199922	1			T22	1		T23	4		T26	1
valid_sources[0x0f]	238966	1			T26	1		T27	1		T28	1
valid_sources[0x10]	231650	1			T24	7		T26	1		T27	1
valid_sources[0x11]	208292	1			T27	1		T117	4		T2	1
valid_sources[0x12]	360162	1			T23	1		T27	2		T31	15
valid_sources[0x13]	208602	1			T22	3		T25	4		T27	2
valid_sources[0x14]	207316	1			T23	2		T24	1		T27	2
valid_sources[0x15]	542712	1			T23	3		T24	6		T27	1
valid_sources[0x16]	187380	1			T22	1		T26	1		T30	1
valid_sources[0x17]	212491	1			T23	1		T26	2		T31	15
valid_sources[0x18]	226314	1			T69	1		T104	1		T117	16
valid_sources[0x19]	212106	1			T25	7		T104	1		T117	5
valid_sources[0x1a]	228498	1			T23	2		T27	1		T117	4
valid_sources[0x1b]	187100	1			T25	3		T31	3		T117	8
valid_sources[0x1c]	192660	1			T22	2		T104	1		T76	5
valid_sources[0x1d]	209138	1			T22	1		T25	4		T26	1
valid_sources[0x1e]	236995	1			T22	1		T24	3		T25	4
valid_sources[0x1f]	207455	1			T22	1		T23	3		T27	2
valid_sources[0x20]	198722	1			T25	2		T28	8		T117	3
valid_sources[0x21]	197530	1			T22	1		T30	1		T104	1
valid_sources[0x22]	187515	1			T22	2		T27	2		T28	2
valid_sources[0x23]	185883	1			T22	1		T27	3		T117	3
valid_sources[0x24]	208128	1			T22	1		T23	3		T24	5
valid_sources[0x25]	212240	1			T25	8		T26	1		T27	2
valid_sources[0x26]	216694	1			T28	1		T30	1		T31	4
valid_sources[0x27]	197911	1			T23	5		T30	1		T104	2
valid_sources[0x28]	197254	1			T27	4		T31	3		T70	1
valid_sources[0x29]	209408	1			T22	1		T23	10		T26	3
valid_sources[0x2a]	197509	1			T23	2		T26	2		T27	5
valid_sources[0x2b]	446534	1			T22	1		T26	2		T27	5
valid_sources[0x2c]	210789	1			T23	1		T27	1		T117	1
valid_sources[0x2d]	210606	1			T22	1		T23	2		T26	1
valid_sources[0x2e]	219317	1			T23	2		T26	1		T27	1
valid_sources[0x2f]	189744	1			T22	1		T23	4		T24	2
valid_sources[0x30]	233440	1			T27	1		T28	2		T31	23
valid_sources[0x31]	206458	1			T27	4		T28	3		T69	1
valid_sources[0x32]	283353	1			T22	1		T23	2		T26	1
valid_sources[0x33]	226327	1			T22	1		T117	2		T1	2
valid_sources[0x34]	226073	1			T22	3		T23	4		T24	1
valid_sources[0x35]	320679	1			T23	1		T27	1		T117	1
valid_sources[0x36]	192945	1			T23	1		T24	1		T25	3
valid_sources[0x37]	197943	1			T22	1		T23	1		T27	1
valid_sources[0x38]	210076	1			T22	2		T24	3		T31	14
valid_sources[0x39]	217769	1			T22	1		T27	2		T30	1
valid_sources[0x3a]	207129	1			T23	1		T27	2		T117	6
valid_sources[0x3b]	291134	1			T22	1		T104	5		T117	1
valid_sources[0x3c]	199427	1			T26	1		T30	1		T104	1
valid_sources[0x3d]	190801	1			T22	1		T23	4		T25	6
valid_sources[0x3e]	201967	1			T23	4		T27	2		T31	10
valid_sources[0x3f]	219868	1			T26	1		T27	1		T30	1
valid_sources[0x40]	232365	1			T22	2		T23	1		T24	1
valid_sources[0x41]	211736	1			T23	5		T27	2		T104	2
valid_sources[0x42]	243081	1			T23	1		T27	2		T117	2
valid_sources[0x43]	211324	1			T22	1		T23	2		T26	2
valid_sources[0x44]	339363	1			T22	1		T26	1		T27	2
valid_sources[0x45]	202766	1			T23	3		T31	8		T117	4
valid_sources[0x46]	193432	1			T23	1		T26	1		T104	4
valid_sources[0x47]	727762	1			T27	1		T28	1		T29	31
valid_sources[0x48]	243078	1			T70	1		T117	5		T76	5
valid_sources[0x49]	218308	1			T22	2		T23	6		T25	1
valid_sources[0x4a]	212793	1			T23	1		T27	2		T117	5
valid_sources[0x4b]	217463	1			T22	2		T23	1		T27	3
valid_sources[0x4c]	207196	1			T22	1		T23	2		T25	5
valid_sources[0x4d]	210175	1			T26	1		T27	2		T28	1
valid_sources[0x4e]	211143	1			T22	1		T27	1		T28	2
valid_sources[0x4f]	254533	1			T23	4		T27	1		T31	1
valid_sources[0x50]	206855	1			T22	1		T27	2		T104	4
valid_sources[0x51]	208560	1			T22	1		T23	1		T26	2
valid_sources[0x52]	232816	1			T22	1		T26	2		T27	2
valid_sources[0x53]	205534	1			T22	1		T24	2		T25	4
valid_sources[0x54]	201072	1			T23	1		T27	1		T31	8
valid_sources[0x55]	210419	1			T23	4		T26	2		T31	12
valid_sources[0x56]	208434	1			T22	1		T27	1		T28	5
valid_sources[0x57]	336057	1			T22	2		T23	6		T117	2
valid_sources[0x58]	318285	1			T22	1		T23	4		T26	4
valid_sources[0x59]	250226	1			T22	1		T26	1		T27	3
valid_sources[0x5a]	201925	1			T23	6		T27	6		T30	1
valid_sources[0x5b]	219164	1			T23	8		T28	2		T117	5
valid_sources[0x5c]	227429	1			T22	2		T23	2		T30	1
valid_sources[0x5d]	226472	1			T22	1		T104	2		T117	1
valid_sources[0x5e]	199585	1			T27	3		T31	5		T70	1
valid_sources[0x5f]	214569	1			T31	4		T70	2		T117	14
valid_sources[0x60]	224851	1			T22	2		T27	3		T28	1
valid_sources[0x61]	199566	1			T23	3		T104	5		T117	2
valid_sources[0x62]	201788	1			T27	3		T31	16		T117	17
valid_sources[0x63]	198016	1			T22	1		T23	2		T26	2
valid_sources[0x64]	235574	1			T24	1		T27	2		T28	1
valid_sources[0x65]	206878	1			T27	5		T31	11		T104	6
valid_sources[0x66]	200413	1			T22	2		T23	1		T26	1
valid_sources[0x67]	235335	1			T22	1		T23	1		T24	1
valid_sources[0x68]	219061	1			T22	2		T23	3		T29	42
valid_sources[0x69]	225687	1			T26	1		T27	1		T117	5
valid_sources[0x6a]	196399	1			T23	2		T26	1		T31	14
valid_sources[0x6b]	205855	1			T23	1		T27	1		T28	2
valid_sources[0x6c]	328282	1			T23	2		T27	3		T117	17
valid_sources[0x6d]	198004	1			T27	2		T28	4		T70	1
valid_sources[0x6e]	194884	1			T23	4		T27	1		T28	1
valid_sources[0x6f]	211792	1			T26	1		T28	2		T117	15
valid_sources[0x70]	264559	1			T22	1		T26	1		T117	3
valid_sources[0x71]	290021	1			T22	1		T23	2		T28	1
valid_sources[0x72]	239918	1			T70	2		T117	8		T2	2
valid_sources[0x73]	223120	1			T22	3		T27	1		T117	12
valid_sources[0x74]	196275	1			T22	2		T23	1		T27	1
valid_sources[0x75]	210722	1			T22	2		T28	1		T70	1
valid_sources[0x76]	312360	1			T22	1		T24	2		T26	1
valid_sources[0x77]	438257	1			T22	1		T27	1		T117	2
valid_sources[0x78]	204403	1			T26	2		T28	2		T31	1
valid_sources[0x79]	858123	1			T22	1		T23	1		T26	1
valid_sources[0x7a]	286730	1			T23	1		T27	1		T117	1
valid_sources[0x7b]	221194	1			T27	1		T28	2		T31	3
valid_sources[0x7c]	270910	1			T22	1		T23	3		T25	1
valid_sources[0x7d]	192904	1			T22	1		T23	2		T26	1
valid_sources[0x7e]	196035	1			T23	6		T26	4		T27	2
valid_sources[0x7f]	263352	1			T27	2		T30	1		T117	2
valid_sources[0x80]	227244	1			T23	4		T24	2		T26	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

13370038

1

T22

33

T23

135

T24

5

values[0x0]

all_enables

biggest_size

1845387

1

T22

36

T23

84

T24

7

values[0x1]

all_enables

biggest_size

1018402

1

T22

31

T23

99

T24

4