Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	527231139	66020	0	0
ctrl_rd_A	527231139	1697	0	0
fifo_ctrl_rd_A	527231139	4678	0	0
host_timeout_ctrl_rd_A	527231139	1524	0	0
intr_enable_rd_A	527231139	3471	0	0
ovrd_rd_A	527231139	2568	0	0
target_id_rd_A	527231139	1988	0	0
timeout_ctrl_rd_A	527231139	1562	0	0
timing0_rd_A	527231139	1630	0	0
timing1_rd_A	527231139	1470	0	0
timing2_rd_A	527231139	1773	0	0
timing3_rd_A	527231139	1625	0	0
timing4_rd_A	527231139	1647	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527231139	66020	0	0
T22	1622	100	0	0
T23	1397	0	0	0
T24	1467	0	0	0
T25	2603	0	0	0
T26	1148	0	0	0
T27	4063	0	0	0
T28	3373	136	0	0
T29	5514	3	0	0
T30	978	0	0	0
T31	5557	1	0	0
T35	0	2584	0	0
T48	0	14643	0	0
T76	0	3	0	0
T80	0	22414	0	0
T86	0	7	0	0
T101	0	17738	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527231139	1697	0	0
T25	2603	20	0	0
T26	1148	0	0	0
T27	4063	98	0	0
T28	3373	0	0	0
T29	5514	0	0	0
T30	978	0	0	0
T31	5557	0	0	0
T35	0	66	0	0
T48	0	577	0	0
T69	2026	0	0	0
T70	1513	0	0	0
T83	0	51	0	0
T86	0	126	0	0
T104	1729	0	0	0
T107	0	59	0	0
T115	0	41	0	0
T120	0	9	0	0
T121	0	10	0	0

fifo_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527231139	4678	0	0
T11	0	70	0	0
T25	2603	18	0	0
T26	1148	0	0	0
T27	4063	95	0	0
T28	3373	0	0	0
T29	5514	0	0	0
T30	978	0	0	0
T31	5557	0	0	0
T35	0	109	0	0
T49	0	118	0	0
T52	0	206	0	0
T69	2026	0	0	0
T70	1513	0	0	0
T104	1729	0	0	0
T122	0	132	0	0
T123	0	151	0	0
T124	0	125	0	0
T125	0	97	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527231139	1524	0	0
T25	2603	5	0	0
T26	1148	0	0	0
T27	4063	94	0	0
T28	3373	0	0	0
T29	5514	0	0	0
T30	978	0	0	0
T31	5557	0	0	0
T35	0	93	0	0
T48	0	548	0	0
T69	2026	0	0	0
T70	1513	0	0	0
T83	0	39	0	0
T86	0	86	0	0
T104	1729	0	0	0
T107	0	73	0	0
T115	0	69	0	0
T120	0	4	0	0
T121	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527231139	3471	0	0
T11	0	10	0	0
T25	2603	117	0	0
T26	1148	0	0	0
T27	4063	86	0	0
T28	3373	0	0	0
T29	5514	0	0	0
T30	978	0	0	0
T31	5557	0	0	0
T35	0	87	0	0
T48	0	570	0	0
T49	0	27	0	0
T69	2026	11	0	0
T70	1513	0	0	0
T104	1729	0	0	0
T118	0	43	0	0
T119	0	3	0	0
T126	0	6	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527231139	2568	0	0
T4	0	22	0	0
T5	0	31	0	0
T25	2603	1	0	0
T26	1148	0	0	0
T27	4063	81	0	0
T28	3373	0	0	0
T29	5514	0	0	0
T30	978	0	0	0
T31	5557	0	0	0
T35	0	123	0	0
T69	2026	0	0	0
T70	1513	0	0	0
T104	1729	0	0	0
T127	0	67	0	0
T128	0	34	0	0
T129	0	98	0	0
T130	0	87	0	0
T131	0	38	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527231139	1988	0	0
T25	2603	7	0	0
T26	1148	0	0	0
T27	4063	87	0	0
T28	3373	0	0	0
T29	5514	0	0	0
T30	978	0	0	0
T31	5557	0	0	0
T35	0	116	0	0
T48	0	662	0	0
T69	2026	0	0	0
T70	1513	0	0	0
T83	0	112	0	0
T86	0	158	0	0
T104	1729	0	0	0
T107	0	53	0	0
T115	0	22	0	0
T120	0	23	0	0
T132	0	14	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527231139	1562	0	0
T25	2603	13	0	0
T26	1148	0	0	0
T27	4063	85	0	0
T28	3373	0	0	0
T29	5514	0	0	0
T30	978	0	0	0
T31	5557	0	0	0
T35	0	140	0	0
T48	0	505	0	0
T69	2026	0	0	0
T70	1513	0	0	0
T83	0	43	0	0
T86	0	122	0	0
T104	1729	0	0	0
T107	0	36	0	0
T115	0	52	0	0
T120	0	21	0	0
T121	0	7	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527231139	1630	0	0
T25	2603	6	0	0
T26	1148	0	0	0
T27	4063	66	0	0
T28	3373	0	0	0
T29	5514	0	0	0
T30	978	0	0	0
T31	5557	0	0	0
T35	0	140	0	0
T48	0	584	0	0
T69	2026	0	0	0
T70	1513	0	0	0
T83	0	35	0	0
T86	0	130	0	0
T104	1729	0	0	0
T107	0	52	0	0
T115	0	24	0	0
T120	0	11	0	0
T121	0	16	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527231139	1470	0	0
T25	2603	22	0	0
T26	1148	0	0	0
T27	4063	67	0	0
T28	3373	0	0	0
T29	5514	0	0	0
T30	978	0	0	0
T31	5557	0	0	0
T35	0	60	0	0
T48	0	455	0	0
T69	2026	0	0	0
T70	1513	0	0	0
T83	0	43	0	0
T86	0	102	0	0
T104	1729	0	0	0
T107	0	69	0	0
T115	0	30	0	0
T120	0	4	0	0
T121	0	10	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527231139	1773	0	0
T25	2603	13	0	0
T26	1148	0	0	0
T27	4063	92	0	0
T28	3373	0	0	0
T29	5514	0	0	0
T30	978	0	0	0
T31	5557	0	0	0
T35	0	104	0	0
T48	0	643	0	0
T69	2026	0	0	0
T70	1513	0	0	0
T83	0	66	0	0
T86	0	80	0	0
T104	1729	0	0	0
T107	0	53	0	0
T115	0	53	0	0
T120	0	16	0	0
T121	0	29	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527231139	1625	0	0
T25	2603	16	0	0
T26	1148	0	0	0
T27	4063	88	0	0
T28	3373	0	0	0
T29	5514	0	0	0
T30	978	0	0	0
T31	5557	0	0	0
T35	0	130	0	0
T48	0	505	0	0
T69	2026	0	0	0
T70	1513	0	0	0
T83	0	70	0	0
T86	0	116	0	0
T104	1729	0	0	0
T107	0	63	0	0
T115	0	35	0	0
T120	0	7	0	0
T121	0	18	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527231139	1647	0	0
T25	2603	9	0	0
T26	1148	0	0	0
T27	4063	86	0	0
T28	3373	0	0	0
T29	5514	0	0	0
T30	978	0	0	0
T31	5557	0	0	0
T35	0	114	0	0
T48	0	600	0	0
T69	2026	0	0	0
T70	1513	0	0	0
T83	0	52	0	0
T86	0	85	0	0
T104	1729	0	0	0
T107	0	67	0	0
T115	0	19	0	0
T120	0	34	0	0
T121	0	11	0	0