Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.01	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	15	45	75.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	15	45	75.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	316	1			T1	5		T3	5		T11	8
all_values[1]	316	1			T1	5		T3	5		T11	8
all_values[2]	316	1			T1	5		T3	5		T11	8
all_values[3]	316	1			T1	5		T3	5		T11	8
all_values[4]	316	1			T1	5		T3	5		T11	8
all_values[5]	316	1			T1	5		T3	5		T11	8
all_values[6]	316	1			T1	5		T3	5		T11	8
all_values[7]	316	1			T1	5		T3	5		T11	8
all_values[8]	316	1			T1	5		T3	5		T11	8
all_values[9]	316	1			T1	5		T3	5		T11	8
all_values[10]	316	1			T1	5		T3	5		T11	8
all_values[11]	316	1			T1	5		T3	5		T11	8
all_values[12]	316	1			T1	5		T3	5		T11	8
all_values[13]	316	1			T1	5		T3	5		T11	8
all_values[14]	316	1			T1	5		T3	5		T11	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2989

1

T1

38

T3

40

T11

69

auto[1]

1751

1

T1

37

T3

35

T11

51

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

969

1

T1

13

T3

9

T11

17

auto[1]

3771

1

T1

62

T3

66

T11

103

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	15	45	75.00	15

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	[auto[0]]	--	--	15

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	81	1			T1	1		T3	5		T11	8
all_values[0]	auto[0]	auto[1]	119	1			T1	2		T10	4		T12	4
all_values[0]	auto[1]	auto[1]	116	1			T1	2		T10	4		T64	1
all_values[1]	auto[0]	auto[0]	75	1			T3	1		T11	1		T8	1
all_values[1]	auto[0]	auto[1]	121	1			T1	2		T3	1		T11	3
all_values[1]	auto[1]	auto[1]	120	1			T1	3		T3	3		T11	4
all_values[2]	auto[0]	auto[0]	70	1			T1	2		T11	1		T8	1
all_values[2]	auto[0]	auto[1]	131	1			T1	1		T3	3		T11	3
all_values[2]	auto[1]	auto[1]	115	1			T1	2		T3	2		T11	4
all_values[3]	auto[0]	auto[0]	66	1			T1	1		T11	1		T8	1
all_values[3]	auto[0]	auto[1]	135	1			T1	4		T3	2		T11	4
all_values[3]	auto[1]	auto[1]	115	1			T3	3		T11	3		T10	2
all_values[4]	auto[0]	auto[0]	69	1			T11	1		T8	1		T12	2
all_values[4]	auto[0]	auto[1]	136	1			T1	1		T3	1		T11	2
all_values[4]	auto[1]	auto[1]	111	1			T1	4		T3	4		T11	5
all_values[5]	auto[0]	auto[0]	61	1			T8	1		T13	1		T14	1
all_values[5]	auto[0]	auto[1]	141	1			T1	3		T3	2		T11	2
all_values[5]	auto[1]	auto[1]	114	1			T1	2		T3	3		T11	6
all_values[6]	auto[0]	auto[0]	51	1			T11	1		T8	1		T13	1
all_values[6]	auto[0]	auto[1]	138	1			T1	4		T3	4		T11	3
all_values[6]	auto[1]	auto[1]	127	1			T1	1		T3	1		T11	4
all_values[7]	auto[0]	auto[0]	64	1			T1	2		T3	1		T8	1
all_values[7]	auto[0]	auto[1]	138	1			T1	1		T3	1		T11	5
all_values[7]	auto[1]	auto[1]	114	1			T1	2		T3	3		T11	3
all_values[8]	auto[0]	auto[0]	65	1			T3	2		T11	2		T8	1
all_values[8]	auto[0]	auto[1]	123	1			T1	1		T3	1		T11	4
all_values[8]	auto[1]	auto[1]	128	1			T1	4		T3	2		T11	2
all_values[9]	auto[0]	auto[0]	51	1			T1	1		T8	1		T10	1
all_values[9]	auto[0]	auto[1]	136	1			T1	1		T3	2		T11	5
all_values[9]	auto[1]	auto[1]	129	1			T1	3		T3	3		T11	3
all_values[10]	auto[0]	auto[0]	60	1			T1	5		T11	1		T8	1
all_values[10]	auto[0]	auto[1]	143	1			T3	3		T11	3		T10	3
all_values[10]	auto[1]	auto[1]	113	1			T3	2		T11	4		T10	5
all_values[11]	auto[0]	auto[0]	56	1			T8	1		T10	1		T13	1
all_values[11]	auto[0]	auto[1]	141	1			T1	1		T3	5		T11	5
all_values[11]	auto[1]	auto[1]	119	1			T1	4		T11	3		T10	2
all_values[12]	auto[0]	auto[0]	59	1			T8	1		T12	1		T13	1
all_values[12]	auto[0]	auto[1]	147	1			T1	2		T3	3		T11	7
all_values[12]	auto[1]	auto[1]	110	1			T1	3		T3	2		T11	1
all_values[13]	auto[0]	auto[0]	71	1			T1	1		T8	1		T13	1
all_values[13]	auto[0]	auto[1]	135	1			T1	1		T3	1		T11	5
all_values[13]	auto[1]	auto[1]	110	1			T1	3		T3	4		T11	3
all_values[14]	auto[0]	auto[0]	70	1			T11	1		T8	1		T12	1
all_values[14]	auto[0]	auto[1]	136	1			T1	1		T3	2		T11	1
all_values[14]	auto[1]	auto[1]	110	1			T1	4		T3	3		T11	6