Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
59.10	52.44	59.16	94.90	0.00	53.13	100.00	54.10

Total tests in report: 154

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
50.14	50.14	49.51	49.51	49.80	49.80	94.12	94.12	0.00	0.00	50.05	50.05	91.96	91.96	15.55	15.55	/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.122511437
55.98	5.84	51.66	2.15	55.75	5.95	97.44	3.32	0.00	0.00	52.91	2.85	92.28	0.32	41.81	26.26	/workspace/coverage/cover_reg_top/16.i2c_intr_test.622502734
57.74	1.77	51.71	0.05	57.69	1.94	98.47	1.02	0.00	0.00	53.02	0.11	97.43	5.14	45.90	4.10	/workspace/coverage/cover_reg_top/7.i2c_tl_errors.438306397
58.32	0.58	51.71	0.00	57.95	0.27	98.98	0.51	0.00	0.00	53.02	0.00	97.43	0.00	49.16	3.26	/workspace/coverage/cover_reg_top/28.i2c_intr_test.3232296139
58.79	0.47	51.76	0.05	58.29	0.33	100.00	1.02	0.00	0.00	53.13	0.11	97.43	0.00	50.95	1.79	/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2639393645
59.17	0.38	52.44	0.68	58.42	0.13	100.00	0.00	0.00	0.00	53.13	0.00	99.04	1.61	51.16	0.21	/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1068010005
59.35	0.18	52.44	0.00	58.42	0.00	100.00	0.00	0.00	0.00	53.13	0.00	99.04	0.00	52.42	1.26	/workspace/coverage/cover_reg_top/6.i2c_intr_test.1193664342
59.47	0.12	52.44	0.00	58.42	0.00	100.00	0.00	0.00	0.00	53.13	0.00	99.68	0.64	52.63	0.21	/workspace/coverage/cover_reg_top/13.i2c_csr_rw.2249970592
59.53	0.06	52.44	0.00	58.62	0.20	100.00	0.00	0.00	0.00	53.13	0.00	99.68	0.00	52.84	0.21	/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.764150291
59.58	0.05	52.44	0.00	58.62	0.00	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.32	52.84	0.00	/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.4032843158
59.62	0.05	52.44	0.00	58.62	0.00	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	53.15	0.32	/workspace/coverage/cover_reg_top/29.i2c_intr_test.637781438
59.67	0.05	52.44	0.00	58.62	0.00	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	53.47	0.32	/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.150339636
59.70	0.04	52.44	0.00	58.89	0.27	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	53.47	0.00	/workspace/coverage/cover_reg_top/19.i2c_tl_errors.2760183777
59.73	0.03	52.44	0.00	58.89	0.00	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	53.68	0.21	/workspace/coverage/cover_reg_top/40.i2c_intr_test.3156389204
59.76	0.03	52.44	0.00	58.89	0.00	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	53.89	0.21	/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4211399645
59.78	0.02	52.44	0.00	59.02	0.13	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	53.89	0.00	/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1614513158
59.80	0.02	52.44	0.00	59.02	0.00	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	53.99	0.11	/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1270443412
59.81	0.02	52.44	0.00	59.02	0.00	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	54.10	0.11	/workspace/coverage/cover_reg_top/15.i2c_csr_rw.1624284691
59.82	0.01	52.44	0.00	59.09	0.07	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	54.10	0.00	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1607176453
59.83	0.01	52.44	0.00	59.16	0.07	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	54.10	0.00	/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.60603371

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1853535976
/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3422260227
/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.670816271
/workspace/coverage/cover_reg_top/0.i2c_csr_rw.2076722927
/workspace/coverage/cover_reg_top/0.i2c_intr_test.1765640819
/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1772543272
/workspace/coverage/cover_reg_top/0.i2c_tl_errors.1063581500
/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1629369861
/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1003542304
/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3268405985
/workspace/coverage/cover_reg_top/1.i2c_csr_rw.3961134650
/workspace/coverage/cover_reg_top/1.i2c_intr_test.3032721707
/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2937360051
/workspace/coverage/cover_reg_top/1.i2c_tl_errors.3373835331
/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3133020035
/workspace/coverage/cover_reg_top/10.i2c_csr_rw.3020121194
/workspace/coverage/cover_reg_top/10.i2c_intr_test.3081980498
/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3987899984
/workspace/coverage/cover_reg_top/10.i2c_tl_errors.1689177897
/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.4107159449
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.432833177
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.3313603581
/workspace/coverage/cover_reg_top/11.i2c_intr_test.1844947542
/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2057138663
/workspace/coverage/cover_reg_top/11.i2c_tl_errors.1213061113
/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3338008867
/workspace/coverage/cover_reg_top/12.i2c_csr_rw.686581418
/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.148860328
/workspace/coverage/cover_reg_top/12.i2c_tl_errors.2787584313
/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3566347974
/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.726104731
/workspace/coverage/cover_reg_top/13.i2c_intr_test.1733285875
/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1922620013
/workspace/coverage/cover_reg_top/13.i2c_tl_errors.2106547277
/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.934608743
/workspace/coverage/cover_reg_top/14.i2c_csr_rw.1441778657
/workspace/coverage/cover_reg_top/14.i2c_intr_test.4196969138
/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.601937869
/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2343155468
/workspace/coverage/cover_reg_top/15.i2c_intr_test.1894183747
/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1440916738
/workspace/coverage/cover_reg_top/15.i2c_tl_errors.1539316643
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1297953885
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.1946692922
/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3309061591
/workspace/coverage/cover_reg_top/16.i2c_tl_errors.2344394370
/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1299435116
/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2253780975
/workspace/coverage/cover_reg_top/17.i2c_csr_rw.2398933873
/workspace/coverage/cover_reg_top/17.i2c_intr_test.3747715890
/workspace/coverage/cover_reg_top/17.i2c_tl_errors.761082543
/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.84855885
/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3720053275
/workspace/coverage/cover_reg_top/18.i2c_csr_rw.4273564921
/workspace/coverage/cover_reg_top/18.i2c_intr_test.2229821921
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1646045822
/workspace/coverage/cover_reg_top/18.i2c_tl_errors.3435992602
/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2856096129
/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2399268976
/workspace/coverage/cover_reg_top/19.i2c_intr_test.188043665
/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1078179432
/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.31022944
/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1011426715
/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2096857777
/workspace/coverage/cover_reg_top/2.i2c_csr_rw.2409803441
/workspace/coverage/cover_reg_top/2.i2c_intr_test.2106868729
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1392596218
/workspace/coverage/cover_reg_top/2.i2c_tl_errors.777106164
/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1680229532
/workspace/coverage/cover_reg_top/20.i2c_intr_test.1974591574
/workspace/coverage/cover_reg_top/21.i2c_intr_test.4135167824
/workspace/coverage/cover_reg_top/22.i2c_intr_test.2227444533
/workspace/coverage/cover_reg_top/23.i2c_intr_test.3996947839
/workspace/coverage/cover_reg_top/24.i2c_intr_test.1795740625
/workspace/coverage/cover_reg_top/25.i2c_intr_test.1854635195
/workspace/coverage/cover_reg_top/26.i2c_intr_test.3547173214
/workspace/coverage/cover_reg_top/27.i2c_intr_test.55795579
/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.799127472
/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1276597881
/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.897506760
/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3405056694
/workspace/coverage/cover_reg_top/3.i2c_csr_rw.3061946568
/workspace/coverage/cover_reg_top/3.i2c_tl_errors.690569662
/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2076331538
/workspace/coverage/cover_reg_top/31.i2c_intr_test.1622269884
/workspace/coverage/cover_reg_top/32.i2c_intr_test.3262611029
/workspace/coverage/cover_reg_top/33.i2c_intr_test.1548382437
/workspace/coverage/cover_reg_top/34.i2c_intr_test.799843787
/workspace/coverage/cover_reg_top/35.i2c_intr_test.2748633037
/workspace/coverage/cover_reg_top/36.i2c_intr_test.2273707582
/workspace/coverage/cover_reg_top/37.i2c_intr_test.1131980662
/workspace/coverage/cover_reg_top/39.i2c_intr_test.1520822509
/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1952791327
/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.458238463
/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.692857366
/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3395951503
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.2698585885
/workspace/coverage/cover_reg_top/4.i2c_intr_test.1731534620
/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1907470266
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.487661664
/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.133215622
/workspace/coverage/cover_reg_top/41.i2c_intr_test.26738183
/workspace/coverage/cover_reg_top/42.i2c_intr_test.238748915
/workspace/coverage/cover_reg_top/43.i2c_intr_test.560740758
/workspace/coverage/cover_reg_top/44.i2c_intr_test.1422052861
/workspace/coverage/cover_reg_top/45.i2c_intr_test.3891589554
/workspace/coverage/cover_reg_top/46.i2c_intr_test.11767257
/workspace/coverage/cover_reg_top/47.i2c_intr_test.4242556219
/workspace/coverage/cover_reg_top/48.i2c_intr_test.500173912
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.888796400
/workspace/coverage/cover_reg_top/5.i2c_csr_rw.3970616015
/workspace/coverage/cover_reg_top/5.i2c_intr_test.344516590
/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1954436682
/workspace/coverage/cover_reg_top/5.i2c_tl_errors.1022081610
/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1868714603
/workspace/coverage/cover_reg_top/6.i2c_csr_rw.701836372
/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3092366596
/workspace/coverage/cover_reg_top/6.i2c_tl_errors.1377630135
/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2848808391
/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.460206930
/workspace/coverage/cover_reg_top/7.i2c_csr_rw.2530845651
/workspace/coverage/cover_reg_top/7.i2c_intr_test.3282064260
/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3275006957
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1714271906
/workspace/coverage/cover_reg_top/8.i2c_csr_rw.375075150
/workspace/coverage/cover_reg_top/8.i2c_intr_test.1411576349
/workspace/coverage/cover_reg_top/8.i2c_tl_errors.2558048727
/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2965175712
/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1172094533
/workspace/coverage/cover_reg_top/9.i2c_csr_rw.1940810477
/workspace/coverage/cover_reg_top/9.i2c_intr_test.976282005
/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3064334989
/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3130327592
/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.170924464

Total test records in report: 154

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/46.i2c_intr_test.11767257	Jan 10 01:01:15 PM PST 24	Jan 10 01:02:45 PM PST 24	17981652 ps
T2	/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.122511437	Jan 10 01:00:37 PM PST 24	Jan 10 01:01:53 PM PST 24	2813777472 ps
T3	/workspace/coverage/cover_reg_top/17.i2c_intr_test.3747715890	Jan 10 01:01:05 PM PST 24	Jan 10 01:02:21 PM PST 24	17681304 ps
T7	/workspace/coverage/cover_reg_top/17.i2c_csr_rw.2398933873	Jan 10 01:01:10 PM PST 24	Jan 10 01:02:53 PM PST 24	33488641 ps
T4	/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2965175712	Jan 10 01:01:12 PM PST 24	Jan 10 01:02:43 PM PST 24	176053773 ps
T11	/workspace/coverage/cover_reg_top/16.i2c_intr_test.622502734	Jan 10 01:01:14 PM PST 24	Jan 10 01:02:40 PM PST 24	18802223 ps
T5	/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3092366596	Jan 10 01:01:16 PM PST 24	Jan 10 01:02:46 PM PST 24	81454130 ps
T8	/workspace/coverage/cover_reg_top/6.i2c_tl_errors.1377630135	Jan 10 01:01:10 PM PST 24	Jan 10 01:02:54 PM PST 24	54940996 ps
T6	/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.148860328	Jan 10 01:00:50 PM PST 24	Jan 10 01:02:02 PM PST 24	74912039 ps
T10	/workspace/coverage/cover_reg_top/13.i2c_intr_test.1733285875	Jan 10 01:01:22 PM PST 24	Jan 10 01:02:55 PM PST 24	20105078 ps
T9	/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.670816271	Jan 10 01:00:31 PM PST 24	Jan 10 01:02:29 PM PST 24	30758815 ps
T20	/workspace/coverage/cover_reg_top/13.i2c_csr_rw.2249970592	Jan 10 01:01:14 PM PST 24	Jan 10 01:02:40 PM PST 24	18771602 ps
T21	/workspace/coverage/cover_reg_top/9.i2c_csr_rw.1940810477	Jan 10 01:01:12 PM PST 24	Jan 10 01:02:36 PM PST 24	75545305 ps
T22	/workspace/coverage/cover_reg_top/3.i2c_csr_rw.3061946568	Jan 10 01:00:36 PM PST 24	Jan 10 01:01:52 PM PST 24	105738683 ps
T25	/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1868714603	Jan 10 01:01:18 PM PST 24	Jan 10 01:02:44 PM PST 24	40522849 ps
T12	/workspace/coverage/cover_reg_top/25.i2c_intr_test.1854635195	Jan 10 01:01:09 PM PST 24	Jan 10 01:02:31 PM PST 24	28416153 ps
T13	/workspace/coverage/cover_reg_top/7.i2c_tl_errors.438306397	Jan 10 01:01:16 PM PST 24	Jan 10 01:02:53 PM PST 24	91490919 ps
T28	/workspace/coverage/cover_reg_top/12.i2c_csr_rw.686581418	Jan 10 01:00:49 PM PST 24	Jan 10 01:02:28 PM PST 24	17621153 ps
T14	/workspace/coverage/cover_reg_top/11.i2c_tl_errors.1213061113	Jan 10 01:01:03 PM PST 24	Jan 10 01:02:18 PM PST 24	345559599 ps
T29	/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3422260227	Jan 10 01:00:46 PM PST 24	Jan 10 01:01:59 PM PST 24	35164733 ps
T49	/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1646045822	Jan 10 01:01:37 PM PST 24	Jan 10 01:03:02 PM PST 24	46326331 ps
T30	/workspace/coverage/cover_reg_top/8.i2c_csr_rw.375075150	Jan 10 01:01:12 PM PST 24	Jan 10 01:02:42 PM PST 24	36148600 ps
T59	/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.460206930	Jan 10 01:00:51 PM PST 24	Jan 10 01:02:10 PM PST 24	22764960 ps
T15	/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2639393645	Jan 10 01:01:07 PM PST 24	Jan 10 01:02:36 PM PST 24	456054417 ps
T64	/workspace/coverage/cover_reg_top/45.i2c_intr_test.3891589554	Jan 10 01:01:12 PM PST 24	Jan 10 01:02:42 PM PST 24	49544792 ps
T60	/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.726104731	Jan 10 01:01:21 PM PST 24	Jan 10 01:02:47 PM PST 24	59727205 ps
T65	/workspace/coverage/cover_reg_top/15.i2c_intr_test.1894183747	Jan 10 01:01:24 PM PST 24	Jan 10 01:02:50 PM PST 24	30060085 ps
T73	/workspace/coverage/cover_reg_top/36.i2c_intr_test.2273707582	Jan 10 01:01:08 PM PST 24	Jan 10 01:02:32 PM PST 24	38137809 ps
T74	/workspace/coverage/cover_reg_top/19.i2c_intr_test.188043665	Jan 10 01:00:58 PM PST 24	Jan 10 01:02:15 PM PST 24	44908059 ps
T75	/workspace/coverage/cover_reg_top/28.i2c_intr_test.3232296139	Jan 10 01:01:14 PM PST 24	Jan 10 01:02:50 PM PST 24	21526521 ps
T16	/workspace/coverage/cover_reg_top/5.i2c_tl_errors.1022081610	Jan 10 01:01:12 PM PST 24	Jan 10 01:02:42 PM PST 24	69268753 ps
T79	/workspace/coverage/cover_reg_top/27.i2c_intr_test.55795579	Jan 10 01:00:54 PM PST 24	Jan 10 01:02:04 PM PST 24	15248378 ps
T50	/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1772543272	Jan 10 01:00:36 PM PST 24	Jan 10 01:01:52 PM PST 24	83477723 ps
T76	/workspace/coverage/cover_reg_top/47.i2c_intr_test.4242556219	Jan 10 01:01:03 PM PST 24	Jan 10 01:02:25 PM PST 24	62573094 ps
T77	/workspace/coverage/cover_reg_top/22.i2c_intr_test.2227444533	Jan 10 01:01:24 PM PST 24	Jan 10 01:02:54 PM PST 24	44318377 ps
T31	/workspace/coverage/cover_reg_top/2.i2c_csr_rw.2409803441	Jan 10 01:00:36 PM PST 24	Jan 10 01:02:03 PM PST 24	60777342 ps
T17	/workspace/coverage/cover_reg_top/2.i2c_tl_errors.777106164	Jan 10 01:00:46 PM PST 24	Jan 10 01:02:03 PM PST 24	70069447 ps
T78	/workspace/coverage/cover_reg_top/24.i2c_intr_test.1795740625	Jan 10 01:01:16 PM PST 24	Jan 10 01:02:45 PM PST 24	16124284 ps
T18	/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.934608743	Jan 10 01:00:49 PM PST 24	Jan 10 01:01:59 PM PST 24	227246446 ps
T19	/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1172094533	Jan 10 01:00:49 PM PST 24	Jan 10 01:01:59 PM PST 24	61952574 ps
T66	/workspace/coverage/cover_reg_top/23.i2c_intr_test.3996947839	Jan 10 01:01:11 PM PST 24	Jan 10 01:02:35 PM PST 24	31009902 ps
T23	/workspace/coverage/cover_reg_top/12.i2c_tl_errors.2787584313	Jan 10 01:00:50 PM PST 24	Jan 10 01:02:10 PM PST 24	134926846 ps
T26	/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2856096129	Jan 10 01:01:03 PM PST 24	Jan 10 01:02:52 PM PST 24	254887048 ps
T24	/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3133020035	Jan 10 01:00:50 PM PST 24	Jan 10 01:02:14 PM PST 24	101915482 ps
T32	/workspace/coverage/cover_reg_top/0.i2c_csr_rw.2076722927	Jan 10 01:00:40 PM PST 24	Jan 10 01:02:03 PM PST 24	23210275 ps
T51	/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.84855885	Jan 10 01:01:15 PM PST 24	Jan 10 01:02:47 PM PST 24	1830437687 ps
T27	/workspace/coverage/cover_reg_top/18.i2c_tl_errors.3435992602	Jan 10 01:01:15 PM PST 24	Jan 10 01:02:41 PM PST 24	182442479 ps
T87	/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1922620013	Jan 10 01:01:00 PM PST 24	Jan 10 01:02:20 PM PST 24	63485338 ps
T33	/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.601937869	Jan 10 01:01:22 PM PST 24	Jan 10 01:02:49 PM PST 24	18434140 ps
T34	/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2057138663	Jan 10 01:00:50 PM PST 24	Jan 10 01:02:03 PM PST 24	124787535 ps
T88	/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2253780975	Jan 10 01:01:06 PM PST 24	Jan 10 01:02:27 PM PST 24	19182126 ps
T35	/workspace/coverage/cover_reg_top/11.i2c_csr_rw.3313603581	Jan 10 01:01:14 PM PST 24	Jan 10 01:02:47 PM PST 24	20075052 ps
T36	/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1068010005	Jan 10 01:01:05 PM PST 24	Jan 10 01:02:30 PM PST 24	18507362 ps
T89	/workspace/coverage/cover_reg_top/3.i2c_tl_errors.690569662	Jan 10 01:00:31 PM PST 24	Jan 10 01:01:53 PM PST 24	46386100 ps
T55	/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.60603371	Jan 10 01:00:51 PM PST 24	Jan 10 01:02:11 PM PST 24	88103858 ps
T81	/workspace/coverage/cover_reg_top/6.i2c_intr_test.1193664342	Jan 10 01:01:15 PM PST 24	Jan 10 01:02:50 PM PST 24	16184639 ps
T86	/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2343155468	Jan 10 01:01:21 PM PST 24	Jan 10 01:02:46 PM PST 24	69846046 ps
T61	/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3987899984	Jan 10 01:00:50 PM PST 24	Jan 10 01:02:14 PM PST 24	36078682 ps
T90	/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.799127472	Jan 10 01:00:46 PM PST 24	Jan 10 01:01:57 PM PST 24	55091971 ps
T84	/workspace/coverage/cover_reg_top/0.i2c_intr_test.1765640819	Jan 10 01:00:36 PM PST 24	Jan 10 01:02:19 PM PST 24	51808506 ps
T62	/workspace/coverage/cover_reg_top/19.i2c_tl_errors.2760183777	Jan 10 01:01:13 PM PST 24	Jan 10 01:02:44 PM PST 24	191654404 ps
T52	/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1614513158	Jan 10 01:01:17 PM PST 24	Jan 10 01:02:50 PM PST 24	311543263 ps
T63	/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1440916738	Jan 10 01:00:58 PM PST 24	Jan 10 01:02:49 PM PST 24	169928133 ps
T91	/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1954436682	Jan 10 01:01:08 PM PST 24	Jan 10 01:02:42 PM PST 24	56041797 ps
T67	/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1392596218	Jan 10 01:00:40 PM PST 24	Jan 10 01:02:03 PM PST 24	55602116 ps
T71	/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1629369861	Jan 10 01:01:12 PM PST 24	Jan 10 01:02:38 PM PST 24	426635261 ps
T92	/workspace/coverage/cover_reg_top/0.i2c_tl_errors.1063581500	Jan 10 01:01:02 PM PST 24	Jan 10 01:02:34 PM PST 24	149561224 ps
T93	/workspace/coverage/cover_reg_top/15.i2c_tl_errors.1539316643	Jan 10 01:01:41 PM PST 24	Jan 10 01:03:16 PM PST 24	123126154 ps
T94	/workspace/coverage/cover_reg_top/18.i2c_csr_rw.4273564921	Jan 10 01:01:22 PM PST 24	Jan 10 01:02:49 PM PST 24	25361055 ps
T80	/workspace/coverage/cover_reg_top/10.i2c_intr_test.3081980498	Jan 10 01:00:44 PM PST 24	Jan 10 01:02:30 PM PST 24	28994714 ps
T95	/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.170924464	Jan 10 01:00:50 PM PST 24	Jan 10 01:02:03 PM PST 24	124434480 ps
T96	/workspace/coverage/cover_reg_top/11.i2c_intr_test.1844947542	Jan 10 01:00:45 PM PST 24	Jan 10 01:02:24 PM PST 24	18197829 ps
T85	/workspace/coverage/cover_reg_top/37.i2c_intr_test.1131980662	Jan 10 01:01:39 PM PST 24	Jan 10 01:03:23 PM PST 24	52707303 ps
T82	/workspace/coverage/cover_reg_top/9.i2c_intr_test.976282005	Jan 10 01:00:50 PM PST 24	Jan 10 01:02:14 PM PST 24	40230607 ps
T72	/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3275006957	Jan 10 01:01:12 PM PST 24	Jan 10 01:02:37 PM PST 24	144000700 ps
T97	/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1276597881	Jan 10 01:01:18 PM PST 24	Jan 10 01:02:53 PM PST 24	4070480402 ps
T98	/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2848808391	Jan 10 01:01:18 PM PST 24	Jan 10 01:02:50 PM PST 24	115646491 ps
T99	/workspace/coverage/cover_reg_top/16.i2c_tl_errors.2344394370	Jan 10 01:01:14 PM PST 24	Jan 10 01:02:42 PM PST 24	217049249 ps
T37	/workspace/coverage/cover_reg_top/16.i2c_csr_rw.1946692922	Jan 10 01:00:49 PM PST 24	Jan 10 01:02:12 PM PST 24	27844820 ps
T42	/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3395951503	Jan 10 01:00:41 PM PST 24	Jan 10 01:02:14 PM PST 24	33294792 ps
T100	/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1297953885	Jan 10 01:01:14 PM PST 24	Jan 10 01:02:45 PM PST 24	26140772 ps
T101	/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2399268976	Jan 10 01:01:08 PM PST 24	Jan 10 01:02:34 PM PST 24	25553412 ps
T102	/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3338008867	Jan 10 01:01:16 PM PST 24	Jan 10 01:02:57 PM PST 24	46475519 ps
T38	/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1003542304	Jan 10 01:00:37 PM PST 24	Jan 10 01:01:57 PM PST 24	25392110 ps
T43	/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.133215622	Jan 10 01:01:05 PM PST 24	Jan 10 01:02:30 PM PST 24	120136876 ps
T44	/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3309061591	Jan 10 01:01:24 PM PST 24	Jan 10 01:02:54 PM PST 24	43893585 ps
T45	/workspace/coverage/cover_reg_top/2.i2c_intr_test.2106868729	Jan 10 01:00:27 PM PST 24	Jan 10 01:01:49 PM PST 24	18517206 ps
T46	/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4211399645	Jan 10 01:01:17 PM PST 24	Jan 10 01:02:48 PM PST 24	86551523 ps
T47	/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1714271906	Jan 10 01:00:51 PM PST 24	Jan 10 01:02:36 PM PST 24	41453132 ps
T48	/workspace/coverage/cover_reg_top/34.i2c_intr_test.799843787	Jan 10 01:01:29 PM PST 24	Jan 10 01:02:59 PM PST 24	46790737 ps
T103	/workspace/coverage/cover_reg_top/42.i2c_intr_test.238748915	Jan 10 01:01:03 PM PST 24	Jan 10 01:02:25 PM PST 24	15119644 ps
T83	/workspace/coverage/cover_reg_top/41.i2c_intr_test.26738183	Jan 10 01:01:13 PM PST 24	Jan 10 01:02:53 PM PST 24	86707329 ps
T104	/workspace/coverage/cover_reg_top/5.i2c_csr_rw.3970616015	Jan 10 01:01:11 PM PST 24	Jan 10 01:02:48 PM PST 24	43824336 ps
T56	/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.764150291	Jan 10 01:01:25 PM PST 24	Jan 10 01:02:54 PM PST 24	271937718 ps
T105	/workspace/coverage/cover_reg_top/48.i2c_intr_test.500173912	Jan 10 01:01:08 PM PST 24	Jan 10 01:02:34 PM PST 24	21137108 ps
T106	/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1270443412	Jan 10 01:00:44 PM PST 24	Jan 10 01:02:05 PM PST 24	90323429 ps
T68	/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.150339636	Jan 10 01:01:10 PM PST 24	Jan 10 01:02:32 PM PST 24	54789743 ps
T107	/workspace/coverage/cover_reg_top/1.i2c_csr_rw.3961134650	Jan 10 01:00:23 PM PST 24	Jan 10 01:02:05 PM PST 24	24009457 ps
T108	/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1011426715	Jan 10 01:00:36 PM PST 24	Jan 10 01:02:03 PM PST 24	616332998 ps
T109	/workspace/coverage/cover_reg_top/8.i2c_intr_test.1411576349	Jan 10 01:00:50 PM PST 24	Jan 10 01:02:10 PM PST 24	59385590 ps
T110	/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3566347974	Jan 10 01:00:50 PM PST 24	Jan 10 01:02:03 PM PST 24	50511504 ps
T111	/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3720053275	Jan 10 01:01:03 PM PST 24	Jan 10 01:02:25 PM PST 24	46916011 ps
T112	/workspace/coverage/cover_reg_top/5.i2c_intr_test.344516590	Jan 10 01:00:40 PM PST 24	Jan 10 01:01:58 PM PST 24	52904350 ps
T57	/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1078179432	Jan 10 01:01:09 PM PST 24	Jan 10 01:03:00 PM PST 24	1402600883 ps
T70	/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.897506760	Jan 10 01:00:45 PM PST 24	Jan 10 01:02:30 PM PST 24	32640381 ps
T113	/workspace/coverage/cover_reg_top/26.i2c_intr_test.3547173214	Jan 10 01:00:50 PM PST 24	Jan 10 01:02:14 PM PST 24	25663912 ps
T114	/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1952791327	Jan 10 01:01:19 PM PST 24	Jan 10 01:03:00 PM PST 24	67954545 ps
T115	/workspace/coverage/cover_reg_top/43.i2c_intr_test.560740758	Jan 10 01:01:02 PM PST 24	Jan 10 01:02:30 PM PST 24	17910447 ps
T39	/workspace/coverage/cover_reg_top/4.i2c_csr_rw.2698585885	Jan 10 01:00:45 PM PST 24	Jan 10 01:02:05 PM PST 24	41769663 ps
T58	/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1680229532	Jan 10 01:00:27 PM PST 24	Jan 10 01:01:52 PM PST 24	78814302 ps
T116	/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.31022944	Jan 10 01:00:35 PM PST 24	Jan 10 01:02:15 PM PST 24	111668852 ps
T117	/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.432833177	Jan 10 01:00:46 PM PST 24	Jan 10 01:01:57 PM PST 24	32738727 ps
T118	/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3268405985	Jan 10 01:00:31 PM PST 24	Jan 10 01:02:15 PM PST 24	45575491 ps
T119	/workspace/coverage/cover_reg_top/10.i2c_tl_errors.1689177897	Jan 10 01:01:20 PM PST 24	Jan 10 01:02:49 PM PST 24	195801905 ps
T120	/workspace/coverage/cover_reg_top/32.i2c_intr_test.3262611029	Jan 10 01:01:35 PM PST 24	Jan 10 01:03:00 PM PST 24	43221408 ps
T121	/workspace/coverage/cover_reg_top/44.i2c_intr_test.1422052861	Jan 10 01:01:19 PM PST 24	Jan 10 01:02:53 PM PST 24	62563627 ps
T40	/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.4032843158	Jan 10 01:00:41 PM PST 24	Jan 10 01:02:37 PM PST 24	860275861 ps
T122	/workspace/coverage/cover_reg_top/40.i2c_intr_test.3156389204	Jan 10 01:01:08 PM PST 24	Jan 10 01:02:42 PM PST 24	40904362 ps
T123	/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3064334989	Jan 10 01:01:17 PM PST 24	Jan 10 01:02:48 PM PST 24	55643987 ps
T41	/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.692857366	Jan 10 01:00:36 PM PST 24	Jan 10 01:02:03 PM PST 24	37359578 ps
T124	/workspace/coverage/cover_reg_top/31.i2c_intr_test.1622269884	Jan 10 01:00:58 PM PST 24	Jan 10 01:02:15 PM PST 24	18030205 ps
T125	/workspace/coverage/cover_reg_top/17.i2c_tl_errors.761082543	Jan 10 01:01:22 PM PST 24	Jan 10 01:02:53 PM PST 24	167366285 ps
T126	/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1853535976	Jan 10 01:01:02 PM PST 24	Jan 10 01:02:30 PM PST 24	22742535 ps
T127	/workspace/coverage/cover_reg_top/7.i2c_csr_rw.2530845651	Jan 10 01:00:48 PM PST 24	Jan 10 01:02:14 PM PST 24	57638562 ps
T128	/workspace/coverage/cover_reg_top/13.i2c_tl_errors.2106547277	Jan 10 01:01:11 PM PST 24	Jan 10 01:02:50 PM PST 24	158047788 ps
T129	/workspace/coverage/cover_reg_top/39.i2c_intr_test.1520822509	Jan 10 01:01:17 PM PST 24	Jan 10 01:02:48 PM PST 24	16626016 ps
T130	/workspace/coverage/cover_reg_top/33.i2c_intr_test.1548382437	Jan 10 01:01:04 PM PST 24	Jan 10 01:02:22 PM PST 24	39131786 ps
T131	/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1907470266	Jan 10 01:00:46 PM PST 24	Jan 10 01:01:57 PM PST 24	37880208 ps
T132	/workspace/coverage/cover_reg_top/14.i2c_intr_test.4196969138	Jan 10 01:01:12 PM PST 24	Jan 10 01:02:35 PM PST 24	22075835 ps
T133	/workspace/coverage/cover_reg_top/29.i2c_intr_test.637781438	Jan 10 01:01:12 PM PST 24	Jan 10 01:02:43 PM PST 24	21849808 ps
T134	/workspace/coverage/cover_reg_top/6.i2c_csr_rw.701836372	Jan 10 01:01:17 PM PST 24	Jan 10 01:02:48 PM PST 24	48823950 ps
T135	/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.458238463	Jan 10 01:01:17 PM PST 24	Jan 10 01:02:46 PM PST 24	152943925 ps
T136	/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.4107159449	Jan 10 01:01:07 PM PST 24	Jan 10 01:02:35 PM PST 24	48504366 ps
T137	/workspace/coverage/cover_reg_top/35.i2c_intr_test.2748633037	Jan 10 01:01:02 PM PST 24	Jan 10 01:02:30 PM PST 24	70002120 ps
T138	/workspace/coverage/cover_reg_top/4.i2c_tl_errors.487661664	Jan 10 01:00:46 PM PST 24	Jan 10 01:02:05 PM PST 24	121785432 ps
T139	/workspace/coverage/cover_reg_top/18.i2c_intr_test.2229821921	Jan 10 01:01:12 PM PST 24	Jan 10 01:02:37 PM PST 24	16592923 ps
T140	/workspace/coverage/cover_reg_top/7.i2c_intr_test.3282064260	Jan 10 01:01:18 PM PST 24	Jan 10 01:02:49 PM PST 24	16171098 ps
T141	/workspace/coverage/cover_reg_top/4.i2c_intr_test.1731534620	Jan 10 01:00:40 PM PST 24	Jan 10 01:01:59 PM PST 24	21556193 ps
T53	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1607176453	Jan 10 01:01:08 PM PST 24	Jan 10 01:02:34 PM PST 24	126841125 ps
T142	/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2076331538	Jan 10 01:00:32 PM PST 24	Jan 10 01:02:02 PM PST 24	328161927 ps
T143	/workspace/coverage/cover_reg_top/1.i2c_tl_errors.3373835331	Jan 10 01:00:33 PM PST 24	Jan 10 01:02:11 PM PST 24	36995622 ps
T54	/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1299435116	Jan 10 01:00:53 PM PST 24	Jan 10 01:02:26 PM PST 24	269373190 ps
T144	/workspace/coverage/cover_reg_top/20.i2c_intr_test.1974591574	Jan 10 01:01:21 PM PST 24	Jan 10 01:02:47 PM PST 24	43997101 ps
T145	/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2937360051	Jan 10 01:00:28 PM PST 24	Jan 10 01:01:52 PM PST 24	35026009 ps
T146	/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3130327592	Jan 10 01:01:16 PM PST 24	Jan 10 01:02:58 PM PST 24	61012650 ps
T147	/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3405056694	Jan 10 01:00:46 PM PST 24	Jan 10 01:02:00 PM PST 24	72122725 ps
T69	/workspace/coverage/cover_reg_top/15.i2c_csr_rw.1624284691	Jan 10 01:01:12 PM PST 24	Jan 10 01:02:36 PM PST 24	20091578 ps
T148	/workspace/coverage/cover_reg_top/10.i2c_csr_rw.3020121194	Jan 10 01:00:49 PM PST 24	Jan 10 01:02:12 PM PST 24	21867254 ps
T149	/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2096857777	Jan 10 01:01:10 PM PST 24	Jan 10 01:02:38 PM PST 24	47241270 ps
T150	/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.888796400	Jan 10 01:00:47 PM PST 24	Jan 10 01:01:57 PM PST 24	31352329 ps
T151	/workspace/coverage/cover_reg_top/1.i2c_intr_test.3032721707	Jan 10 01:00:59 PM PST 24	Jan 10 01:02:30 PM PST 24	44312578 ps
T152	/workspace/coverage/cover_reg_top/21.i2c_intr_test.4135167824	Jan 10 01:01:20 PM PST 24	Jan 10 01:02:47 PM PST 24	14653046 ps
T153	/workspace/coverage/cover_reg_top/14.i2c_csr_rw.1441778657	Jan 10 01:01:06 PM PST 24	Jan 10 01:02:26 PM PST 24	52768404 ps
T154	/workspace/coverage/cover_reg_top/8.i2c_tl_errors.2558048727	Jan 10 01:00:49 PM PST 24	Jan 10 01:02:00 PM PST 24	541653328 ps

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.122511437
Short name	T2
Test name
Test status
Simulation time	2813777472 ps
CPU time	2.28 seconds
Started	Jan 10 01:00:37 PM PST 24
Finished	Jan 10 01:01:53 PM PST 24
Peak memory	202904 kb
Host	smart-6aad123b-3766-47fe-be06-112e62a577ed
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122511437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.122511437
Directory	/workspace/1.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_intr_test.622502734
Short name	T11
Test name
Test status
Simulation time	18802223 ps
CPU time	0.68 seconds
Started	Jan 10 01:01:14 PM PST 24
Finished	Jan 10 01:02:40 PM PST 24
Peak memory	202668 kb
Host	smart-9aef2906-e91b-4a08-a6cb-af04542747bd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622502734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.622502734
Directory	/workspace/16.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_tl_errors.438306397
Short name	T13
Test name
Test status
Simulation time	91490919 ps
CPU time	1.61 seconds
Started	Jan 10 01:01:16 PM PST 24
Finished	Jan 10 01:02:53 PM PST 24
Peak memory	202920 kb
Host	smart-8e3fa047-7b7b-458e-9336-cccf0f1a1a0d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438306397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.438306397
Directory	/workspace/7.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/28.i2c_intr_test.3232296139
Short name	T75
Test name
Test status
Simulation time	21526521 ps
CPU time	0.65 seconds
Started	Jan 10 01:01:14 PM PST 24
Finished	Jan 10 01:02:50 PM PST 24
Peak memory	202680 kb
Host	smart-8c0af337-67de-4cad-8395-a0648cb5be7f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232296139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.3232296139
Directory	/workspace/28.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2639393645
Short name	T15
Test name
Test status
Simulation time	456054417 ps
CPU time	1.84 seconds
Started	Jan 10 01:01:07 PM PST 24
Finished	Jan 10 01:02:36 PM PST 24
Peak memory	202944 kb
Host	smart-febf505f-cfa8-42f3-88ee-a01691e83246
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639393645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.2639393645
Directory	/workspace/14.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1068010005
Short name	T36
Test name
Test status
Simulation time	18507362 ps
CPU time	0.71 seconds
Started	Jan 10 01:01:05 PM PST 24
Finished	Jan 10 01:02:30 PM PST 24
Peak memory	202708 kb
Host	smart-32b67baa-2680-4457-8612-2399b04a9577
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068010005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.1068010005
Directory	/workspace/2.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_intr_test.1193664342
Short name	T81
Test name
Test status
Simulation time	16184639 ps
CPU time	0.69 seconds
Started	Jan 10 01:01:15 PM PST 24
Finished	Jan 10 01:02:50 PM PST 24
Peak memory	202704 kb
Host	smart-2498bed8-f218-43d3-88b6-902892840c6e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193664342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1193664342
Directory	/workspace/6.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_csr_rw.2249970592
Short name	T20
Test name
Test status
Simulation time	18771602 ps
CPU time	0.71 seconds
Started	Jan 10 01:01:14 PM PST 24
Finished	Jan 10 01:02:40 PM PST 24
Peak memory	202640 kb
Host	smart-ae296fd7-d2a3-40bc-b18c-94e1dcd3cc46
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249970592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.2249970592
Directory	/workspace/13.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.764150291
Short name	T56
Test name
Test status
Simulation time	271937718 ps
CPU time	1.76 seconds
Started	Jan 10 01:01:25 PM PST 24
Finished	Jan 10 01:02:54 PM PST 24
Peak memory	203032 kb
Host	smart-202aac3f-d5a0-4999-9def-5e6556b54d67
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764150291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.764150291
Directory	/workspace/15.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.4032843158
Short name	T40
Test name
Test status
Simulation time	860275861 ps
CPU time	4.2 seconds
Started	Jan 10 01:00:41 PM PST 24
Finished	Jan 10 01:02:37 PM PST 24
Peak memory	202888 kb
Host	smart-1974bae7-4adf-426f-b434-2bb169304ad9
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032843158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.4032843158
Directory	/workspace/0.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/29.i2c_intr_test.637781438
Short name	T133
Test name
Test status
Simulation time	21849808 ps
CPU time	0.65 seconds
Started	Jan 10 01:01:12 PM PST 24
Finished	Jan 10 01:02:43 PM PST 24
Peak memory	202692 kb
Host	smart-94de9cf4-c797-4fc5-a613-a903f366b4a6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637781438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.637781438
Directory	/workspace/29.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.150339636
Short name	T68
Test name
Test status
Simulation time	54789743 ps
CPU time	0.78 seconds
Started	Jan 10 01:01:10 PM PST 24
Finished	Jan 10 01:02:32 PM PST 24
Peak memory	202632 kb
Host	smart-65e868d0-d11b-4699-ba6f-76d2bf3a201d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150339636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_out standing.150339636
Directory	/workspace/3.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_tl_errors.2760183777
Short name	T62
Test name
Test status
Simulation time	191654404 ps
CPU time	1.96 seconds
Started	Jan 10 01:01:13 PM PST 24
Finished	Jan 10 01:02:44 PM PST 24
Peak memory	202912 kb
Host	smart-f8ea7bee-f9db-4272-9864-b75f31784a38
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760183777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2760183777
Directory	/workspace/19.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/40.i2c_intr_test.3156389204
Short name	T122
Test name
Test status
Simulation time	40904362 ps
CPU time	0.6 seconds
Started	Jan 10 01:01:08 PM PST 24
Finished	Jan 10 01:02:42 PM PST 24
Peak memory	202592 kb
Host	smart-ff895f11-cd63-41c8-a8ad-d7a7700a8dbc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156389204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.3156389204
Directory	/workspace/40.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4211399645
Short name	T46
Test name
Test status
Simulation time	86551523 ps
CPU time	0.77 seconds
Started	Jan 10 01:01:17 PM PST 24
Finished	Jan 10 01:02:48 PM PST 24
Peak memory	202764 kb
Host	smart-e9d40303-b61f-4d2b-a980-13662af5d799
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211399645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou tstanding.4211399645
Directory	/workspace/8.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1614513158
Short name	T52
Test name
Test status
Simulation time	311543263 ps
CPU time	1.77 seconds
Started	Jan 10 01:01:17 PM PST 24
Finished	Jan 10 01:02:50 PM PST 24
Peak memory	203016 kb
Host	smart-f0119ff4-8421-46fa-8197-fbab088a0c1e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614513158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.1614513158
Directory	/workspace/5.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1270443412
Short name	T106
Test name
Test status
Simulation time	90323429 ps
CPU time	1.01 seconds
Started	Jan 10 01:00:44 PM PST 24
Finished	Jan 10 01:02:05 PM PST 24
Peak memory	202740 kb
Host	smart-deec81c3-54c9-4241-9220-f676ee31c0f0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270443412 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1270443412
Directory	/workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_csr_rw.1624284691
Short name	T69
Test name
Test status
Simulation time	20091578 ps
CPU time	0.63 seconds
Started	Jan 10 01:01:12 PM PST 24
Finished	Jan 10 01:02:36 PM PST 24
Peak memory	201744 kb
Host	smart-72951c62-323b-4d8d-a364-e06074119a79
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624284691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1624284691
Directory	/workspace/15.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1607176453
Short name	T53
Test name
Test status
Simulation time	126841125 ps
CPU time	1.34 seconds
Started	Jan 10 01:01:08 PM PST 24
Finished	Jan 10 01:02:34 PM PST 24
Peak memory	202976 kb
Host	smart-e306c03c-b5fe-4c97-ab74-a66f1a961a69
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607176453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.1607176453
Directory	/workspace/1.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.60603371
Short name	T55
Test name
Test status
Simulation time	88103858 ps
CPU time	1.71 seconds
Started	Jan 10 01:00:51 PM PST 24
Finished	Jan 10 01:02:11 PM PST 24
Peak memory	202900 kb
Host	smart-434fd085-e55c-4f6a-bb87-ae7323a69457
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60603371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.60603371
Directory	/workspace/11.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1853535976
Short name	T126
Test name
Test status
Simulation time	22742535 ps
CPU time	0.91 seconds
Started	Jan 10 01:01:02 PM PST 24
Finished	Jan 10 01:02:30 PM PST 24
Peak memory	202636 kb
Host	smart-9214b831-e401-49d1-b2f8-5c032835a195
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853535976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1853535976
Directory	/workspace/0.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3422260227
Short name	T29
Test name
Test status
Simulation time	35164733 ps
CPU time	0.69 seconds
Started	Jan 10 01:00:46 PM PST 24
Finished	Jan 10 01:01:59 PM PST 24
Peak memory	202764 kb
Host	smart-4fee8e81-c897-4429-8cc5-75eaa85c1605
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422260227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.3422260227
Directory	/workspace/0.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.670816271
Short name	T9
Test name
Test status
Simulation time	30758815 ps
CPU time	0.9 seconds
Started	Jan 10 01:00:31 PM PST 24
Finished	Jan 10 01:02:29 PM PST 24
Peak memory	202808 kb
Host	smart-f71a69d7-510e-423b-8f40-4de2b40136ac
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670816271 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.670816271
Directory	/workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_rw.2076722927
Short name	T32
Test name
Test status
Simulation time	23210275 ps
CPU time	0.64 seconds
Started	Jan 10 01:00:40 PM PST 24
Finished	Jan 10 01:02:03 PM PST 24
Peak memory	202116 kb
Host	smart-6149fc74-cf59-4256-90bc-0d694c3cf5d1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076722927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.2076722927
Directory	/workspace/0.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_intr_test.1765640819
Short name	T84
Test name
Test status
Simulation time	51808506 ps
CPU time	0.61 seconds
Started	Jan 10 01:00:36 PM PST 24
Finished	Jan 10 01:02:19 PM PST 24
Peak memory	202676 kb
Host	smart-ba4051c4-5e5c-41b3-a249-97744f7d2385
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765640819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1765640819
Directory	/workspace/0.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1772543272
Short name	T50
Test name
Test status
Simulation time	83477723 ps
CPU time	0.72 seconds
Started	Jan 10 01:00:36 PM PST 24
Finished	Jan 10 01:01:52 PM PST 24
Peak memory	202628 kb
Host	smart-8c644012-bf12-4a84-8266-0530fb98ba28
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772543272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou tstanding.1772543272
Directory	/workspace/0.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_tl_errors.1063581500
Short name	T92
Test name
Test status
Simulation time	149561224 ps
CPU time	1.23 seconds
Started	Jan 10 01:01:02 PM PST 24
Finished	Jan 10 01:02:34 PM PST 24
Peak memory	202904 kb
Host	smart-8b25c211-033a-4781-9661-7675ef24a757
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063581500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1063581500
Directory	/workspace/0.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1629369861
Short name	T71
Test name
Test status
Simulation time	426635261 ps
CPU time	1.82 seconds
Started	Jan 10 01:01:12 PM PST 24
Finished	Jan 10 01:02:38 PM PST 24
Peak memory	202908 kb
Host	smart-df178231-148a-45ea-97db-a736cdceb40a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629369861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.1629369861
Directory	/workspace/0.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1003542304
Short name	T38
Test name
Test status
Simulation time	25392110 ps
CPU time	0.93 seconds
Started	Jan 10 01:00:37 PM PST 24
Finished	Jan 10 01:01:57 PM PST 24
Peak memory	202680 kb
Host	smart-203d12ef-3101-4669-a753-40aaa4649542
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003542304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.1003542304
Directory	/workspace/1.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3268405985
Short name	T118
Test name
Test status
Simulation time	45575491 ps
CPU time	0.69 seconds
Started	Jan 10 01:00:31 PM PST 24
Finished	Jan 10 01:02:15 PM PST 24
Peak memory	202696 kb
Host	smart-32efc456-b168-4b02-93ab-8f6234c4a3d4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268405985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.3268405985
Directory	/workspace/1.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_rw.3961134650
Short name	T107
Test name
Test status
Simulation time	24009457 ps
CPU time	0.7 seconds
Started	Jan 10 01:00:23 PM PST 24
Finished	Jan 10 01:02:05 PM PST 24
Peak memory	202672 kb
Host	smart-96999cf7-c1df-4e4d-a49d-5632dd67c209
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961134650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.3961134650
Directory	/workspace/1.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_intr_test.3032721707
Short name	T151
Test name
Test status
Simulation time	44312578 ps
CPU time	0.64 seconds
Started	Jan 10 01:00:59 PM PST 24
Finished	Jan 10 01:02:30 PM PST 24
Peak memory	202660 kb
Host	smart-2eb6a381-6faf-4e20-94cf-5e368333647c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032721707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3032721707
Directory	/workspace/1.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2937360051
Short name	T145
Test name
Test status
Simulation time	35026009 ps
CPU time	0.79 seconds
Started	Jan 10 01:00:28 PM PST 24
Finished	Jan 10 01:01:52 PM PST 24
Peak memory	202752 kb
Host	smart-37c1bdef-fc29-4cc9-ac78-799bf3cf8649
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937360051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou tstanding.2937360051
Directory	/workspace/1.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_tl_errors.3373835331
Short name	T143
Test name
Test status
Simulation time	36995622 ps
CPU time	1.72 seconds
Started	Jan 10 01:00:33 PM PST 24
Finished	Jan 10 01:02:11 PM PST 24
Peak memory	202952 kb
Host	smart-d7b32861-0b0a-4caf-8285-8a37d88023f9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373835331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.3373835331
Directory	/workspace/1.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3133020035
Short name	T24
Test name
Test status
Simulation time	101915482 ps
CPU time	0.86 seconds
Started	Jan 10 01:00:50 PM PST 24
Finished	Jan 10 01:02:14 PM PST 24
Peak memory	202876 kb
Host	smart-98fa246e-9aa6-4db4-9874-6c9d2e07d189
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133020035 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.3133020035
Directory	/workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_csr_rw.3020121194
Short name	T148
Test name
Test status
Simulation time	21867254 ps
CPU time	0.63 seconds
Started	Jan 10 01:00:49 PM PST 24
Finished	Jan 10 01:02:12 PM PST 24
Peak memory	202616 kb
Host	smart-f7e13df0-c1ec-4625-a877-d90b85f5cfc1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020121194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3020121194
Directory	/workspace/10.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_intr_test.3081980498
Short name	T80
Test name
Test status
Simulation time	28994714 ps
CPU time	0.64 seconds
Started	Jan 10 01:00:44 PM PST 24
Finished	Jan 10 01:02:30 PM PST 24
Peak memory	202752 kb
Host	smart-1a0ffcdb-86fa-4d90-87b2-5cede7039a70
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081980498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3081980498
Directory	/workspace/10.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3987899984
Short name	T61
Test name
Test status
Simulation time	36078682 ps
CPU time	0.88 seconds
Started	Jan 10 01:00:50 PM PST 24
Finished	Jan 10 01:02:14 PM PST 24
Peak memory	202784 kb
Host	smart-9ba1452b-e5b0-42b5-883b-f74d24e0f06e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987899984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o utstanding.3987899984
Directory	/workspace/10.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_tl_errors.1689177897
Short name	T119
Test name
Test status
Simulation time	195801905 ps
CPU time	2.61 seconds
Started	Jan 10 01:01:20 PM PST 24
Finished	Jan 10 01:02:49 PM PST 24
Peak memory	203004 kb
Host	smart-17701e9c-e7e0-4da2-8fe5-ee9787aa8c70
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689177897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1689177897
Directory	/workspace/10.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.4107159449
Short name	T136
Test name
Test status
Simulation time	48504366 ps
CPU time	1.16 seconds
Started	Jan 10 01:01:07 PM PST 24
Finished	Jan 10 01:02:35 PM PST 24
Peak memory	202816 kb
Host	smart-c7b8c9b2-9657-49d2-b6dc-5d22fc00b59d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107159449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.4107159449
Directory	/workspace/10.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.432833177
Short name	T117
Test name
Test status
Simulation time	32738727 ps
CPU time	0.89 seconds
Started	Jan 10 01:00:46 PM PST 24
Finished	Jan 10 01:01:57 PM PST 24
Peak memory	202828 kb
Host	smart-d9878b72-833b-481f-8f1a-4939019c0469
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432833177 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.432833177
Directory	/workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_csr_rw.3313603581
Short name	T35
Test name
Test status
Simulation time	20075052 ps
CPU time	0.69 seconds
Started	Jan 10 01:01:14 PM PST 24
Finished	Jan 10 01:02:47 PM PST 24
Peak memory	202904 kb
Host	smart-f625b33d-9695-446e-a314-1202f58333cc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313603581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.3313603581
Directory	/workspace/11.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_intr_test.1844947542
Short name	T96
Test name
Test status
Simulation time	18197829 ps
CPU time	0.64 seconds
Started	Jan 10 01:00:45 PM PST 24
Finished	Jan 10 01:02:24 PM PST 24
Peak memory	202732 kb
Host	smart-fe08beda-a9a0-4326-af34-9021567560c9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844947542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1844947542
Directory	/workspace/11.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2057138663
Short name	T34
Test name
Test status
Simulation time	124787535 ps
CPU time	0.85 seconds
Started	Jan 10 01:00:50 PM PST 24
Finished	Jan 10 01:02:03 PM PST 24
Peak memory	202776 kb
Host	smart-8cc3fae4-319f-42e8-a95c-f22808eb404f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057138663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o utstanding.2057138663
Directory	/workspace/11.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_tl_errors.1213061113
Short name	T14
Test name
Test status
Simulation time	345559599 ps
CPU time	1.54 seconds
Started	Jan 10 01:01:03 PM PST 24
Finished	Jan 10 01:02:18 PM PST 24
Peak memory	202992 kb
Host	smart-7d4566a4-b6b9-48a4-93fe-6fec023d4180
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213061113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1213061113
Directory	/workspace/11.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3338008867
Short name	T102
Test name
Test status
Simulation time	46475519 ps
CPU time	0.67 seconds
Started	Jan 10 01:01:16 PM PST 24
Finished	Jan 10 01:02:57 PM PST 24
Peak memory	202764 kb
Host	smart-91fa2c52-3162-4837-9366-da4f7160443b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338008867 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3338008867
Directory	/workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_csr_rw.686581418
Short name	T28
Test name
Test status
Simulation time	17621153 ps
CPU time	0.61 seconds
Started	Jan 10 01:00:49 PM PST 24
Finished	Jan 10 01:02:28 PM PST 24
Peak memory	202604 kb
Host	smart-1c8d1d0b-856c-4c68-b477-c15df76dfa49
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686581418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.686581418
Directory	/workspace/12.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.148860328
Short name	T6
Test name
Test status
Simulation time	74912039 ps
CPU time	0.92 seconds
Started	Jan 10 01:00:50 PM PST 24
Finished	Jan 10 01:02:02 PM PST 24
Peak memory	202904 kb
Host	smart-05095582-6692-4d67-abb6-9a3da6584926
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148860328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_ou tstanding.148860328
Directory	/workspace/12.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_tl_errors.2787584313
Short name	T23
Test name
Test status
Simulation time	134926846 ps
CPU time	1.02 seconds
Started	Jan 10 01:00:50 PM PST 24
Finished	Jan 10 01:02:10 PM PST 24
Peak memory	202800 kb
Host	smart-4a267ed1-0b2e-4623-bb6b-8237f72ed334
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787584313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.2787584313
Directory	/workspace/12.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3566347974
Short name	T110
Test name
Test status
Simulation time	50511504 ps
CPU time	1.17 seconds
Started	Jan 10 01:00:50 PM PST 24
Finished	Jan 10 01:02:03 PM PST 24
Peak memory	202860 kb
Host	smart-6385ba85-e7e4-40b7-b552-8be438e507b3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566347974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.3566347974
Directory	/workspace/12.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.726104731
Short name	T60
Test name
Test status
Simulation time	59727205 ps
CPU time	0.92 seconds
Started	Jan 10 01:01:21 PM PST 24
Finished	Jan 10 01:02:47 PM PST 24
Peak memory	202808 kb
Host	smart-9f9acba9-a369-487d-8706-e03f0ed63d01
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726104731 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.726104731
Directory	/workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_intr_test.1733285875
Short name	T10
Test name
Test status
Simulation time	20105078 ps
CPU time	0.63 seconds
Started	Jan 10 01:01:22 PM PST 24
Finished	Jan 10 01:02:55 PM PST 24
Peak memory	202740 kb
Host	smart-25a5c456-f9f5-49c2-a672-1eb51b04d0c7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733285875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1733285875
Directory	/workspace/13.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1922620013
Short name	T87
Test name
Test status
Simulation time	63485338 ps
CPU time	0.74 seconds
Started	Jan 10 01:01:00 PM PST 24
Finished	Jan 10 01:02:20 PM PST 24
Peak memory	202776 kb
Host	smart-4e0e80c1-f4eb-408f-a314-57dde0040f26
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922620013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o utstanding.1922620013
Directory	/workspace/13.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_tl_errors.2106547277
Short name	T128
Test name
Test status
Simulation time	158047788 ps
CPU time	2.22 seconds
Started	Jan 10 01:01:11 PM PST 24
Finished	Jan 10 01:02:50 PM PST 24
Peak memory	202944 kb
Host	smart-9741eda5-1e93-4290-9711-244dba8521fe
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106547277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2106547277
Directory	/workspace/13.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.934608743
Short name	T18
Test name
Test status
Simulation time	227246446 ps
CPU time	1.14 seconds
Started	Jan 10 01:00:49 PM PST 24
Finished	Jan 10 01:01:59 PM PST 24
Peak memory	202968 kb
Host	smart-7cbcc0a2-efb9-4cb2-91ce-3b803ee2499c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934608743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.934608743
Directory	/workspace/13.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_csr_rw.1441778657
Short name	T153
Test name
Test status
Simulation time	52768404 ps
CPU time	0.64 seconds
Started	Jan 10 01:01:06 PM PST 24
Finished	Jan 10 01:02:26 PM PST 24
Peak memory	201780 kb
Host	smart-ed862424-e0d6-439e-b7c7-6ccd5d398466
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441778657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.1441778657
Directory	/workspace/14.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_intr_test.4196969138
Short name	T132
Test name
Test status
Simulation time	22075835 ps
CPU time	0.65 seconds
Started	Jan 10 01:01:12 PM PST 24
Finished	Jan 10 01:02:35 PM PST 24
Peak memory	202588 kb
Host	smart-2a4d9b09-4c00-425c-b263-2f06c49f97d1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196969138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.4196969138
Directory	/workspace/14.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.601937869
Short name	T33
Test name
Test status
Simulation time	18434140 ps
CPU time	0.76 seconds
Started	Jan 10 01:01:22 PM PST 24
Finished	Jan 10 01:02:49 PM PST 24
Peak memory	202692 kb
Host	smart-4003c5d6-1f41-4f4c-989c-3ca3c6d2dfc8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601937869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_ou tstanding.601937869
Directory	/workspace/14.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2343155468
Short name	T86
Test name
Test status
Simulation time	69846046 ps
CPU time	0.79 seconds
Started	Jan 10 01:01:21 PM PST 24
Finished	Jan 10 01:02:46 PM PST 24
Peak memory	202760 kb
Host	smart-4aa7112c-96bd-4b4d-b6e2-cc48fa8a4631
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343155468 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.2343155468
Directory	/workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_intr_test.1894183747
Short name	T65
Test name
Test status
Simulation time	30060085 ps
CPU time	0.65 seconds
Started	Jan 10 01:01:24 PM PST 24
Finished	Jan 10 01:02:50 PM PST 24
Peak memory	202756 kb
Host	smart-6d2f4bb9-b513-4102-995d-5c88d1ff41ab
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894183747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1894183747
Directory	/workspace/15.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1440916738
Short name	T63
Test name
Test status
Simulation time	169928133 ps
CPU time	0.98 seconds
Started	Jan 10 01:00:58 PM PST 24
Finished	Jan 10 01:02:49 PM PST 24
Peak memory	202884 kb
Host	smart-1c1b6c46-cdf7-4807-b091-149d239f87d6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440916738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o utstanding.1440916738
Directory	/workspace/15.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_tl_errors.1539316643
Short name	T93
Test name
Test status
Simulation time	123126154 ps
CPU time	1.28 seconds
Started	Jan 10 01:01:41 PM PST 24
Finished	Jan 10 01:03:16 PM PST 24
Peak memory	202924 kb
Host	smart-8a788b68-29d0-4864-a306-d44f9ef17d7c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539316643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.1539316643
Directory	/workspace/15.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1297953885
Short name	T100
Test name
Test status
Simulation time	26140772 ps
CPU time	0.86 seconds
Started	Jan 10 01:01:14 PM PST 24
Finished	Jan 10 01:02:45 PM PST 24
Peak memory	202764 kb
Host	smart-93eb1bd4-313e-4bdd-b974-aa230a2650a3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297953885 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.1297953885
Directory	/workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_csr_rw.1946692922
Short name	T37
Test name
Test status
Simulation time	27844820 ps
CPU time	0.63 seconds
Started	Jan 10 01:00:49 PM PST 24
Finished	Jan 10 01:02:12 PM PST 24
Peak memory	202768 kb
Host	smart-cb6d1609-458c-42c7-9239-8face28a0049
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946692922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1946692922
Directory	/workspace/16.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3309061591
Short name	T44
Test name
Test status
Simulation time	43893585 ps
CPU time	1 seconds
Started	Jan 10 01:01:24 PM PST 24
Finished	Jan 10 01:02:54 PM PST 24
Peak memory	202928 kb
Host	smart-ec4a49a2-9c80-4a06-9db2-bdfd84708d19
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309061591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o utstanding.3309061591
Directory	/workspace/16.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_tl_errors.2344394370
Short name	T99
Test name
Test status
Simulation time	217049249 ps
CPU time	2.06 seconds
Started	Jan 10 01:01:14 PM PST 24
Finished	Jan 10 01:02:42 PM PST 24
Peak memory	202968 kb
Host	smart-c4d7a5a1-346a-473c-bedc-86bedd09107a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344394370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.2344394370
Directory	/workspace/16.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1299435116
Short name	T54
Test name
Test status
Simulation time	269373190 ps
CPU time	1.63 seconds
Started	Jan 10 01:00:53 PM PST 24
Finished	Jan 10 01:02:26 PM PST 24
Peak memory	202952 kb
Host	smart-07a40f24-faf6-4016-9bdf-16d987166aee
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299435116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.1299435116
Directory	/workspace/16.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2253780975
Short name	T88
Test name
Test status
Simulation time	19182126 ps
CPU time	0.69 seconds
Started	Jan 10 01:01:06 PM PST 24
Finished	Jan 10 01:02:27 PM PST 24
Peak memory	202688 kb
Host	smart-57b95c49-34fc-4d59-b0e4-c4882a0789c0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253780975 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.2253780975
Directory	/workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_csr_rw.2398933873
Short name	T7
Test name
Test status
Simulation time	33488641 ps
CPU time	0.65 seconds
Started	Jan 10 01:01:10 PM PST 24
Finished	Jan 10 01:02:53 PM PST 24
Peak memory	201952 kb
Host	smart-506cab60-447d-4279-8741-7191a12d5a72
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398933873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.2398933873
Directory	/workspace/17.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_intr_test.3747715890
Short name	T3
Test name
Test status
Simulation time	17681304 ps
CPU time	0.68 seconds
Started	Jan 10 01:01:05 PM PST 24
Finished	Jan 10 01:02:21 PM PST 24
Peak memory	202756 kb
Host	smart-447c5a9b-ef1b-444d-9ae5-f7a5af41997b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747715890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.3747715890
Directory	/workspace/17.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_tl_errors.761082543
Short name	T125
Test name
Test status
Simulation time	167366285 ps
CPU time	2.37 seconds
Started	Jan 10 01:01:22 PM PST 24
Finished	Jan 10 01:02:53 PM PST 24
Peak memory	203020 kb
Host	smart-89a80a26-152d-47d2-8da6-8846419129ff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761082543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.761082543
Directory	/workspace/17.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.84855885
Short name	T51
Test name
Test status
Simulation time	1830437687 ps
CPU time	1.9 seconds
Started	Jan 10 01:01:15 PM PST 24
Finished	Jan 10 01:02:47 PM PST 24
Peak memory	202796 kb
Host	smart-8e75ddaf-0d22-4608-94d6-ee826fc1f7d8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84855885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.84855885
Directory	/workspace/17.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3720053275
Short name	T111
Test name
Test status
Simulation time	46916011 ps
CPU time	0.78 seconds
Started	Jan 10 01:01:03 PM PST 24
Finished	Jan 10 01:02:25 PM PST 24
Peak memory	202828 kb
Host	smart-bb5ab03d-8ef0-47b2-9be8-4c2e8cca6b1d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720053275 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.3720053275
Directory	/workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_csr_rw.4273564921
Short name	T94
Test name
Test status
Simulation time	25361055 ps
CPU time	0.66 seconds
Started	Jan 10 01:01:22 PM PST 24
Finished	Jan 10 01:02:49 PM PST 24
Peak memory	202072 kb
Host	smart-810b8b68-3080-4d94-b075-4169f8ce495d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273564921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.4273564921
Directory	/workspace/18.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_intr_test.2229821921
Short name	T139
Test name
Test status
Simulation time	16592923 ps
CPU time	0.64 seconds
Started	Jan 10 01:01:12 PM PST 24
Finished	Jan 10 01:02:37 PM PST 24
Peak memory	202656 kb
Host	smart-b0461e2f-e878-4727-a611-40231d6d14ad
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229821921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.2229821921
Directory	/workspace/18.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1646045822
Short name	T49
Test name
Test status
Simulation time	46326331 ps
CPU time	0.72 seconds
Started	Jan 10 01:01:37 PM PST 24
Finished	Jan 10 01:03:02 PM PST 24
Peak memory	202728 kb
Host	smart-1db80331-1ff8-445d-80f1-6a79ddae7fcb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646045822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o utstanding.1646045822
Directory	/workspace/18.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_tl_errors.3435992602
Short name	T27
Test name
Test status
Simulation time	182442479 ps
CPU time	2.49 seconds
Started	Jan 10 01:01:15 PM PST 24
Finished	Jan 10 01:02:41 PM PST 24
Peak memory	202928 kb
Host	smart-b7216372-80c9-4480-89f2-1d8ca67cf39f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435992602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.3435992602
Directory	/workspace/18.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2856096129
Short name	T26
Test name
Test status
Simulation time	254887048 ps
CPU time	1.24 seconds
Started	Jan 10 01:01:03 PM PST 24
Finished	Jan 10 01:02:52 PM PST 24
Peak memory	202928 kb
Host	smart-f22c7edf-a0b8-4e03-9608-cd5558599364
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856096129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2856096129
Directory	/workspace/18.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2399268976
Short name	T101
Test name
Test status
Simulation time	25553412 ps
CPU time	0.79 seconds
Started	Jan 10 01:01:08 PM PST 24
Finished	Jan 10 01:02:34 PM PST 24
Peak memory	202740 kb
Host	smart-d131d87c-57f3-4b66-be8c-25726d829e9f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399268976 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2399268976
Directory	/workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_intr_test.188043665
Short name	T74
Test name
Test status
Simulation time	44908059 ps
CPU time	0.64 seconds
Started	Jan 10 01:00:58 PM PST 24
Finished	Jan 10 01:02:15 PM PST 24
Peak memory	202676 kb
Host	smart-717e38aa-e085-4784-8c78-9d62fd07dc94
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188043665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.188043665
Directory	/workspace/19.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1078179432
Short name	T57
Test name
Test status
Simulation time	1402600883 ps
CPU time	1.28 seconds
Started	Jan 10 01:01:09 PM PST 24
Finished	Jan 10 01:03:00 PM PST 24
Peak memory	202908 kb
Host	smart-bc7f97fb-b243-4339-b1a8-0d783d62679b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078179432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.1078179432
Directory	/workspace/19.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.31022944
Short name	T116
Test name
Test status
Simulation time	111668852 ps
CPU time	0.93 seconds
Started	Jan 10 01:00:35 PM PST 24
Finished	Jan 10 01:02:15 PM PST 24
Peak memory	202756 kb
Host	smart-5c0d1ad3-a8f1-4f7a-aba5-208285d348a8
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31022944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.31022944
Directory	/workspace/2.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1011426715
Short name	T108
Test name
Test status
Simulation time	616332998 ps
CPU time	4.03 seconds
Started	Jan 10 01:00:36 PM PST 24
Finished	Jan 10 01:02:03 PM PST 24
Peak memory	202868 kb
Host	smart-dc0d0f5a-fec3-403c-9651-240e0c23413c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011426715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.1011426715
Directory	/workspace/2.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2096857777
Short name	T149
Test name
Test status
Simulation time	47241270 ps
CPU time	0.91 seconds
Started	Jan 10 01:01:10 PM PST 24
Finished	Jan 10 01:02:38 PM PST 24
Peak memory	202792 kb
Host	smart-478089ed-7ff7-4004-9f9c-ddb4c789e977
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096857777 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.2096857777
Directory	/workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_rw.2409803441
Short name	T31
Test name
Test status
Simulation time	60777342 ps
CPU time	0.7 seconds
Started	Jan 10 01:00:36 PM PST 24
Finished	Jan 10 01:02:03 PM PST 24
Peak memory	202524 kb
Host	smart-9e781b47-ff8c-427e-8112-833586a70b44
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409803441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.2409803441
Directory	/workspace/2.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_intr_test.2106868729
Short name	T45
Test name
Test status
Simulation time	18517206 ps
CPU time	0.66 seconds
Started	Jan 10 01:00:27 PM PST 24
Finished	Jan 10 01:01:49 PM PST 24
Peak memory	202564 kb
Host	smart-919d379b-7a75-4131-8f01-26648c2bb4c6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106868729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.2106868729
Directory	/workspace/2.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1392596218
Short name	T67
Test name
Test status
Simulation time	55602116 ps
CPU time	1.04 seconds
Started	Jan 10 01:00:40 PM PST 24
Finished	Jan 10 01:02:03 PM PST 24
Peak memory	202760 kb
Host	smart-0578d510-75d7-40ff-af72-c2c906ce786c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392596218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou tstanding.1392596218
Directory	/workspace/2.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_tl_errors.777106164
Short name	T17
Test name
Test status
Simulation time	70069447 ps
CPU time	1.14 seconds
Started	Jan 10 01:00:46 PM PST 24
Finished	Jan 10 01:02:03 PM PST 24
Peak memory	203008 kb
Host	smart-29dbb0f7-37de-4fec-be06-30cadb4d039f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777106164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.777106164
Directory	/workspace/2.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1680229532
Short name	T58
Test name
Test status
Simulation time	78814302 ps
CPU time	1.26 seconds
Started	Jan 10 01:00:27 PM PST 24
Finished	Jan 10 01:01:52 PM PST 24
Peak memory	202928 kb
Host	smart-212e6cc7-2643-4dbe-a760-db61fda74fbf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680229532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.1680229532
Directory	/workspace/2.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.i2c_intr_test.1974591574
Short name	T144
Test name
Test status
Simulation time	43997101 ps
CPU time	0.63 seconds
Started	Jan 10 01:01:21 PM PST 24
Finished	Jan 10 01:02:47 PM PST 24
Peak memory	202740 kb
Host	smart-79b2685b-4f11-467f-93d1-d4fc789f8178
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974591574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.1974591574
Directory	/workspace/20.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.i2c_intr_test.4135167824
Short name	T152
Test name
Test status
Simulation time	14653046 ps
CPU time	0.67 seconds
Started	Jan 10 01:01:20 PM PST 24
Finished	Jan 10 01:02:47 PM PST 24
Peak memory	202688 kb
Host	smart-a99bc526-8577-4e9f-b9d8-e1441adcc943
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135167824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.4135167824
Directory	/workspace/21.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.i2c_intr_test.2227444533
Short name	T77
Test name
Test status
Simulation time	44318377 ps
CPU time	0.65 seconds
Started	Jan 10 01:01:24 PM PST 24
Finished	Jan 10 01:02:54 PM PST 24
Peak memory	202748 kb
Host	smart-fc36efbf-c22c-4165-aa93-55d28e79aa42
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227444533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.2227444533
Directory	/workspace/22.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.i2c_intr_test.3996947839
Short name	T66
Test name
Test status
Simulation time	31009902 ps
CPU time	0.63 seconds
Started	Jan 10 01:01:11 PM PST 24
Finished	Jan 10 01:02:35 PM PST 24
Peak memory	202584 kb
Host	smart-56959d4b-2201-49ec-8c97-10dc398ae2f9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996947839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.3996947839
Directory	/workspace/23.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.i2c_intr_test.1795740625
Short name	T78
Test name
Test status
Simulation time	16124284 ps
CPU time	0.62 seconds
Started	Jan 10 01:01:16 PM PST 24
Finished	Jan 10 01:02:45 PM PST 24
Peak memory	202640 kb
Host	smart-c45bc9c0-0b92-4412-93e5-b789085a268c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795740625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.1795740625
Directory	/workspace/24.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.i2c_intr_test.1854635195
Short name	T12
Test name
Test status
Simulation time	28416153 ps
CPU time	0.63 seconds
Started	Jan 10 01:01:09 PM PST 24
Finished	Jan 10 01:02:31 PM PST 24
Peak memory	202752 kb
Host	smart-247157c5-e002-4920-a328-3f50d2569786
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854635195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1854635195
Directory	/workspace/25.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.i2c_intr_test.3547173214
Short name	T113
Test name
Test status
Simulation time	25663912 ps
CPU time	0.65 seconds
Started	Jan 10 01:00:50 PM PST 24
Finished	Jan 10 01:02:14 PM PST 24
Peak memory	202660 kb
Host	smart-54cbc781-6978-44aa-b5ba-9cc58f71cded
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547173214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.3547173214
Directory	/workspace/26.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.i2c_intr_test.55795579
Short name	T79
Test name
Test status
Simulation time	15248378 ps
CPU time	0.6 seconds
Started	Jan 10 01:00:54 PM PST 24
Finished	Jan 10 01:02:04 PM PST 24
Peak memory	200804 kb
Host	smart-df16a5fb-dcd9-4ab9-b607-ca1b9c1388e4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55795579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.55795579
Directory	/workspace/27.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.799127472
Short name	T90
Test name
Test status
Simulation time	55091971 ps
CPU time	1.23 seconds
Started	Jan 10 01:00:46 PM PST 24
Finished	Jan 10 01:01:57 PM PST 24
Peak memory	203000 kb
Host	smart-cb9df4cb-8450-423d-8aef-56b5e0b9954a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799127472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.799127472
Directory	/workspace/3.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1276597881
Short name	T97
Test name
Test status
Simulation time	4070480402 ps
CPU time	4.22 seconds
Started	Jan 10 01:01:18 PM PST 24
Finished	Jan 10 01:02:53 PM PST 24
Peak memory	203072 kb
Host	smart-740d797e-b0d8-4fe0-acf7-dc32dd478235
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276597881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1276597881
Directory	/workspace/3.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.897506760
Short name	T70
Test name
Test status
Simulation time	32640381 ps
CPU time	0.67 seconds
Started	Jan 10 01:00:45 PM PST 24
Finished	Jan 10 01:02:30 PM PST 24
Peak memory	202628 kb
Host	smart-6ae315dd-3b00-43e6-88a2-0c7c9f6ff1b6
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897506760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.897506760
Directory	/workspace/3.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3405056694
Short name	T147
Test name
Test status
Simulation time	72122725 ps
CPU time	1.14 seconds
Started	Jan 10 01:00:46 PM PST 24
Finished	Jan 10 01:02:00 PM PST 24
Peak memory	202948 kb
Host	smart-7f727568-5fdc-44e5-bef9-18a81d2fcead
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405056694 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3405056694
Directory	/workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_rw.3061946568
Short name	T22
Test name
Test status
Simulation time	105738683 ps
CPU time	0.68 seconds
Started	Jan 10 01:00:36 PM PST 24
Finished	Jan 10 01:01:52 PM PST 24
Peak memory	202688 kb
Host	smart-7b91cedc-a539-49ba-8827-dd851ccf19d9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061946568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3061946568
Directory	/workspace/3.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_tl_errors.690569662
Short name	T89
Test name
Test status
Simulation time	46386100 ps
CPU time	2.13 seconds
Started	Jan 10 01:00:31 PM PST 24
Finished	Jan 10 01:01:53 PM PST 24
Peak memory	203052 kb
Host	smart-e1af9d60-df0a-42c6-9977-379d10266c3f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690569662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.690569662
Directory	/workspace/3.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2076331538
Short name	T142
Test name
Test status
Simulation time	328161927 ps
CPU time	1.2 seconds
Started	Jan 10 01:00:32 PM PST 24
Finished	Jan 10 01:02:02 PM PST 24
Peak memory	202864 kb
Host	smart-ecd24c5a-a5f4-4773-951a-a6df0a3d906e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076331538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.2076331538
Directory	/workspace/3.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/31.i2c_intr_test.1622269884
Short name	T124
Test name
Test status
Simulation time	18030205 ps
CPU time	0.63 seconds
Started	Jan 10 01:00:58 PM PST 24
Finished	Jan 10 01:02:15 PM PST 24
Peak memory	202652 kb
Host	smart-69a496a3-7639-4150-8d50-e69b2d919bc5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622269884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.1622269884
Directory	/workspace/31.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.i2c_intr_test.3262611029
Short name	T120
Test name
Test status
Simulation time	43221408 ps
CPU time	0.65 seconds
Started	Jan 10 01:01:35 PM PST 24
Finished	Jan 10 01:03:00 PM PST 24
Peak memory	202736 kb
Host	smart-e9e6f218-b93a-479a-bf0e-139bcec21b14
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262611029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.3262611029
Directory	/workspace/32.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.i2c_intr_test.1548382437
Short name	T130
Test name
Test status
Simulation time	39131786 ps
CPU time	0.62 seconds
Started	Jan 10 01:01:04 PM PST 24
Finished	Jan 10 01:02:22 PM PST 24
Peak memory	202540 kb
Host	smart-5b9860b9-02e7-40e0-98cb-0520cba6e144
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548382437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.1548382437
Directory	/workspace/33.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.i2c_intr_test.799843787
Short name	T48
Test name
Test status
Simulation time	46790737 ps
CPU time	0.65 seconds
Started	Jan 10 01:01:29 PM PST 24
Finished	Jan 10 01:02:59 PM PST 24
Peak memory	202764 kb
Host	smart-397b8f99-cd66-43fa-b9f5-de647e294e14
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799843787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.799843787
Directory	/workspace/34.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.i2c_intr_test.2748633037
Short name	T137
Test name
Test status
Simulation time	70002120 ps
CPU time	0.66 seconds
Started	Jan 10 01:01:02 PM PST 24
Finished	Jan 10 01:02:30 PM PST 24
Peak memory	202720 kb
Host	smart-1c46aeff-b0d1-4df2-b984-f27332f9750c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748633037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.2748633037
Directory	/workspace/35.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.i2c_intr_test.2273707582
Short name	T73
Test name
Test status
Simulation time	38137809 ps
CPU time	0.62 seconds
Started	Jan 10 01:01:08 PM PST 24
Finished	Jan 10 01:02:32 PM PST 24
Peak memory	202748 kb
Host	smart-7d4043c1-d856-4e33-b396-811e3717b386
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273707582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.2273707582
Directory	/workspace/36.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.i2c_intr_test.1131980662
Short name	T85
Test name
Test status
Simulation time	52707303 ps
CPU time	0.66 seconds
Started	Jan 10 01:01:39 PM PST 24
Finished	Jan 10 01:03:23 PM PST 24
Peak memory	202740 kb
Host	smart-157e3934-4929-4f68-8eff-7b555d83592c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131980662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1131980662
Directory	/workspace/37.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.i2c_intr_test.1520822509
Short name	T129
Test name
Test status
Simulation time	16626016 ps
CPU time	0.66 seconds
Started	Jan 10 01:01:17 PM PST 24
Finished	Jan 10 01:02:48 PM PST 24
Peak memory	202728 kb
Host	smart-1e028dc5-0040-48c1-b75f-4d33e7c334a2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520822509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1520822509
Directory	/workspace/39.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1952791327
Short name	T114
Test name
Test status
Simulation time	67954545 ps
CPU time	0.89 seconds
Started	Jan 10 01:01:19 PM PST 24
Finished	Jan 10 01:03:00 PM PST 24
Peak memory	201984 kb
Host	smart-8edece79-05a5-4f36-9843-03810550eb33
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952791327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1952791327
Directory	/workspace/4.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.458238463
Short name	T135
Test name
Test status
Simulation time	152943925 ps
CPU time	2.29 seconds
Started	Jan 10 01:01:17 PM PST 24
Finished	Jan 10 01:02:46 PM PST 24
Peak memory	202972 kb
Host	smart-68558f7d-7126-464f-b629-6174d0b1fe1c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458238463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.458238463
Directory	/workspace/4.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.692857366
Short name	T41
Test name
Test status
Simulation time	37359578 ps
CPU time	0.7 seconds
Started	Jan 10 01:00:36 PM PST 24
Finished	Jan 10 01:02:03 PM PST 24
Peak memory	202776 kb
Host	smart-3388f4c7-9763-491a-b6cf-52fef27279d9
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692857366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.692857366
Directory	/workspace/4.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3395951503
Short name	T42
Test name
Test status
Simulation time	33294792 ps
CPU time	0.89 seconds
Started	Jan 10 01:00:41 PM PST 24
Finished	Jan 10 01:02:14 PM PST 24
Peak memory	202684 kb
Host	smart-095f7600-acf0-46f6-99c7-444c1d6de239
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395951503 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.3395951503
Directory	/workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_rw.2698585885
Short name	T39
Test name
Test status
Simulation time	41769663 ps
CPU time	0.77 seconds
Started	Jan 10 01:00:45 PM PST 24
Finished	Jan 10 01:02:05 PM PST 24
Peak memory	202784 kb
Host	smart-8799fc37-640d-4228-b510-d48b8388de22
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698585885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.2698585885
Directory	/workspace/4.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_intr_test.1731534620
Short name	T141
Test name
Test status
Simulation time	21556193 ps
CPU time	0.62 seconds
Started	Jan 10 01:00:40 PM PST 24
Finished	Jan 10 01:01:59 PM PST 24
Peak memory	202736 kb
Host	smart-b9b907d8-915e-4baa-b269-19dcca0b9e5a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731534620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1731534620
Directory	/workspace/4.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1907470266
Short name	T131
Test name
Test status
Simulation time	37880208 ps
CPU time	0.89 seconds
Started	Jan 10 01:00:46 PM PST 24
Finished	Jan 10 01:01:57 PM PST 24
Peak memory	202760 kb
Host	smart-2a45020a-0192-442f-9048-4d61adbec49f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907470266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou tstanding.1907470266
Directory	/workspace/4.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_tl_errors.487661664
Short name	T138
Test name
Test status
Simulation time	121785432 ps
CPU time	1.58 seconds
Started	Jan 10 01:00:46 PM PST 24
Finished	Jan 10 01:02:05 PM PST 24
Peak memory	202996 kb
Host	smart-7f5aa146-4e8b-4076-967e-96fa0d324ced
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487661664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.487661664
Directory	/workspace/4.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.133215622
Short name	T43
Test name
Test status
Simulation time	120136876 ps
CPU time	1.82 seconds
Started	Jan 10 01:01:05 PM PST 24
Finished	Jan 10 01:02:30 PM PST 24
Peak memory	202924 kb
Host	smart-1bf5750b-194e-4270-8dac-20c04f64570b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133215622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.133215622
Directory	/workspace/4.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/41.i2c_intr_test.26738183
Short name	T83
Test name
Test status
Simulation time	86707329 ps
CPU time	0.64 seconds
Started	Jan 10 01:01:13 PM PST 24
Finished	Jan 10 01:02:53 PM PST 24
Peak memory	202756 kb
Host	smart-b31da999-464a-45a5-a567-2be76ea5e40f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26738183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.26738183
Directory	/workspace/41.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.i2c_intr_test.238748915
Short name	T103
Test name
Test status
Simulation time	15119644 ps
CPU time	0.65 seconds
Started	Jan 10 01:01:03 PM PST 24
Finished	Jan 10 01:02:25 PM PST 24
Peak memory	202660 kb
Host	smart-7c529ff1-9a3e-4916-88ea-a748ee857c48
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238748915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.238748915
Directory	/workspace/42.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.i2c_intr_test.560740758
Short name	T115
Test name
Test status
Simulation time	17910447 ps
CPU time	0.72 seconds
Started	Jan 10 01:01:02 PM PST 24
Finished	Jan 10 01:02:30 PM PST 24
Peak memory	202652 kb
Host	smart-63405b4a-af33-4e41-ba9b-b9e4d1bed511
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560740758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.560740758
Directory	/workspace/43.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.i2c_intr_test.1422052861
Short name	T121
Test name
Test status
Simulation time	62563627 ps
CPU time	0.61 seconds
Started	Jan 10 01:01:19 PM PST 24
Finished	Jan 10 01:02:53 PM PST 24
Peak memory	202740 kb
Host	smart-10077beb-97df-4435-af33-ab97392451f8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422052861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1422052861
Directory	/workspace/44.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.i2c_intr_test.3891589554
Short name	T64
Test name
Test status
Simulation time	49544792 ps
CPU time	0.64 seconds
Started	Jan 10 01:01:12 PM PST 24
Finished	Jan 10 01:02:42 PM PST 24
Peak memory	202744 kb
Host	smart-ca51b57d-d52c-47f7-a4d1-7b87d2808103
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891589554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.3891589554
Directory	/workspace/45.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.i2c_intr_test.11767257
Short name	T1
Test name
Test status
Simulation time	17981652 ps
CPU time	0.64 seconds
Started	Jan 10 01:01:15 PM PST 24
Finished	Jan 10 01:02:45 PM PST 24
Peak memory	202740 kb
Host	smart-23ed517f-90d5-446c-b4b5-c28bea2f7048
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11767257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.11767257
Directory	/workspace/46.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.i2c_intr_test.4242556219
Short name	T76
Test name
Test status
Simulation time	62573094 ps
CPU time	0.67 seconds
Started	Jan 10 01:01:03 PM PST 24
Finished	Jan 10 01:02:25 PM PST 24
Peak memory	202736 kb
Host	smart-2c509c48-78c4-4b09-a956-8eb5d88701a3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242556219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.4242556219
Directory	/workspace/47.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.i2c_intr_test.500173912
Short name	T105
Test name
Test status
Simulation time	21137108 ps
CPU time	0.75 seconds
Started	Jan 10 01:01:08 PM PST 24
Finished	Jan 10 01:02:34 PM PST 24
Peak memory	202728 kb
Host	smart-5f5360bd-e4c5-4d48-87fe-bd1977b1b6ff
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500173912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.500173912
Directory	/workspace/48.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.888796400
Short name	T150
Test name
Test status
Simulation time	31352329 ps
CPU time	1.28 seconds
Started	Jan 10 01:00:47 PM PST 24
Finished	Jan 10 01:01:57 PM PST 24
Peak memory	202984 kb
Host	smart-f7c00d2b-355d-445f-9cc9-96d1e4e60cd2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888796400 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.888796400
Directory	/workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_csr_rw.3970616015
Short name	T104
Test name
Test status
Simulation time	43824336 ps
CPU time	0.65 seconds
Started	Jan 10 01:01:11 PM PST 24
Finished	Jan 10 01:02:48 PM PST 24
Peak memory	202744 kb
Host	smart-bc5d5e60-0d2e-43bc-b665-e63c40c8ad3d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970616015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3970616015
Directory	/workspace/5.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_intr_test.344516590
Short name	T112
Test name
Test status
Simulation time	52904350 ps
CPU time	0.64 seconds
Started	Jan 10 01:00:40 PM PST 24
Finished	Jan 10 01:01:58 PM PST 24
Peak memory	202740 kb
Host	smart-8b016fb6-a275-40c9-9706-537d795639b9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344516590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.344516590
Directory	/workspace/5.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1954436682
Short name	T91
Test name
Test status
Simulation time	56041797 ps
CPU time	0.74 seconds
Started	Jan 10 01:01:08 PM PST 24
Finished	Jan 10 01:02:42 PM PST 24
Peak memory	202716 kb
Host	smart-196438ed-d343-4e53-b42e-bad3e93412ec
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954436682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou tstanding.1954436682
Directory	/workspace/5.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_tl_errors.1022081610
Short name	T16
Test name
Test status
Simulation time	69268753 ps
CPU time	1.6 seconds
Started	Jan 10 01:01:12 PM PST 24
Finished	Jan 10 01:02:42 PM PST 24
Peak memory	202892 kb
Host	smart-33980324-eda4-4566-b365-9b96b1073d5e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022081610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.1022081610
Directory	/workspace/5.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1868714603
Short name	T25
Test name
Test status
Simulation time	40522849 ps
CPU time	0.78 seconds
Started	Jan 10 01:01:18 PM PST 24
Finished	Jan 10 01:02:44 PM PST 24
Peak memory	202808 kb
Host	smart-1974f475-fcae-4240-9cfd-cbd3fde73b8a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868714603 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.1868714603
Directory	/workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_csr_rw.701836372
Short name	T134
Test name
Test status
Simulation time	48823950 ps
CPU time	0.64 seconds
Started	Jan 10 01:01:17 PM PST 24
Finished	Jan 10 01:02:48 PM PST 24
Peak memory	202084 kb
Host	smart-53671cad-69c9-4bac-89bb-7fe33a335341
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701836372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.701836372
Directory	/workspace/6.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3092366596
Short name	T5
Test name
Test status
Simulation time	81454130 ps
CPU time	1.02 seconds
Started	Jan 10 01:01:16 PM PST 24
Finished	Jan 10 01:02:46 PM PST 24
Peak memory	202808 kb
Host	smart-4ddf4191-b445-486a-b717-baa11db8bc0f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092366596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou tstanding.3092366596
Directory	/workspace/6.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_tl_errors.1377630135
Short name	T8
Test name
Test status
Simulation time	54940996 ps
CPU time	1.55 seconds
Started	Jan 10 01:01:10 PM PST 24
Finished	Jan 10 01:02:54 PM PST 24
Peak memory	202984 kb
Host	smart-255fb24d-5aef-484c-b1bf-59560d1c1fb0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377630135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.1377630135
Directory	/workspace/6.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2848808391
Short name	T98
Test name
Test status
Simulation time	115646491 ps
CPU time	1.85 seconds
Started	Jan 10 01:01:18 PM PST 24
Finished	Jan 10 01:02:50 PM PST 24
Peak memory	202916 kb
Host	smart-08b0a2fe-a890-4678-af0d-63ed18117450
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848808391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.2848808391
Directory	/workspace/6.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.460206930
Short name	T59
Test name
Test status
Simulation time	22764960 ps
CPU time	0.87 seconds
Started	Jan 10 01:00:51 PM PST 24
Finished	Jan 10 01:02:10 PM PST 24
Peak memory	202748 kb
Host	smart-3e602e87-37ca-44b5-bdc8-ddcf974f3d14
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460206930 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.460206930
Directory	/workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_csr_rw.2530845651
Short name	T127
Test name
Test status
Simulation time	57638562 ps
CPU time	0.71 seconds
Started	Jan 10 01:00:48 PM PST 24
Finished	Jan 10 01:02:14 PM PST 24
Peak memory	202908 kb
Host	smart-101771b6-eb62-4f03-ab57-ad4dfc94d506
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530845651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.2530845651
Directory	/workspace/7.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_intr_test.3282064260
Short name	T140
Test name
Test status
Simulation time	16171098 ps
CPU time	0.59 seconds
Started	Jan 10 01:01:18 PM PST 24
Finished	Jan 10 01:02:49 PM PST 24
Peak memory	200800 kb
Host	smart-eb00ef57-8875-496a-8603-eddfba040168
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282064260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.3282064260
Directory	/workspace/7.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3275006957
Short name	T72
Test name
Test status
Simulation time	144000700 ps
CPU time	1.67 seconds
Started	Jan 10 01:01:12 PM PST 24
Finished	Jan 10 01:02:37 PM PST 24
Peak memory	202892 kb
Host	smart-c41bf9f1-45e9-4d7d-9ecd-063366271ed4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275006957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.3275006957
Directory	/workspace/7.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1714271906
Short name	T47
Test name
Test status
Simulation time	41453132 ps
CPU time	1.06 seconds
Started	Jan 10 01:00:51 PM PST 24
Finished	Jan 10 01:02:36 PM PST 24
Peak memory	203004 kb
Host	smart-ad121a27-b892-4883-a26e-11f7145f7dca
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714271906 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1714271906
Directory	/workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_csr_rw.375075150
Short name	T30
Test name
Test status
Simulation time	36148600 ps
CPU time	0.71 seconds
Started	Jan 10 01:01:12 PM PST 24
Finished	Jan 10 01:02:42 PM PST 24
Peak memory	202688 kb
Host	smart-ad0eb598-6b79-404d-bc8a-a575876b5686
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375075150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.375075150
Directory	/workspace/8.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_intr_test.1411576349
Short name	T109
Test name
Test status
Simulation time	59385590 ps
CPU time	0.66 seconds
Started	Jan 10 01:00:50 PM PST 24
Finished	Jan 10 01:02:10 PM PST 24
Peak memory	202736 kb
Host	smart-1109706e-4244-40fa-9fb2-f77713d6e253
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411576349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1411576349
Directory	/workspace/8.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_tl_errors.2558048727
Short name	T154
Test name
Test status
Simulation time	541653328 ps
CPU time	2.43 seconds
Started	Jan 10 01:00:49 PM PST 24
Finished	Jan 10 01:02:00 PM PST 24
Peak memory	202860 kb
Host	smart-b056676a-9e60-4eaa-976f-0e937ba7bbaa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558048727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.2558048727
Directory	/workspace/8.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2965175712
Short name	T4
Test name
Test status
Simulation time	176053773 ps
CPU time	1.14 seconds
Started	Jan 10 01:01:12 PM PST 24
Finished	Jan 10 01:02:43 PM PST 24
Peak memory	202828 kb
Host	smart-1600aace-7b90-4286-883c-007873cf1bd6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965175712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.2965175712
Directory	/workspace/8.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1172094533
Short name	T19
Test name
Test status
Simulation time	61952574 ps
CPU time	1.51 seconds
Started	Jan 10 01:00:49 PM PST 24
Finished	Jan 10 01:01:59 PM PST 24
Peak memory	203012 kb
Host	smart-a59bc0f6-2845-4ef5-9f05-840003efeae3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172094533 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.1172094533
Directory	/workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_csr_rw.1940810477
Short name	T21
Test name
Test status
Simulation time	75545305 ps
CPU time	0.69 seconds
Started	Jan 10 01:01:12 PM PST 24
Finished	Jan 10 01:02:36 PM PST 24
Peak memory	202724 kb
Host	smart-bae52d80-1ddf-45b0-9af9-43f12b82a972
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940810477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1940810477
Directory	/workspace/9.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_intr_test.976282005
Short name	T82
Test name
Test status
Simulation time	40230607 ps
CPU time	0.61 seconds
Started	Jan 10 01:00:50 PM PST 24
Finished	Jan 10 01:02:14 PM PST 24
Peak memory	202756 kb
Host	smart-b1f7f6b5-97bc-4dab-8f75-c53c28856463
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976282005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.976282005
Directory	/workspace/9.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3064334989
Short name	T123
Test name
Test status
Simulation time	55643987 ps
CPU time	0.76 seconds
Started	Jan 10 01:01:17 PM PST 24
Finished	Jan 10 01:02:48 PM PST 24
Peak memory	202624 kb
Host	smart-0b798b8e-2c62-4ab3-938f-d53f8ad03b5d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064334989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou tstanding.3064334989
Directory	/workspace/9.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3130327592
Short name	T146
Test name
Test status
Simulation time	61012650 ps
CPU time	1.51 seconds
Started	Jan 10 01:01:16 PM PST 24
Finished	Jan 10 01:02:58 PM PST 24
Peak memory	203056 kb
Host	smart-53c22839-73f3-43c3-932a-85a200126d81
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130327592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.3130327592
Directory	/workspace/9.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.170924464
Short name	T95
Test name
Test status
Simulation time	124434480 ps
CPU time	1.21 seconds
Started	Jan 10 01:00:50 PM PST 24
Finished	Jan 10 01:02:03 PM PST 24
Peak memory	202916 kb
Host	smart-1bc3d6f4-2a25-4bf9-93ac-1e78a29c1de0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170924464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.170924464
Directory	/workspace/9.i2c_tl_intg_err/latest