Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	316	1			T1	5		T3	5		T11	8
all_pins[1]	316	1			T1	5		T3	5		T11	8
all_pins[2]	316	1			T1	5		T3	5		T11	8
all_pins[3]	316	1			T1	5		T3	5		T11	8
all_pins[4]	316	1			T1	5		T3	5		T11	8
all_pins[5]	316	1			T1	5		T3	5		T11	8
all_pins[6]	316	1			T1	5		T3	5		T11	8
all_pins[7]	316	1			T1	5		T3	5		T11	8
all_pins[8]	316	1			T1	5		T3	5		T11	8
all_pins[9]	316	1			T1	5		T3	5		T11	8
all_pins[10]	316	1			T1	5		T3	5		T11	8
all_pins[11]	316	1			T1	5		T3	5		T11	8
all_pins[12]	316	1			T1	5		T3	5		T11	8
all_pins[13]	316	1			T1	5		T3	5		T11	8
all_pins[14]	316	1			T1	5		T3	5		T11	8

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	3886	1			T1	60		T3	58		T11	97
values[0x1]	854	1			T1	15		T3	17		T11	23
transitions[0x0=>0x1]	667	1			T1	10		T3	14		T11	20
transitions[0x1=>0x0]	676	1			T1	10		T3	14		T11	20

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	249	1			T1	3		T3	5		T11	8
all_pins[0]	values[0x1]	67	1			T1	2		T10	3		T64	1
all_pins[0]	transitions[0x0=>0x1]	44	1			T10	3		T73	4		T74	1
all_pins[0]	transitions[0x1=>0x0]	37	1			T3	3		T11	1		T10	2
all_pins[1]	values[0x0]	256	1			T1	3		T3	2		T11	7
all_pins[1]	values[0x1]	60	1			T1	2		T3	3		T11	1
all_pins[1]	transitions[0x0=>0x1]	43	1			T1	2		T3	1		T11	1
all_pins[1]	transitions[0x1=>0x0]	39	1			T11	2		T64	1		T65	2
all_pins[2]	values[0x0]	260	1			T1	5		T3	3		T11	6
all_pins[2]	values[0x1]	56	1			T3	2		T11	2		T64	1
all_pins[2]	transitions[0x0=>0x1]	49	1			T3	2		T11	2		T64	1
all_pins[2]	transitions[0x1=>0x0]	50	1			T3	1		T11	2		T64	2
all_pins[3]	values[0x0]	259	1			T1	5		T3	4		T11	6
all_pins[3]	values[0x1]	57	1			T3	1		T11	2		T64	2
all_pins[3]	transitions[0x0=>0x1]	49	1			T3	1		T11	2		T64	2
all_pins[3]	transitions[0x1=>0x0]	43	1			T1	1		T3	2		T11	1
all_pins[4]	values[0x0]	265	1			T1	4		T3	3		T11	7
all_pins[4]	values[0x1]	51	1			T1	1		T3	2		T11	1
all_pins[4]	transitions[0x0=>0x1]	41	1			T3	2		T11	1		T65	5
all_pins[4]	transitions[0x1=>0x0]	50	1			T1	1		T11	4		T10	5
all_pins[5]	values[0x0]	256	1			T1	3		T3	5		T11	4
all_pins[5]	values[0x1]	60	1			T1	2		T11	4		T10	5
all_pins[5]	transitions[0x0=>0x1]	49	1			T1	2		T11	3		T10	5
all_pins[5]	transitions[0x1=>0x0]	52	1			T3	1		T11	2		T10	1
all_pins[6]	values[0x0]	253	1			T1	5		T3	4		T11	5
all_pins[6]	values[0x1]	63	1			T3	1		T11	3		T10	1
all_pins[6]	transitions[0x0=>0x1]	49	1			T3	1		T11	2		T10	1
all_pins[6]	transitions[0x1=>0x0]	41	1			T3	2		T10	1		T65	2
all_pins[7]	values[0x0]	261	1			T1	5		T3	3		T11	7
all_pins[7]	values[0x1]	55	1			T3	2		T11	1		T10	1
all_pins[7]	transitions[0x0=>0x1]	45	1			T3	2		T65	2		T74	3
all_pins[7]	transitions[0x1=>0x0]	49	1			T1	3		T10	1		T12	2
all_pins[8]	values[0x0]	257	1			T1	2		T3	5		T11	7
all_pins[8]	values[0x1]	59	1			T1	3		T11	1		T10	2
all_pins[8]	transitions[0x0=>0x1]	45	1			T1	3		T11	1		T10	2
all_pins[8]	transitions[0x1=>0x0]	47	1			T3	1		T11	1		T10	1
all_pins[9]	values[0x0]	255	1			T1	5		T3	4		T11	7
all_pins[9]	values[0x1]	61	1			T3	1		T11	1		T10	1
all_pins[9]	transitions[0x0=>0x1]	47	1			T11	1		T10	1		T12	1
all_pins[9]	transitions[0x1=>0x0]	40	1			T3	1		T65	3		T74	2
all_pins[10]	values[0x0]	262	1			T1	5		T3	3		T11	8
all_pins[10]	values[0x1]	54	1			T3	2		T65	3		T74	2
all_pins[10]	transitions[0x0=>0x1]	47	1			T3	2		T65	3		T74	2
all_pins[10]	transitions[0x1=>0x0]	54	1			T1	3		T11	2		T10	1
all_pins[11]	values[0x0]	255	1			T1	2		T3	5		T11	6
all_pins[11]	values[0x1]	61	1			T1	3		T11	2		T10	1
all_pins[11]	transitions[0x0=>0x1]	46	1			T1	1		T11	2		T12	1
all_pins[11]	transitions[0x1=>0x0]	40	1			T3	1		T10	2		T12	1
all_pins[12]	values[0x0]	261	1			T1	3		T3	4		T11	8
all_pins[12]	values[0x1]	55	1			T1	2		T3	1		T10	3
all_pins[12]	transitions[0x0=>0x1]	44	1			T1	2		T3	1		T10	2
all_pins[12]	transitions[0x1=>0x0]	40	1			T3	2		T11	1		T10	1
all_pins[13]	values[0x0]	265	1			T1	5		T3	3		T11	7
all_pins[13]	values[0x1]	51	1			T3	2		T11	1		T10	2
all_pins[13]	transitions[0x0=>0x1]	43	1			T3	2		T11	1		T10	2
all_pins[13]	transitions[0x1=>0x0]	36	1			T11	4		T64	3		T65	1
all_pins[14]	values[0x0]	272	1			T1	5		T3	5		T11	4
all_pins[14]	values[0x1]	44	1			T11	4		T64	4		T65	1
all_pins[14]	transitions[0x0=>0x1]	26	1			T11	4		T64	2		T74	1
all_pins[14]	transitions[0x1=>0x0]	58	1			T1	2		T10	3		T65	1