Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.94	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	4	56	93.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	4	56	93.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7787444	1			T22	5		T23	1		T26	5
all_values[1]	7787444	1			T22	5		T23	1		T26	5
all_values[2]	7787444	1			T22	5		T23	1		T26	5
all_values[3]	7787444	1			T22	5		T23	1		T26	5
all_values[4]	7787444	1			T22	5		T23	1		T26	5
all_values[5]	7787444	1			T22	5		T23	1		T26	5
all_values[6]	7787444	1			T22	5		T23	1		T26	5
all_values[7]	7787444	1			T22	5		T23	1		T26	5
all_values[8]	7787444	1			T22	5		T23	1		T26	5
all_values[9]	7787444	1			T22	5		T23	1		T26	5
all_values[10]	7787444	1			T22	5		T23	1		T26	5
all_values[11]	7787444	1			T22	5		T23	1		T26	5
all_values[12]	7787444	1			T22	5		T23	1		T26	5
all_values[13]	7787444	1			T22	5		T23	1		T26	5
all_values[14]	7787444	1			T22	5		T23	1		T26	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111032779

1

T22

50

T23

15

T26

57

auto[1]

5778881

1

T22

25

T26

18

T27

47

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106996875

1

T22

12

T23

15

T26

12

auto[1]

9814785

1

T22

63

T26

63

T27

110

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	4	56	93.33	4

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	6320235	1			T22	1		T23	1		T27	3
all_values[0]	auto[0]	auto[1]	538450	1			T22	3		T26	2		T27	4
all_values[0]	auto[1]	auto[0]	786341	1			T3	1		T54	1		T10	1
all_values[0]	auto[1]	auto[1]	142418	1			T22	1		T26	3		T27	1
all_values[1]	auto[0]	auto[0]	6552187	1			T23	1		T26	5		T77	1
all_values[1]	auto[0]	auto[1]	540960	1			T22	3		T27	5		T70	1
all_values[1]	auto[1]	auto[0]	606687	1			T10	1		T37	120		T14	68
all_values[1]	auto[1]	auto[1]	87610	1			T22	2		T27	3		T70	4
all_values[2]	auto[0]	auto[0]	7208996	1			T22	2		T23	1		T26	1
all_values[2]	auto[0]	auto[1]	578258	1			T22	3		T26	4		T27	2
all_values[2]	auto[1]	auto[1]	190	1			T27	5		T70	1		T96	4
all_values[3]	auto[0]	auto[0]	7106583	1			T23	1		T77	1		T70	2
all_values[3]	auto[0]	auto[1]	680656	1			T22	3		T26	5		T27	5
all_values[3]	auto[1]	auto[1]	205	1			T22	2		T27	3		T96	5
all_values[4]	auto[0]	auto[0]	7106457	1			T22	1		T23	1		T26	1
all_values[4]	auto[0]	auto[1]	680637	1			T22	3		T26	1		T27	4
all_values[4]	auto[1]	auto[0]	104	1			T53	58		T45	45		T182	1
all_values[4]	auto[1]	auto[1]	246	1			T22	1		T26	3		T27	4
all_values[5]	auto[0]	auto[0]	7110414	1			T22	2		T23	1		T77	1
all_values[5]	auto[0]	auto[1]	674604	1			T22	3		T26	3		T27	3
all_values[5]	auto[1]	auto[0]	2199	1			T45	2199		-	-		-	-
all_values[5]	auto[1]	auto[1]	227	1			T26	2		T27	5		T70	4
all_values[6]	auto[0]	auto[0]	6275292	1			T23	1		T26	1		T27	2
all_values[6]	auto[0]	auto[1]	532894	1			T22	4		T26	4		T27	5
all_values[6]	auto[1]	auto[0]	831263	1			T1	1		T2	1		T3	1
all_values[6]	auto[1]	auto[1]	147995	1			T22	1		T27	1		T70	2
all_values[7]	auto[0]	auto[0]	6859353	1			T23	1		T77	1		T84	1
all_values[7]	auto[0]	auto[1]	578434	1			T22	5		T26	5		T27	4
all_values[7]	auto[1]	auto[0]	331846	1			T1	1		T2	1		T3	1
all_values[7]	auto[1]	auto[1]	17811	1			T27	4		T70	4		T96	2
all_values[8]	auto[0]	auto[0]	6099312	1			T23	1		T77	1		T84	1
all_values[8]	auto[0]	auto[1]	525276	1			T22	3		T26	4		T27	4
all_values[8]	auto[1]	auto[0]	1007244	1			T1	1		T2	1		T3	1
all_values[8]	auto[1]	auto[1]	155612	1			T22	2		T26	1		T27	4
all_values[9]	auto[0]	auto[0]	6166091	1			T23	1		T27	1		T77	1
all_values[9]	auto[0]	auto[1]	533542	1			T22	1		T26	4		T27	4
all_values[9]	auto[1]	auto[0]	940470	1			T1	1		T2	1		T3	1
all_values[9]	auto[1]	auto[1]	147341	1			T22	4		T26	1		T27	3
all_values[10]	auto[0]	auto[0]	7053586	1			T23	1		T26	1		T77	1
all_values[10]	auto[0]	auto[1]	610598	1			T22	2		T26	3		T27	4
all_values[10]	auto[1]	auto[0]	123079	1			T15	2691		T16	1780		T17	975
all_values[10]	auto[1]	auto[1]	181	1			T22	3		T26	1		T27	4
all_values[11]	auto[0]	auto[0]	6709918	1			T22	5		T23	1		T26	2
all_values[11]	auto[0]	auto[1]	628349	1			T26	1		T27	5		T70	1
all_values[11]	auto[1]	auto[0]	448969	1			T15	5552		T16	6557		T17	4241
all_values[11]	auto[1]	auto[1]	208	1			T26	2		T27	2		T70	3
all_values[12]	auto[0]	auto[0]	7106575	1			T23	1		T26	1		T27	2
all_values[12]	auto[0]	auto[1]	680687	1			T22	3		T26	2		T27	4
all_values[12]	auto[1]	auto[1]	182	1			T22	2		T26	2		T27	2
all_values[13]	auto[0]	auto[0]	7106585	1			T23	1		T77	1		T70	5
all_values[13]	auto[0]	auto[1]	680624	1			T22	1		T26	3		T27	5
all_values[13]	auto[1]	auto[0]	12	1			T173	1		T183	1		T184	1
all_values[13]	auto[1]	auto[1]	223	1			T22	4		T26	2		T27	3
all_values[14]	auto[0]	auto[0]	7137077	1			T22	1		T23	1		T77	1
all_values[14]	auto[0]	auto[1]	650149	1			T22	1		T26	4		T27	5
all_values[14]	auto[1]	auto[1]	218	1			T22	3		T26	1		T27	3