Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7787444	1			T22	5		T23	1		T26	5
all_pins[1]	7787444	1			T22	5		T23	1		T26	5
all_pins[2]	7787444	1			T22	5		T23	1		T26	5
all_pins[3]	7787444	1			T22	5		T23	1		T26	5
all_pins[4]	7787444	1			T22	5		T23	1		T26	5
all_pins[5]	7787444	1			T22	5		T23	1		T26	5
all_pins[6]	7787444	1			T22	5		T23	1		T26	5
all_pins[7]	7787444	1			T22	5		T23	1		T26	5
all_pins[8]	7787444	1			T22	5		T23	1		T26	5
all_pins[9]	7787444	1			T22	5		T23	1		T26	5
all_pins[10]	7787444	1			T22	5		T23	1		T26	5
all_pins[11]	7787444	1			T22	5		T23	1		T26	5
all_pins[12]	7787444	1			T22	5		T23	1		T26	5
all_pins[13]	7787444	1			T22	5		T23	1		T26	5
all_pins[14]	7787444	1			T22	5		T23	1		T26	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	110959907	1			T22	63		T23	15		T26	67
values[0x1]	5851753	1			T22	12		T26	8		T27	24
transitions[0x0=>0x1]	3973601	1			T22	10		T26	6		T27	16
transitions[0x1=>0x0]	3973613	1			T22	10		T26	7		T27	17

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	6858441	1			T22	4		T23	1		T26	5
all_pins[0]	values[0x1]	929003	1			T22	1		T27	1		T70	1
all_pins[0]	transitions[0x0=>0x1]	265743	1			T22	1		T27	1		T70	1
all_pins[0]	transitions[0x1=>0x0]	33658	1			T22	2		T27	3		T37	137
all_pins[1]	values[0x0]	7090526	1			T22	3		T23	1		T26	5
all_pins[1]	values[0x1]	696918	1			T22	2		T27	3		T10	1
all_pins[1]	transitions[0x0=>0x1]	696890	1			T22	2		T27	3		T10	1
all_pins[1]	transitions[0x1=>0x0]	71	1			T70	1		T96	2		T33	6
all_pins[2]	values[0x0]	7787345	1			T22	5		T23	1		T26	5
all_pins[2]	values[0x1]	99	1			T70	1		T96	2		T33	7
all_pins[2]	transitions[0x0=>0x1]	68	1			T70	1		T96	2		T33	3
all_pins[2]	transitions[0x1=>0x0]	73	1			T22	2		T27	2		T96	3
all_pins[3]	values[0x0]	7787340	1			T22	3		T23	1		T26	5
all_pins[3]	values[0x1]	104	1			T22	2		T27	2		T96	3
all_pins[3]	transitions[0x0=>0x1]	75	1			T22	2		T27	1		T96	1
all_pins[3]	transitions[0x1=>0x0]	197	1			T22	1		T26	2		T27	2
all_pins[4]	values[0x0]	7787218	1			T22	4		T23	1		T26	3
all_pins[4]	values[0x1]	226	1			T22	1		T26	2		T27	3
all_pins[4]	transitions[0x0=>0x1]	206	1			T22	1		T26	2		T27	3
all_pins[4]	transitions[0x1=>0x0]	2691	1			T26	2		T70	1		T96	3
all_pins[5]	values[0x0]	7784733	1			T22	5		T23	1		T26	3
all_pins[5]	values[0x1]	2711	1			T26	2		T70	1		T96	4
all_pins[5]	transitions[0x0=>0x1]	2450	1			T26	2		T70	1		T96	2
all_pins[5]	transitions[0x1=>0x0]	982796	1			T27	1		T95	3		T97	1
all_pins[6]	values[0x0]	6804387	1			T22	5		T23	1		T26	5
all_pins[6]	values[0x1]	983057	1			T27	1		T96	2		T95	3
all_pins[6]	transitions[0x0=>0x1]	958155	1			T27	1		T96	2		T95	2
all_pins[6]	transitions[0x1=>0x0]	364118	1			T27	3		T70	4		T37	2736
all_pins[7]	values[0x0]	7398424	1			T22	5		T23	1		T26	5
all_pins[7]	values[0x1]	389020	1			T27	3		T70	4		T95	1
all_pins[7]	transitions[0x0=>0x1]	318991	1			T27	1		T70	4		T95	1
all_pins[7]	transitions[0x1=>0x0]	1119032	1			T26	1		T96	1		T95	1
all_pins[8]	values[0x0]	6598383	1			T22	5		T23	1		T26	4
all_pins[8]	values[0x1]	1189061	1			T26	1		T27	2		T96	1
all_pins[8]	transitions[0x0=>0x1]	246240	1			T27	2		T96	1		T97	2
all_pins[8]	transitions[0x1=>0x0]	145908	1			T22	2		T27	2		T95	1
all_pins[9]	values[0x0]	6698715	1			T22	3		T23	1		T26	4
all_pins[9]	values[0x1]	1088729	1			T22	2		T26	1		T27	2
all_pins[9]	transitions[0x0=>0x1]	1033134	1			T26	1		T95	2		T1	1
all_pins[9]	transitions[0x1=>0x0]	67834	1			T26	1		T70	1		T96	2
all_pins[10]	values[0x0]	7664015	1			T22	3		T23	1		T26	4
all_pins[10]	values[0x1]	123429	1			T22	2		T26	1		T27	2
all_pins[10]	transitions[0x0=>0x1]	2376	1			T22	2		T26	1		T27	1
all_pins[10]	transitions[0x1=>0x0]	328014	1			T70	2		T95	2		T97	2
all_pins[11]	values[0x0]	7338377	1			T22	5		T23	1		T26	5
all_pins[11]	values[0x1]	449067	1			T27	1		T70	3		T95	2
all_pins[11]	transitions[0x0=>0x1]	449042	1			T27	1		T70	3		T95	1
all_pins[11]	transitions[0x1=>0x0]	67	1			T22	2		T96	1		T33	2
all_pins[12]	values[0x0]	7787352	1			T22	3		T23	1		T26	5
all_pins[12]	values[0x1]	92	1			T22	2		T96	1		T95	1
all_pins[12]	transitions[0x0=>0x1]	69	1			T22	2		T95	1		T97	1
all_pins[12]	transitions[0x1=>0x0]	101	1			T27	1		T96	1		T33	5
all_pins[13]	values[0x0]	7787320	1			T22	5		T23	1		T26	5
all_pins[13]	values[0x1]	124	1			T27	1		T96	2		T33	6
all_pins[13]	transitions[0x0=>0x1]	91	1			T96	2		T33	4		T141	1
all_pins[13]	transitions[0x1=>0x0]	80	1			T26	1		T27	2		T97	4
all_pins[14]	values[0x0]	7787331	1			T22	5		T23	1		T26	4
all_pins[14]	values[0x1]	113	1			T26	1		T27	3		T97	4
all_pins[14]	transitions[0x0=>0x1]	71	1			T27	2		T97	3		T33	1
all_pins[14]	transitions[0x1=>0x0]	928973	1			T22	1		T27	1		T70	1