Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	453	1			T22	4		T26	4		T27	7
all_values[1]	453	1			T22	4		T26	4		T27	7
all_values[2]	453	1			T22	4		T26	4		T27	7
all_values[3]	453	1			T22	4		T26	4		T27	7
all_values[4]	453	1			T22	4		T26	4		T27	7
all_values[5]	453	1			T22	4		T26	4		T27	7
all_values[6]	453	1			T22	4		T26	4		T27	7
all_values[7]	453	1			T22	4		T26	4		T27	7
all_values[8]	453	1			T22	4		T26	4		T27	7
all_values[9]	453	1			T22	4		T26	4		T27	7
all_values[10]	453	1			T22	4		T26	4		T27	7
all_values[11]	453	1			T22	4		T26	4		T27	7
all_values[12]	453	1			T22	4		T26	4		T27	7
all_values[13]	453	1			T22	4		T26	4		T27	7
all_values[14]	453	1			T22	4		T26	4		T27	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3527

1

T22

37

T26

40

T27

58

auto[1]

3268

1

T22

23

T26

20

T27

47

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1029

1

T22

11

T26

11

T27

10

auto[1]

5766

1

T22

49

T26

49

T27

95

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4041

1

T22

32

T26

37

T27

58

auto[1]

2754

1

T22

28

T26

23

T27

47

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	35	1			T22	1		T141	1		T200	3
all_values[0]	auto[0]	auto[0]	auto[1]	103	1			T26	2		T27	2		T70	1
all_values[0]	auto[0]	auto[1]	auto[0]	33	1			T27	3		T97	2		T33	1
all_values[0]	auto[0]	auto[1]	auto[1]	99	1			T22	1		T27	1		T96	2
all_values[0]	auto[1]	auto[0]	auto[1]	89	1			T26	2		T70	1		T95	2
all_values[0]	auto[1]	auto[1]	auto[1]	94	1			T22	2		T27	1		T70	2
all_values[1]	auto[0]	auto[0]	auto[0]	39	1			T26	2		T96	1		T95	1
all_values[1]	auto[0]	auto[0]	auto[1]	112	1			T27	3		T70	2		T96	3
all_values[1]	auto[0]	auto[1]	auto[0]	24	1			T26	2		T95	1		T33	1
all_values[1]	auto[0]	auto[1]	auto[1]	101	1			T22	2		T97	1		T33	5
all_values[1]	auto[1]	auto[0]	auto[1]	107	1			T22	1		T27	1		T70	2
all_values[1]	auto[1]	auto[1]	auto[1]	70	1			T22	1		T27	3		T95	1
all_values[2]	auto[0]	auto[0]	auto[0]	56	1			T22	1		T26	1		T97	2
all_values[2]	auto[0]	auto[0]	auto[1]	93	1			T22	1		T27	3		T95	2
all_values[2]	auto[0]	auto[1]	auto[0]	41	1			T22	1		T27	1		T33	1
all_values[2]	auto[0]	auto[1]	auto[1]	98	1			T26	2		T70	3		T96	3
all_values[2]	auto[1]	auto[0]	auto[1]	92	1			T26	1		T27	3		T96	3
all_values[2]	auto[1]	auto[1]	auto[1]	73	1			T22	1		T70	1		T96	1
all_values[3]	auto[0]	auto[0]	auto[0]	47	1			T70	1		T95	1		T142	1
all_values[3]	auto[0]	auto[0]	auto[1]	106	1			T96	1		T95	1		T33	2
all_values[3]	auto[0]	auto[1]	auto[0]	29	1			T70	1		T96	1		T51	1
all_values[3]	auto[0]	auto[1]	auto[1]	98	1			T22	2		T26	2		T27	4
all_values[3]	auto[1]	auto[0]	auto[1]	86	1			T22	1		T26	2		T27	2
all_values[3]	auto[1]	auto[1]	auto[1]	87	1			T22	1		T27	1		T70	1
all_values[4]	auto[0]	auto[0]	auto[0]	31	1			T22	1		T26	1		T95	2
all_values[4]	auto[0]	auto[0]	auto[1]	106	1			T22	1		T70	1		T96	1
all_values[4]	auto[0]	auto[1]	auto[0]	24	1			T70	1		T95	2		T97	1
all_values[4]	auto[0]	auto[1]	auto[1]	97	1			T26	2		T27	2		T96	2
all_values[4]	auto[1]	auto[0]	auto[1]	113	1			T27	2		T96	2		T33	3
all_values[4]	auto[1]	auto[1]	auto[1]	82	1			T22	2		T26	1		T27	3
all_values[5]	auto[0]	auto[0]	auto[0]	33	1			T22	2		T95	1		T142	1
all_values[5]	auto[0]	auto[0]	auto[1]	119	1			T22	1		T26	2		T27	3
all_values[5]	auto[0]	auto[1]	auto[0]	20	1			T95	1		T33	1		T147	2
all_values[5]	auto[0]	auto[1]	auto[1]	90	1			T26	1		T96	3		T95	1
all_values[5]	auto[1]	auto[0]	auto[1]	106	1			T22	1		T26	1		T27	4
all_values[5]	auto[1]	auto[1]	auto[1]	85	1			T70	1		T96	2		T95	1
all_values[6]	auto[0]	auto[0]	auto[0]	30	1			T26	1		T27	2		T95	1
all_values[6]	auto[0]	auto[0]	auto[1]	97	1			T22	1		T27	2		T70	2
all_values[6]	auto[0]	auto[1]	auto[0]	20	1			T201	2		T148	1		T202	1
all_values[6]	auto[0]	auto[1]	auto[1]	109	1			T26	1		T27	1		T96	2
all_values[6]	auto[1]	auto[0]	auto[1]	93	1			T22	3		T70	2		T96	2
all_values[6]	auto[1]	auto[1]	auto[1]	104	1			T26	2		T27	2		T96	1
all_values[7]	auto[0]	auto[0]	auto[0]	40	1			T96	4		T95	1		T97	1
all_values[7]	auto[0]	auto[0]	auto[1]	101	1			T22	1		T26	1		T27	2
all_values[7]	auto[0]	auto[1]	auto[0]	28	1			T96	1		T141	1		T203	1
all_values[7]	auto[0]	auto[1]	auto[1]	102	1			T22	1		T26	1		T27	2
all_values[7]	auto[1]	auto[0]	auto[1]	94	1			T22	1		T26	2		T27	2
all_values[7]	auto[1]	auto[1]	auto[1]	88	1			T22	1		T27	1		T70	2
all_values[8]	auto[0]	auto[0]	auto[0]	20	1			T142	2		T147	1		T148	1
all_values[8]	auto[0]	auto[0]	auto[1]	123	1			T22	1		T26	1		T27	3
all_values[8]	auto[0]	auto[1]	auto[0]	30	1			T96	1		T97	2		T51	1
all_values[8]	auto[0]	auto[1]	auto[1]	97	1			T26	1		T96	1		T95	3
all_values[8]	auto[1]	auto[0]	auto[1]	90	1			T22	1		T26	2		T27	2
all_values[8]	auto[1]	auto[1]	auto[1]	93	1			T22	2		T27	2		T96	2
all_values[9]	auto[0]	auto[0]	auto[0]	23	1			T27	1		T70	1		T142	1
all_values[9]	auto[0]	auto[0]	auto[1]	108	1			T22	1		T26	1		T27	2
all_values[9]	auto[0]	auto[1]	auto[0]	31	1			T70	3		T96	3		T201	2
all_values[9]	auto[0]	auto[1]	auto[1]	105	1			T22	1		T27	1		T96	3
all_values[9]	auto[1]	auto[0]	auto[1]	98	1			T22	1		T26	2		T27	1
all_values[9]	auto[1]	auto[1]	auto[1]	88	1			T22	1		T26	1		T27	2
all_values[10]	auto[0]	auto[0]	auto[0]	39	1			T26	1		T95	2		T203	1
all_values[10]	auto[0]	auto[0]	auto[1]	96	1			T22	1		T26	2		T27	2
all_values[10]	auto[0]	auto[1]	auto[0]	46	1			T70	2		T95	2		T201	2
all_values[10]	auto[0]	auto[1]	auto[1]	91	1			T27	1		T70	1		T33	6
all_values[10]	auto[1]	auto[0]	auto[1]	90	1			T22	1		T27	2		T96	4
all_values[10]	auto[1]	auto[1]	auto[1]	91	1			T22	2		T26	1		T27	2
all_values[11]	auto[0]	auto[0]	auto[0]	41	1			T22	3		T26	1		T95	1
all_values[11]	auto[0]	auto[0]	auto[1]	92	1			T26	1		T95	1		T33	4
all_values[11]	auto[0]	auto[1]	auto[0]	34	1			T22	1		T26	1		T27	1
all_values[11]	auto[0]	auto[1]	auto[1]	102	1			T27	3		T70	1		T96	4
all_values[11]	auto[1]	auto[0]	auto[1]	111	1			T26	1		T27	3		T96	1
all_values[11]	auto[1]	auto[1]	auto[1]	73	1			T70	2		T97	1		T33	3
all_values[12]	auto[0]	auto[0]	auto[0]	34	1			T26	1		T27	2		T96	1
all_values[12]	auto[0]	auto[0]	auto[1]	93	1			T22	1		T26	1		T27	2
all_values[12]	auto[0]	auto[1]	auto[0]	35	1			T97	1		T33	1		T201	1
all_values[12]	auto[0]	auto[1]	auto[1]	109	1			T22	1		T27	1		T96	3
all_values[12]	auto[1]	auto[0]	auto[1]	95	1			T22	2		T26	1		T27	2
all_values[12]	auto[1]	auto[1]	auto[1]	87	1			T26	1		T97	1		T33	4
all_values[13]	auto[0]	auto[0]	auto[0]	46	1			T70	1		T96	1		T95	3
all_values[13]	auto[0]	auto[0]	auto[1]	91	1			T22	3		T26	2		T27	4
all_values[13]	auto[0]	auto[1]	auto[0]	32	1			T70	3		T95	1		T33	4
all_values[13]	auto[0]	auto[1]	auto[1]	89	1			T27	1		T96	2		T97	1
all_values[13]	auto[1]	auto[0]	auto[1]	92	1			T22	1		T26	2		T27	1
all_values[13]	auto[1]	auto[1]	auto[1]	103	1			T27	1		T96	2		T97	2
all_values[14]	auto[0]	auto[0]	auto[0]	49	1			T22	1		T95	1		T97	1
all_values[14]	auto[0]	auto[0]	auto[1]	85	1			T22	1		T26	2		T70	1
all_values[14]	auto[0]	auto[1]	auto[0]	39	1			T96	1		T95	1		T33	2
all_values[14]	auto[0]	auto[1]	auto[1]	100	1			T26	1		T27	3		T70	2
all_values[14]	auto[1]	auto[0]	auto[1]	83	1			T22	2		T26	1		T70	1
all_values[14]	auto[1]	auto[1]	auto[1]	97	1			T27	4		T96	1		T95	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal