Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.94	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	4	56	93.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	4	56	93.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7776892	1			T21	5		T23	5		T24	5
all_values[1]	7776892	1			T21	5		T23	5		T24	5
all_values[2]	7776892	1			T21	5		T23	5		T24	5
all_values[3]	7776892	1			T21	5		T23	5		T24	5
all_values[4]	7776892	1			T21	5		T23	5		T24	5
all_values[5]	7776892	1			T21	5		T23	5		T24	5
all_values[6]	7776892	1			T21	5		T23	5		T24	5
all_values[7]	7776892	1			T21	5		T23	5		T24	5
all_values[8]	7776892	1			T21	5		T23	5		T24	5
all_values[9]	7776892	1			T21	5		T23	5		T24	5
all_values[10]	7776892	1			T21	5		T23	5		T24	5
all_values[11]	7776892	1			T21	5		T23	5		T24	5
all_values[12]	7776892	1			T21	5		T23	5		T24	5
all_values[13]	7776892	1			T21	5		T23	5		T24	5
all_values[14]	7776892	1			T21	5		T23	5		T24	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111167305

1

T21

59

T23

60

T24

56

auto[1]

5486075

1

T21

16

T23

15

T24

19

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108532068

1

T21

23

T23

22

T24

15

auto[1]

8121312

1

T21

52

T23

53

T24

60

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	4	56	93.33	4

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	6557072	1			T24	2		T66	2		T142	1
all_values[0]	auto[0]	auto[1]	408466	1			T21	5		T23	4		T24	1
all_values[0]	auto[1]	auto[0]	674239	1			T8	1		T9	25		T10	1
all_values[0]	auto[1]	auto[1]	137115	1			T23	1		T24	2		T25	3
all_values[1]	auto[0]	auto[0]	6692379	1			T21	1		T23	5		T166	2
all_values[1]	auto[0]	auto[1]	432020	1			T21	3		T24	4		T25	1
all_values[1]	auto[1]	auto[0]	560674	1			T9	29		T10	1		T37	105
all_values[1]	auto[1]	auto[1]	91819	1			T21	1		T24	1		T25	4
all_values[2]	auto[0]	auto[0]	7275681	1			T21	5		T25	1		T166	2
all_values[2]	auto[0]	auto[1]	500989	1			T23	4		T24	3		T25	1
all_values[2]	auto[1]	auto[1]	222	1			T23	1		T24	2		T25	3
all_values[3]	auto[0]	auto[0]	7227222	1			T24	2		T67	1		T167	5
all_values[3]	auto[0]	auto[1]	549431	1			T21	4		T23	3		T24	1
all_values[3]	auto[1]	auto[1]	239	1			T21	1		T23	2		T24	2
all_values[4]	auto[0]	auto[0]	7192464	1			T21	1		T23	5		T25	2
all_values[4]	auto[0]	auto[1]	584123	1			T21	3		T24	4		T25	1
all_values[4]	auto[1]	auto[0]	25	1			T44	25		-	-		-	-
all_values[4]	auto[1]	auto[1]	280	1			T21	1		T24	1		T25	2
all_values[5]	auto[0]	auto[0]	7281428	1			T21	1		T23	5		T24	1
all_values[5]	auto[0]	auto[1]	493995	1			T21	1		T24	4		T25	1
all_values[5]	auto[1]	auto[0]	1230	1			T44	1230		-	-		-	-
all_values[5]	auto[1]	auto[1]	239	1			T21	3		T25	4		T66	3
all_values[6]	auto[0]	auto[0]	6476970	1			T25	1		T66	2		T100	2
all_values[6]	auto[0]	auto[1]	437885	1			T21	4		T23	4		T24	3
all_values[6]	auto[1]	auto[0]	715516	1			T3	1		T8	1		T9	378
all_values[6]	auto[1]	auto[1]	146521	1			T21	1		T23	1		T24	2
all_values[7]	auto[0]	auto[0]	6898036	1			T21	2		T25	2		T66	2
all_values[7]	auto[0]	auto[1]	562221	1			T21	1		T23	3		T24	4
all_values[7]	auto[1]	auto[0]	298406	1			T3	1		T9	1311		T10	1
all_values[7]	auto[1]	auto[1]	18229	1			T21	2		T23	2		T24	1
all_values[8]	auto[0]	auto[0]	6345363	1			T24	2		T25	5		T66	3
all_values[8]	auto[0]	auto[1]	374879	1			T21	4		T23	5		T24	1
all_values[8]	auto[1]	auto[0]	930329	1			T3	1		T9	1887		T10	1
all_values[8]	auto[1]	auto[1]	126321	1			T21	1		T24	2		T66	1
all_values[9]	auto[0]	auto[0]	6293944	1			T21	2		T23	1		T24	1
all_values[9]	auto[0]	auto[1]	440026	1			T21	1		T23	1		T24	4
all_values[9]	auto[1]	auto[0]	898521	1			T1	1		T3	1		T9	51
all_values[9]	auto[1]	auto[1]	144401	1			T21	2		T23	3		T25	2
all_values[10]	auto[0]	auto[0]	7109808	1			T23	5		T25	1		T100	2
all_values[10]	auto[0]	auto[1]	500964	1			T21	2		T24	3		T25	3
all_values[10]	auto[1]	auto[0]	165916	1			T14	2409		T15	1489		T16	3700
all_values[10]	auto[1]	auto[1]	204	1			T21	3		T24	2		T25	1
all_values[11]	auto[0]	auto[0]	6632624	1			T25	1		T67	1		T100	5
all_values[11]	auto[0]	auto[1]	569270	1			T21	5		T23	4		T24	3
all_values[11]	auto[1]	auto[0]	574773	1			T14	5085		T15	5274		T16	6626
all_values[11]	auto[1]	auto[1]	225	1			T23	1		T24	2		T25	3
all_values[12]	auto[0]	auto[0]	7252545	1			T21	1		T23	1		T24	2
all_values[12]	auto[0]	auto[1]	524155	1			T21	3		T23	2		T24	2
all_values[12]	auto[1]	auto[1]	192	1			T21	1		T23	2		T24	1
all_values[13]	auto[0]	auto[0]	7201208	1			T21	5		T24	5		T25	5
all_values[13]	auto[0]	auto[1]	575472	1			T23	5		T66	3		T67	3
all_values[13]	auto[1]	auto[0]	4	1			T168	1		T169	1		T170	1
all_values[13]	auto[1]	auto[1]	208	1			T66	4		T67	2		T100	2
all_values[14]	auto[0]	auto[0]	7275691	1			T21	5		T66	2		T100	1
all_values[14]	auto[0]	auto[1]	500974	1			T23	3		T24	4		T25	4
all_values[14]	auto[1]	auto[1]	227	1			T23	2		T24	1		T25	1