Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.63 99.27 96.92 100.00 95.65 98.57 100.00 92.96


Total tests in report: 1632
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
55.57 55.57 49.51 49.51 48.13 48.13 59.47 59.47 95.65 95.65 50.05 50.05 81.77 81.77 4.41 4.41 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2280851883
77.19 21.62 88.43 38.92 71.89 23.76 67.11 7.65 95.65 0.00 82.00 31.94 96.78 15.01 38.45 34.03 /workspace/coverage/default/49.i2c_host_fifo_watermark.890391453
85.73 8.55 90.58 2.15 78.18 6.29 94.54 27.43 95.65 0.00 84.85 2.85 96.78 0.00 59.56 21.11 /workspace/coverage/cover_reg_top/33.i2c_intr_test.777539184
90.52 4.78 97.12 6.54 84.20 6.02 95.63 1.09 95.65 0.00 94.62 9.77 98.12 1.34 68.28 8.72 /workspace/coverage/default/34.i2c_target_stress_all.170169701
94.36 3.84 97.90 0.78 91.97 7.76 97.33 1.70 95.65 0.00 95.94 1.32 99.46 1.34 82.25 13.97 /workspace/coverage/default/27.i2c_host_stress_all_with_rand_reset.2777842252
95.03 0.67 97.95 0.05 92.77 0.80 98.54 1.21 95.65 0.00 96.05 0.11 99.46 0.00 84.77 2.52 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3644996229
95.52 0.49 98.63 0.68 93.57 0.80 98.54 0.00 95.65 0.00 97.15 1.10 99.46 0.00 85.61 0.84 /workspace/coverage/default/0.i2c_target_stress_all.2759167832
95.77 0.25 98.63 0.00 94.11 0.54 98.79 0.24 95.65 0.00 97.15 0.00 99.73 0.27 86.34 0.74 /workspace/coverage/cover_reg_top/23.i2c_intr_test.2975536072
96.01 0.23 98.88 0.24 94.65 0.54 98.79 0.00 95.65 0.00 97.69 0.55 99.73 0.00 86.66 0.32 /workspace/coverage/default/33.i2c_host_perf.412066404
96.23 0.22 98.88 0.00 94.78 0.13 99.03 0.24 95.65 0.00 97.91 0.22 99.73 0.00 87.61 0.95 /workspace/coverage/default/14.i2c_host_override.1098705528
96.41 0.18 98.88 0.00 94.98 0.20 99.03 0.00 95.65 0.00 97.91 0.00 99.73 0.00 88.66 1.05 /workspace/coverage/default/0.i2c_target_glitch.989269092
96.53 0.12 98.88 0.00 95.11 0.13 99.27 0.24 95.65 0.00 97.91 0.00 100.00 0.27 88.87 0.21 /workspace/coverage/default/0.i2c_sec_cm.394008303
96.64 0.12 98.88 0.00 95.45 0.33 99.76 0.49 95.65 0.00 97.91 0.00 100.00 0.00 88.87 0.00 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3543633347
96.76 0.11 99.22 0.34 95.58 0.13 99.76 0.00 95.65 0.00 98.24 0.33 100.00 0.00 88.87 0.00 /workspace/coverage/default/18.i2c_host_mode_toggle.1369463448
96.86 0.10 99.22 0.00 95.78 0.20 99.76 0.00 95.65 0.00 98.24 0.00 100.00 0.00 89.39 0.53 /workspace/coverage/default/13.i2c_host_stress_all.955067574
96.94 0.07 99.27 0.05 95.92 0.13 99.76 0.00 95.65 0.00 98.46 0.22 100.00 0.00 89.50 0.11 /workspace/coverage/default/5.i2c_target_bad_addr.1023613135
97.00 0.06 99.27 0.00 96.05 0.13 99.76 0.00 95.65 0.00 98.46 0.00 100.00 0.00 89.81 0.32 /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.4261727618
97.06 0.06 99.27 0.00 96.05 0.00 99.76 0.00 95.65 0.00 98.46 0.00 100.00 0.00 90.23 0.42 /workspace/coverage/default/40.i2c_host_stress_all.1575549545
97.11 0.05 99.27 0.00 96.18 0.13 100.00 0.24 95.65 0.00 98.46 0.00 100.00 0.00 90.23 0.00 /workspace/coverage/default/10.i2c_alert_test.3489649144
97.16 0.05 99.27 0.00 96.18 0.00 100.00 0.00 95.65 0.00 98.46 0.00 100.00 0.00 90.55 0.32 /workspace/coverage/default/13.i2c_target_stress_all.3793016242
97.20 0.05 99.27 0.00 96.18 0.00 100.00 0.00 95.65 0.00 98.46 0.00 100.00 0.00 90.86 0.32 /workspace/coverage/default/29.i2c_host_perf.3507182957
97.25 0.04 99.27 0.00 96.39 0.20 100.00 0.00 95.65 0.00 98.46 0.00 100.00 0.00 90.97 0.11 /workspace/coverage/default/31.i2c_host_fifo_overflow.1476545307
97.29 0.04 99.27 0.00 96.45 0.07 100.00 0.00 95.65 0.00 98.57 0.11 100.00 0.00 91.07 0.11 /workspace/coverage/default/28.i2c_target_stretch.1919438541
97.32 0.03 99.27 0.00 96.59 0.13 100.00 0.00 95.65 0.00 98.57 0.00 100.00 0.00 91.18 0.11 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.416170834
97.35 0.03 99.27 0.00 96.59 0.00 100.00 0.00 95.65 0.00 98.57 0.00 100.00 0.00 91.39 0.21 /workspace/coverage/default/1.i2c_host_override.1040498963
97.38 0.03 99.27 0.00 96.59 0.00 100.00 0.00 95.65 0.00 98.57 0.00 100.00 0.00 91.60 0.21 /workspace/coverage/default/23.i2c_host_rx_oversample.757641874
97.41 0.03 99.27 0.00 96.59 0.00 100.00 0.00 95.65 0.00 98.57 0.00 100.00 0.00 91.81 0.21 /workspace/coverage/default/24.i2c_target_hrst.4095183232
97.44 0.03 99.27 0.00 96.59 0.00 100.00 0.00 95.65 0.00 98.57 0.00 100.00 0.00 92.02 0.21 /workspace/coverage/default/30.i2c_host_stress_all.827428157
97.47 0.02 99.27 0.00 96.65 0.07 100.00 0.00 95.65 0.00 98.57 0.00 100.00 0.00 92.12 0.11 /workspace/coverage/default/10.i2c_target_fifo_reset_acq.2043048719
97.49 0.02 99.27 0.00 96.79 0.13 100.00 0.00 95.65 0.00 98.57 0.00 100.00 0.00 92.12 0.00 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.209933680
97.50 0.02 99.27 0.00 96.79 0.00 100.00 0.00 95.65 0.00 98.57 0.00 100.00 0.00 92.23 0.11 /workspace/coverage/default/0.i2c_host_fifo_reset_rx.288559220
97.52 0.02 99.27 0.00 96.79 0.00 100.00 0.00 95.65 0.00 98.57 0.00 100.00 0.00 92.33 0.11 /workspace/coverage/default/11.i2c_target_hrst.1107997282
97.53 0.02 99.27 0.00 96.79 0.00 100.00 0.00 95.65 0.00 98.57 0.00 100.00 0.00 92.44 0.11 /workspace/coverage/default/16.i2c_target_stress_all.82924734
97.55 0.02 99.27 0.00 96.79 0.00 100.00 0.00 95.65 0.00 98.57 0.00 100.00 0.00 92.54 0.11 /workspace/coverage/default/17.i2c_target_fifo_reset_acq.1396629108
97.56 0.02 99.27 0.00 96.79 0.00 100.00 0.00 95.65 0.00 98.57 0.00 100.00 0.00 92.65 0.11 /workspace/coverage/default/19.i2c_host_fifo_watermark.3091018606
97.58 0.02 99.27 0.00 96.79 0.00 100.00 0.00 95.65 0.00 98.57 0.00 100.00 0.00 92.75 0.11 /workspace/coverage/default/19.i2c_host_stress_all.1589211441
97.59 0.02 99.27 0.00 96.79 0.00 100.00 0.00 95.65 0.00 98.57 0.00 100.00 0.00 92.86 0.11 /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.1901217054
97.61 0.02 99.27 0.00 96.79 0.00 100.00 0.00 95.65 0.00 98.57 0.00 100.00 0.00 92.96 0.11 /workspace/coverage/default/32.i2c_host_stress_all.821726663
97.62 0.01 99.27 0.00 96.85 0.07 100.00 0.00 95.65 0.00 98.57 0.00 100.00 0.00 92.96 0.00 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2572173622
97.63 0.01 99.27 0.00 96.92 0.07 100.00 0.00 95.65 0.00 98.57 0.00 100.00 0.00 92.96 0.00 /workspace/coverage/default/2.i2c_host_stress_all.4015890261


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.4239848330
/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3712354208
/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1160464139
/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3367570286
/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1894787750
/workspace/coverage/cover_reg_top/0.i2c_intr_test.3696537436
/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1188742392
/workspace/coverage/cover_reg_top/0.i2c_tl_errors.2736843826
/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1257891259
/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1112424731
/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.25084071
/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2047999321
/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3594544632
/workspace/coverage/cover_reg_top/1.i2c_intr_test.3939649124
/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.4085189689
/workspace/coverage/cover_reg_top/1.i2c_tl_errors.1785915080
/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1686160904
/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.925687906
/workspace/coverage/cover_reg_top/10.i2c_csr_rw.2710812164
/workspace/coverage/cover_reg_top/10.i2c_intr_test.564629284
/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.4256765188
/workspace/coverage/cover_reg_top/10.i2c_tl_errors.3258067658
/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3019417437
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.520461064
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.1576890997
/workspace/coverage/cover_reg_top/11.i2c_intr_test.2036074954
/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1898526330
/workspace/coverage/cover_reg_top/11.i2c_tl_errors.776423592
/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3324097540
/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1822389295
/workspace/coverage/cover_reg_top/12.i2c_csr_rw.2507204175
/workspace/coverage/cover_reg_top/12.i2c_intr_test.866782776
/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2121141733
/workspace/coverage/cover_reg_top/12.i2c_tl_errors.4017956500
/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.97445523
/workspace/coverage/cover_reg_top/13.i2c_csr_rw.2819846259
/workspace/coverage/cover_reg_top/13.i2c_intr_test.3379290449
/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3557683359
/workspace/coverage/cover_reg_top/13.i2c_tl_errors.1116552331
/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1518953101
/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2752920430
/workspace/coverage/cover_reg_top/14.i2c_csr_rw.1200298544
/workspace/coverage/cover_reg_top/14.i2c_intr_test.1690829694
/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2951559434
/workspace/coverage/cover_reg_top/14.i2c_tl_errors.3482955405
/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.4223449853
/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2235819910
/workspace/coverage/cover_reg_top/15.i2c_csr_rw.1957929051
/workspace/coverage/cover_reg_top/15.i2c_intr_test.2222109811
/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3331824899
/workspace/coverage/cover_reg_top/15.i2c_tl_errors.2728714018
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2383759385
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.2240655302
/workspace/coverage/cover_reg_top/16.i2c_intr_test.2931008134
/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2949834607
/workspace/coverage/cover_reg_top/16.i2c_tl_errors.141586807
/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1775923286
/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3035061723
/workspace/coverage/cover_reg_top/17.i2c_csr_rw.1913718603
/workspace/coverage/cover_reg_top/17.i2c_intr_test.751070783
/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1806775744
/workspace/coverage/cover_reg_top/17.i2c_tl_errors.2682121745
/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2686094813
/workspace/coverage/cover_reg_top/18.i2c_csr_rw.3541201403
/workspace/coverage/cover_reg_top/18.i2c_intr_test.3113154501
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3708934733
/workspace/coverage/cover_reg_top/18.i2c_tl_errors.3666989513
/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1946187631
/workspace/coverage/cover_reg_top/19.i2c_csr_rw.3137428099
/workspace/coverage/cover_reg_top/19.i2c_intr_test.2294907684
/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3129560529
/workspace/coverage/cover_reg_top/19.i2c_tl_errors.68102267
/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2537483077
/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2093647129
/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3128302334
/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.37303726
/workspace/coverage/cover_reg_top/2.i2c_csr_rw.317720150
/workspace/coverage/cover_reg_top/2.i2c_intr_test.186249322
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.849463976
/workspace/coverage/cover_reg_top/2.i2c_tl_errors.2675342298
/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.313262485
/workspace/coverage/cover_reg_top/20.i2c_intr_test.3579592921
/workspace/coverage/cover_reg_top/21.i2c_intr_test.3955322040
/workspace/coverage/cover_reg_top/22.i2c_intr_test.2587759130
/workspace/coverage/cover_reg_top/24.i2c_intr_test.2215463623
/workspace/coverage/cover_reg_top/25.i2c_intr_test.3987094195
/workspace/coverage/cover_reg_top/26.i2c_intr_test.3102885399
/workspace/coverage/cover_reg_top/27.i2c_intr_test.2418686672
/workspace/coverage/cover_reg_top/28.i2c_intr_test.3109722064
/workspace/coverage/cover_reg_top/29.i2c_intr_test.2000903538
/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.86041613
/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1221816808
/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.951681822
/workspace/coverage/cover_reg_top/3.i2c_csr_rw.3764272436
/workspace/coverage/cover_reg_top/3.i2c_intr_test.2046369176
/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.4014124448
/workspace/coverage/cover_reg_top/3.i2c_tl_errors.2546015272
/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1925727262
/workspace/coverage/cover_reg_top/30.i2c_intr_test.3488820464
/workspace/coverage/cover_reg_top/31.i2c_intr_test.293480147
/workspace/coverage/cover_reg_top/32.i2c_intr_test.1554030407
/workspace/coverage/cover_reg_top/34.i2c_intr_test.532793058
/workspace/coverage/cover_reg_top/35.i2c_intr_test.3911840389
/workspace/coverage/cover_reg_top/36.i2c_intr_test.1759425512
/workspace/coverage/cover_reg_top/37.i2c_intr_test.3355824617
/workspace/coverage/cover_reg_top/38.i2c_intr_test.3159679534
/workspace/coverage/cover_reg_top/39.i2c_intr_test.2999935100
/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1994938939
/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.962730587
/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2893449413
/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.261070139
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.3123406289
/workspace/coverage/cover_reg_top/4.i2c_intr_test.120557784
/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2952965402
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.3147108438
/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3902359520
/workspace/coverage/cover_reg_top/40.i2c_intr_test.2848145146
/workspace/coverage/cover_reg_top/41.i2c_intr_test.1290016684
/workspace/coverage/cover_reg_top/42.i2c_intr_test.3798306524
/workspace/coverage/cover_reg_top/43.i2c_intr_test.321083007
/workspace/coverage/cover_reg_top/44.i2c_intr_test.3670676456
/workspace/coverage/cover_reg_top/45.i2c_intr_test.2402029905
/workspace/coverage/cover_reg_top/46.i2c_intr_test.657240466
/workspace/coverage/cover_reg_top/47.i2c_intr_test.2279098575
/workspace/coverage/cover_reg_top/48.i2c_intr_test.2158817154
/workspace/coverage/cover_reg_top/49.i2c_intr_test.3599209046
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2691316505
/workspace/coverage/cover_reg_top/5.i2c_csr_rw.214318863
/workspace/coverage/cover_reg_top/5.i2c_intr_test.16558156
/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1952683080
/workspace/coverage/cover_reg_top/5.i2c_tl_errors.1371713835
/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1851130378
/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.4266696589
/workspace/coverage/cover_reg_top/6.i2c_csr_rw.1998163220
/workspace/coverage/cover_reg_top/6.i2c_intr_test.2662630141
/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3301212522
/workspace/coverage/cover_reg_top/6.i2c_tl_errors.3843862249
/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3966193150
/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.948230934
/workspace/coverage/cover_reg_top/7.i2c_csr_rw.2621221994
/workspace/coverage/cover_reg_top/7.i2c_intr_test.2813469790
/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2252019559
/workspace/coverage/cover_reg_top/7.i2c_tl_errors.3602103343
/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1632090220
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3103514712
/workspace/coverage/cover_reg_top/8.i2c_csr_rw.2206751767
/workspace/coverage/cover_reg_top/8.i2c_intr_test.1676575158
/workspace/coverage/cover_reg_top/8.i2c_tl_errors.547974372
/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.818619882
/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3661677080
/workspace/coverage/cover_reg_top/9.i2c_csr_rw.4019921610
/workspace/coverage/cover_reg_top/9.i2c_intr_test.2002299893
/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3250133082
/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3774472275
/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3106795097
/workspace/coverage/default/0.i2c_alert_test.3251663951
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Total test records in report: 1632
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T19 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2280851883 Jan 21 07:30:54 PM PST 24 Jan 21 07:31:00 PM PST 24 102018096 ps
T20 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.4266696589 Jan 21 07:31:11 PM PST 24 Jan 21 07:31:24 PM PST 24 40233374 ps
T21 /workspace/coverage/cover_reg_top/33.i2c_intr_test.777539184 Jan 21 07:31:50 PM PST 24 Jan 21 07:31:54 PM PST 24 50231781 ps
T22 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3543633347 Jan 21 07:31:02 PM PST 24 Jan 21 07:31:07 PM PST 24 23723246 ps
T23 /workspace/coverage/cover_reg_top/24.i2c_intr_test.2215463623 Jan 21 07:31:37 PM PST 24 Jan 21 07:31:45 PM PST 24 26951905 ps
T24 /workspace/coverage/cover_reg_top/47.i2c_intr_test.2279098575 Jan 21 07:31:58 PM PST 24 Jan 21 07:32:02 PM PST 24 117575617 ps
T25 /workspace/coverage/cover_reg_top/23.i2c_intr_test.2975536072 Jan 21 07:31:41 PM PST 24 Jan 21 07:31:49 PM PST 24 26525382 ps
T26 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2893449413 Jan 21 07:30:58 PM PST 24 Jan 21 07:31:03 PM PST 24 68021122 ps
T27 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3712354208 Jan 21 09:05:58 PM PST 24 Jan 21 09:06:34 PM PST 24 95256453 ps
T28 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.86041613 Jan 21 07:31:00 PM PST 24 Jan 21 07:31:05 PM PST 24 108548965 ps
T119 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2093647129 Jan 21 08:50:58 PM PST 24 Jan 21 08:51:35 PM PST 24 152397110 ps
T80 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.317720150 Jan 21 07:30:52 PM PST 24 Jan 21 07:30:58 PM PST 24 33639181 ps
T75 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.313262485 Jan 21 08:41:20 PM PST 24 Jan 21 08:41:25 PM PST 24 59865190 ps
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