Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7776892	1			T21	5		T23	5		T24	5
all_pins[1]	7776892	1			T21	5		T23	5		T24	5
all_pins[2]	7776892	1			T21	5		T23	5		T24	5
all_pins[3]	7776892	1			T21	5		T23	5		T24	5
all_pins[4]	7776892	1			T21	5		T23	5		T24	5
all_pins[5]	7776892	1			T21	5		T23	5		T24	5
all_pins[6]	7776892	1			T21	5		T23	5		T24	5
all_pins[7]	7776892	1			T21	5		T23	5		T24	5
all_pins[8]	7776892	1			T21	5		T23	5		T24	5
all_pins[9]	7776892	1			T21	5		T23	5		T24	5
all_pins[10]	7776892	1			T21	5		T23	5		T24	5
all_pins[11]	7776892	1			T21	5		T23	5		T24	5
all_pins[12]	7776892	1			T21	5		T23	5		T24	5
all_pins[13]	7776892	1			T21	5		T23	5		T24	5
all_pins[14]	7776892	1			T21	5		T23	5		T24	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	111101827	1			T21	66		T23	68		T24	68
values[0x1]	5551553	1			T21	9		T23	7		T24	7
transitions[0x0=>0x1]	3761182	1			T21	8		T23	7		T24	6
transitions[0x1=>0x0]	3761191	1			T21	8		T23	7		T24	7

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	6965337	1			T21	5		T23	5		T24	5
all_pins[0]	values[0x1]	811555	1			T25	2		T100	3		T142	4
all_pins[0]	transitions[0x0=>0x1]	190400	1			T25	2		T100	1		T142	1
all_pins[0]	transitions[0x1=>0x0]	33857	1			T21	1		T25	1		T66	4
all_pins[1]	values[0x0]	7121880	1			T21	4		T23	5		T24	5
all_pins[1]	values[0x1]	655012	1			T21	1		T25	1		T66	4
all_pins[1]	transitions[0x0=>0x1]	654986	1			T21	1		T66	2		T67	1
all_pins[1]	transitions[0x1=>0x0]	84	1			T23	1		T67	2		T166	2
all_pins[2]	values[0x0]	7776782	1			T21	5		T23	4		T24	5
all_pins[2]	values[0x1]	110	1			T23	1		T25	1		T66	2
all_pins[2]	transitions[0x0=>0x1]	84	1			T23	1		T66	2		T67	2
all_pins[2]	transitions[0x1=>0x0]	104	1			T25	1		T100	3		T142	1
all_pins[3]	values[0x0]	7776762	1			T21	5		T23	5		T24	5
all_pins[3]	values[0x1]	130	1			T25	2		T100	3		T142	3
all_pins[3]	transitions[0x0=>0x1]	98	1			T25	2		T100	3		T142	1
all_pins[3]	transitions[0x1=>0x0]	151	1			T21	1		T24	1		T66	3
all_pins[4]	values[0x0]	7776709	1			T21	4		T23	5		T24	4
all_pins[4]	values[0x1]	183	1			T21	1		T24	1		T66	3
all_pins[4]	transitions[0x0=>0x1]	142	1			T21	1		T24	1		T66	2
all_pins[4]	transitions[0x1=>0x0]	1372	1			T25	2		T66	1		T100	3
all_pins[5]	values[0x0]	7775479	1			T21	5		T23	5		T24	5
all_pins[5]	values[0x1]	1413	1			T25	2		T66	2		T67	2
all_pins[5]	transitions[0x0=>0x1]	1228	1			T25	2		T66	1		T67	2
all_pins[5]	transitions[0x1=>0x0]	865269	1			T21	1		T23	1		T24	2
all_pins[6]	values[0x0]	6911438	1			T21	4		T23	4		T24	3
all_pins[6]	values[0x1]	865454	1			T21	1		T23	1		T24	2
all_pins[6]	transitions[0x0=>0x1]	843673	1			T21	1		T23	1		T24	2
all_pins[6]	transitions[0x1=>0x0]	330082	1			T23	2		T25	2		T100	1
all_pins[7]	values[0x0]	7425029	1			T21	5		T23	3		T24	5
all_pins[7]	values[0x1]	351863	1			T23	2		T25	2		T100	1
all_pins[7]	transitions[0x0=>0x1]	286832	1			T23	2		T25	2		T100	1
all_pins[7]	transitions[0x1=>0x0]	1015482	1			T21	1		T67	1		T166	2
all_pins[8]	values[0x0]	6696379	1			T21	4		T23	5		T24	5
all_pins[8]	values[0x1]	1080513	1			T21	1		T67	1		T166	2
all_pins[8]	transitions[0x0=>0x1]	248151	1			T21	1		T67	1		T166	2
all_pins[8]	transitions[0x1=>0x0]	211450	1			T21	2		T25	2		T66	2
all_pins[9]	values[0x0]	6733080	1			T21	3		T23	5		T24	5
all_pins[9]	values[0x1]	1043812	1			T21	2		T25	2		T66	2
all_pins[9]	transitions[0x0=>0x1]	955916	1			T21	1		T25	2		T100	3
all_pins[9]	transitions[0x1=>0x0]	78427	1			T21	1		T24	2		T66	3
all_pins[10]	values[0x0]	7610569	1			T21	3		T23	5		T24	3
all_pins[10]	values[0x1]	166323	1			T21	2		T24	2		T66	5
all_pins[10]	transitions[0x0=>0x1]	4572	1			T21	2		T24	2		T66	4
all_pins[10]	transitions[0x1=>0x0]	413135	1			T24	1		T25	2		T66	1
all_pins[11]	values[0x0]	7202006	1			T21	5		T23	5		T24	4
all_pins[11]	values[0x1]	574886	1			T24	1		T25	2		T66	2
all_pins[11]	transitions[0x0=>0x1]	574864	1			T24	1		T25	2		T66	2
all_pins[11]	transitions[0x1=>0x0]	64	1			T21	1		T23	1		T66	2
all_pins[12]	values[0x0]	7776806	1			T21	4		T23	4		T24	5
all_pins[12]	values[0x1]	86	1			T21	1		T23	1		T66	2
all_pins[12]	transitions[0x0=>0x1]	69	1			T21	1		T23	1		T66	1
all_pins[12]	transitions[0x1=>0x0]	88	1			T66	1		T100	2		T31	14
all_pins[13]	values[0x0]	7776787	1			T21	5		T23	5		T24	5
all_pins[13]	values[0x1]	105	1			T66	2		T100	2		T31	18
all_pins[13]	transitions[0x0=>0x1]	86	1			T66	2		T100	2		T31	12
all_pins[13]	transitions[0x1=>0x0]	89	1			T23	2		T24	1		T66	1
all_pins[14]	values[0x0]	7776784	1			T21	5		T23	3		T24	4
all_pins[14]	values[0x1]	108	1			T23	2		T24	1		T66	1
all_pins[14]	transitions[0x0=>0x1]	81	1			T23	2		T66	1		T167	2
all_pins[14]	transitions[0x1=>0x0]	811537	1			T25	2		T100	2		T142	3