Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	503	1			T21	4		T23	4		T24	4
all_values[1]	503	1			T21	4		T23	4		T24	4
all_values[2]	503	1			T21	4		T23	4		T24	4
all_values[3]	503	1			T21	4		T23	4		T24	4
all_values[4]	503	1			T21	4		T23	4		T24	4
all_values[5]	503	1			T21	4		T23	4		T24	4
all_values[6]	503	1			T21	4		T23	4		T24	4
all_values[7]	503	1			T21	4		T23	4		T24	4
all_values[8]	503	1			T21	4		T23	4		T24	4
all_values[9]	503	1			T21	4		T23	4		T24	4
all_values[10]	503	1			T21	4		T23	4		T24	4
all_values[11]	503	1			T21	4		T23	4		T24	4
all_values[12]	503	1			T21	4		T23	4		T24	4
all_values[13]	503	1			T21	4		T23	4		T24	4
all_values[14]	503	1			T21	4		T23	4		T24	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3928

1

T21

32

T23

41

T24

34

auto[1]

3617

1

T21

28

T23

19

T24

26

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1230

1

T21

20

T23

18

T24

14

auto[1]

6315

1

T21

40

T23

42

T24

46

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4499

1

T21

42

T23

38

T24

39

auto[1]

3046

1

T21

18

T23

22

T24

21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	52	1			T24	1		T66	1		T142	1
all_values[0]	auto[0]	auto[0]	auto[1]	102	1			T21	2		T23	2		T24	1
all_values[0]	auto[0]	auto[1]	auto[0]	42	1			T24	1		T66	1		T31	4
all_values[0]	auto[0]	auto[1]	auto[1]	114	1			T21	1		T23	1		T25	1
all_values[0]	auto[1]	auto[0]	auto[1]	103	1			T21	1		T23	1		T24	1
all_values[0]	auto[1]	auto[1]	auto[1]	90	1			T66	1		T100	2		T142	1
all_values[1]	auto[0]	auto[0]	auto[0]	52	1			T21	1		T23	4		T167	1
all_values[1]	auto[0]	auto[0]	auto[1]	102	1			T21	1		T24	2		T25	1
all_values[1]	auto[0]	auto[1]	auto[0]	46	1			T166	2		T137	1		T175	1
all_values[1]	auto[0]	auto[1]	auto[1]	108	1			T25	1		T66	2		T67	1
all_values[1]	auto[1]	auto[0]	auto[1]	95	1			T24	1		T25	1		T66	3
all_values[1]	auto[1]	auto[1]	auto[1]	100	1			T21	2		T24	1		T25	1
all_values[2]	auto[0]	auto[0]	auto[0]	40	1			T21	4		T25	1		T167	1
all_values[2]	auto[0]	auto[0]	auto[1]	113	1			T23	1		T24	2		T25	1
all_values[2]	auto[0]	auto[1]	auto[0]	24	1			T166	2		T189	1		T175	2
all_values[2]	auto[0]	auto[1]	auto[1]	129	1			T23	1		T66	3		T67	1
all_values[2]	auto[1]	auto[0]	auto[1]	98	1			T23	1		T24	2		T66	1
all_values[2]	auto[1]	auto[1]	auto[1]	99	1			T23	1		T25	2		T66	3
all_values[3]	auto[0]	auto[0]	auto[0]	45	1			T24	2		T67	1		T167	4
all_values[3]	auto[0]	auto[0]	auto[1]	102	1			T21	1		T23	1		T24	1
all_values[3]	auto[0]	auto[1]	auto[0]	23	1			T31	1		T137	1		T190	1
all_values[3]	auto[0]	auto[1]	auto[1]	117	1			T21	1		T23	1		T25	2
all_values[3]	auto[1]	auto[0]	auto[1]	109	1			T21	2		T23	1		T24	1
all_values[3]	auto[1]	auto[1]	auto[1]	107	1			T23	1		T25	1		T67	1
all_values[4]	auto[0]	auto[0]	auto[0]	48	1			T21	1		T23	3		T25	2
all_values[4]	auto[0]	auto[0]	auto[1]	108	1			T24	1		T25	1		T142	2
all_values[4]	auto[0]	auto[1]	auto[0]	27	1			T23	1		T167	1		T137	1
all_values[4]	auto[0]	auto[1]	auto[1]	100	1			T21	2		T66	2		T67	1
all_values[4]	auto[1]	auto[0]	auto[1]	118	1			T24	1		T25	1		T66	2
all_values[4]	auto[1]	auto[1]	auto[1]	102	1			T21	1		T24	2		T66	1
all_values[5]	auto[0]	auto[0]	auto[0]	71	1			T21	1		T23	1		T67	2
all_values[5]	auto[0]	auto[0]	auto[1]	96	1			T21	2		T24	2		T25	1
all_values[5]	auto[0]	auto[1]	auto[0]	38	1			T23	3		T24	1		T31	3
all_values[5]	auto[0]	auto[1]	auto[1]	116	1			T66	2		T67	1		T100	2
all_values[5]	auto[1]	auto[0]	auto[1]	97	1			T25	1		T66	4		T167	1
all_values[5]	auto[1]	auto[1]	auto[1]	85	1			T21	1		T24	1		T25	2
all_values[6]	auto[0]	auto[0]	auto[0]	45	1			T25	1		T66	2		T100	1
all_values[6]	auto[0]	auto[0]	auto[1]	101	1			T24	2		T25	1		T66	1
all_values[6]	auto[0]	auto[1]	auto[0]	29	1			T100	1		T166	4		T142	1
all_values[6]	auto[0]	auto[1]	auto[1]	108	1			T21	1		T23	2		T66	2
all_values[6]	auto[1]	auto[0]	auto[1]	123	1			T21	1		T23	1		T25	2
all_values[6]	auto[1]	auto[1]	auto[1]	97	1			T21	2		T23	1		T24	2
all_values[7]	auto[0]	auto[0]	auto[0]	54	1			T21	1		T25	2		T66	1
all_values[7]	auto[0]	auto[0]	auto[1]	107	1			T21	1		T23	1		T66	1
all_values[7]	auto[0]	auto[1]	auto[0]	30	1			T21	1		T66	1		T137	3
all_values[7]	auto[0]	auto[1]	auto[1]	114	1			T23	1		T24	2		T25	1
all_values[7]	auto[1]	auto[0]	auto[1]	106	1			T23	1		T24	1		T25	1
all_values[7]	auto[1]	auto[1]	auto[1]	92	1			T21	1		T23	1		T24	1
all_values[8]	auto[0]	auto[0]	auto[0]	48	1			T24	2		T25	1		T66	2
all_values[8]	auto[0]	auto[0]	auto[1]	113	1			T21	1		T23	2		T24	1
all_values[8]	auto[0]	auto[1]	auto[0]	29	1			T25	3		T66	1		T100	1
all_values[8]	auto[0]	auto[1]	auto[1]	115	1			T21	2		T66	1		T166	1
all_values[8]	auto[1]	auto[0]	auto[1]	99	1			T21	1		T23	2		T24	1
all_values[8]	auto[1]	auto[1]	auto[1]	99	1			T67	2		T100	1		T166	1
all_values[9]	auto[0]	auto[0]	auto[0]	33	1			T21	1		T23	1		T24	1
all_values[9]	auto[0]	auto[0]	auto[1]	106	1			T23	1		T67	2		T166	1
all_values[9]	auto[0]	auto[1]	auto[0]	23	1			T21	1		T66	1		T166	2
all_values[9]	auto[0]	auto[1]	auto[1]	112	1			T21	1		T24	2		T25	3
all_values[9]	auto[1]	auto[0]	auto[1]	119	1			T23	2		T24	1		T25	1
all_values[9]	auto[1]	auto[1]	auto[1]	110	1			T21	1		T66	2		T100	2
all_values[10]	auto[0]	auto[0]	auto[0]	50	1			T23	4		T25	1		T167	1
all_values[10]	auto[0]	auto[0]	auto[1]	97	1			T25	1		T66	1		T67	1
all_values[10]	auto[0]	auto[1]	auto[0]	38	1			T100	2		T31	1		T138	1
all_values[10]	auto[0]	auto[1]	auto[1]	114	1			T21	1		T24	2		T25	1
all_values[10]	auto[1]	auto[0]	auto[1]	114	1			T21	2		T25	1		T66	1
all_values[10]	auto[1]	auto[1]	auto[1]	90	1			T21	1		T24	2		T66	4
all_values[11]	auto[0]	auto[0]	auto[0]	52	1			T25	1		T100	1		T166	2
all_values[11]	auto[0]	auto[0]	auto[1]	119	1			T21	2		T23	1		T66	2
all_values[11]	auto[0]	auto[1]	auto[0]	36	1			T67	1		T100	3		T167	1
all_values[11]	auto[0]	auto[1]	auto[1]	105	1			T21	1		T24	3		T25	1
all_values[11]	auto[1]	auto[0]	auto[1]	101	1			T21	1		T23	2		T24	1
all_values[11]	auto[1]	auto[1]	auto[1]	90	1			T23	1		T67	1		T166	1
all_values[12]	auto[0]	auto[0]	auto[0]	52	1			T21	1		T23	1		T24	1
all_values[12]	auto[0]	auto[0]	auto[1]	98	1			T24	1		T66	2		T142	2
all_values[12]	auto[0]	auto[1]	auto[0]	39	1			T24	1		T25	2		T67	2
all_values[12]	auto[0]	auto[1]	auto[1]	122	1			T21	2		T23	1		T66	1
all_values[12]	auto[1]	auto[0]	auto[1]	109	1			T23	1		T24	1		T66	1
all_values[12]	auto[1]	auto[1]	auto[1]	83	1			T21	1		T23	1		T66	2
all_values[13]	auto[0]	auto[0]	auto[0]	48	1			T21	1		T24	2		T25	1
all_values[13]	auto[0]	auto[0]	auto[1]	120	1			T23	2		T66	1		T67	1
all_values[13]	auto[0]	auto[1]	auto[0]	42	1			T21	3		T24	2		T25	3
all_values[13]	auto[0]	auto[1]	auto[1]	96	1			T66	2		T100	1		T166	2
all_values[13]	auto[1]	auto[0]	auto[1]	104	1			T23	2		T67	3		T166	1
all_values[13]	auto[1]	auto[1]	auto[1]	93	1			T66	3		T100	2		T167	1
all_values[14]	auto[0]	auto[0]	auto[0]	45	1			T21	3		T66	2		T100	1
all_values[14]	auto[0]	auto[0]	auto[1]	112	1			T23	1		T24	1		T25	2
all_values[14]	auto[0]	auto[1]	auto[0]	29	1			T21	1		T167	1		T31	1
all_values[14]	auto[0]	auto[1]	auto[1]	103	1			T23	1		T24	2		T25	1
all_values[14]	auto[1]	auto[0]	auto[1]	102	1			T23	1		T25	1		T66	2
all_values[14]	auto[1]	auto[1]	auto[1]	112	1			T23	1		T24	1		T66	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal