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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.63 99.27 96.92 100.00 95.65 98.57 100.00 92.96


Total test records in report: 1632
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T1527 /workspace/coverage/default/43.i2c_target_intr_stress_wr.3970387369 Jan 21 08:41:05 PM PST 24 Jan 21 08:57:02 PM PST 24 20698758189 ps
T126 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3128302334 Jan 21 08:28:35 PM PST 24 Jan 21 08:28:39 PM PST 24 19939486 ps
T1528 /workspace/coverage/cover_reg_top/1.i2c_intr_test.3939649124 Jan 21 07:31:07 PM PST 24 Jan 21 07:31:15 PM PST 24 18228863 ps
T1529 /workspace/coverage/cover_reg_top/27.i2c_intr_test.2418686672 Jan 21 07:31:49 PM PST 24 Jan 21 07:31:54 PM PST 24 18890360 ps
T112 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3602103343 Jan 21 07:31:08 PM PST 24 Jan 21 07:31:17 PM PST 24 299338325 ps
T134 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3541201403 Jan 21 07:31:41 PM PST 24 Jan 21 07:31:48 PM PST 24 66334981 ps
T113 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.141586807 Jan 21 07:31:30 PM PST 24 Jan 21 07:31:38 PM PST 24 29205416 ps
T1530 /workspace/coverage/cover_reg_top/39.i2c_intr_test.2999935100 Jan 21 07:31:53 PM PST 24 Jan 21 07:31:57 PM PST 24 41395525 ps
T1531 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3764272436 Jan 21 08:09:20 PM PST 24 Jan 21 08:09:24 PM PST 24 121190508 ps
T91 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.209933680 Jan 21 07:31:23 PM PST 24 Jan 21 07:31:34 PM PST 24 116491642 ps
T114 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3367570286 Jan 21 07:30:49 PM PST 24 Jan 21 07:30:57 PM PST 24 73408817 ps
T1532 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.2819846259 Jan 21 07:31:34 PM PST 24 Jan 21 07:31:43 PM PST 24 24636038 ps
T1533 /workspace/coverage/cover_reg_top/48.i2c_intr_test.2158817154 Jan 21 07:32:04 PM PST 24 Jan 21 07:32:07 PM PST 24 18224023 ps
T1534 /workspace/coverage/cover_reg_top/40.i2c_intr_test.2848145146 Jan 21 07:32:04 PM PST 24 Jan 21 07:32:07 PM PST 24 21441124 ps
T135 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2252019559 Jan 21 07:31:12 PM PST 24 Jan 21 07:31:24 PM PST 24 170935271 ps
T1535 /workspace/coverage/cover_reg_top/7.i2c_intr_test.2813469790 Jan 21 07:31:11 PM PST 24 Jan 21 07:31:24 PM PST 24 34773294 ps
T121 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.4223449853 Jan 21 07:31:30 PM PST 24 Jan 21 07:31:38 PM PST 24 210013104 ps
T94 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2572173622 Jan 21 07:31:41 PM PST 24 Jan 21 07:31:49 PM PST 24 156742414 ps
T127 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.4239848330 Jan 21 07:30:47 PM PST 24 Jan 21 07:30:56 PM PST 24 714794461 ps
T136 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3557683359 Jan 21 07:58:05 PM PST 24 Jan 21 07:58:07 PM PST 24 67717226 ps
T115 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3324097540 Jan 21 07:31:18 PM PST 24 Jan 21 07:31:31 PM PST 24 70392395 ps
T90 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1851130378 Jan 21 07:31:11 PM PST 24 Jan 21 07:31:25 PM PST 24 54619532 ps
T128 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2537483077 Jan 21 07:31:01 PM PST 24 Jan 21 07:31:07 PM PST 24 251883809 ps
T132 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.962730587 Jan 21 07:31:03 PM PST 24 Jan 21 07:31:12 PM PST 24 153748449 ps
T1536 /workspace/coverage/cover_reg_top/29.i2c_intr_test.2000903538 Jan 21 07:31:49 PM PST 24 Jan 21 07:31:54 PM PST 24 34771207 ps
T1537 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2235819910 Jan 21 07:47:42 PM PST 24 Jan 21 07:47:43 PM PST 24 28038778 ps
T1538 /workspace/coverage/cover_reg_top/10.i2c_intr_test.564629284 Jan 21 07:31:21 PM PST 24 Jan 21 07:31:32 PM PST 24 18301389 ps
T1539 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1994938939 Jan 21 07:31:05 PM PST 24 Jan 21 07:31:13 PM PST 24 165775582 ps
T1540 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2951559434 Jan 21 08:51:43 PM PST 24 Jan 21 08:52:23 PM PST 24 83906209 ps
T1541 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2047999321 Jan 21 08:18:13 PM PST 24 Jan 21 08:18:16 PM PST 24 20396400 ps
T1542 /workspace/coverage/cover_reg_top/15.i2c_intr_test.2222109811 Jan 21 07:31:27 PM PST 24 Jan 21 07:31:35 PM PST 24 22432250 ps
T1543 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1576890997 Jan 21 07:31:25 PM PST 24 Jan 21 07:31:35 PM PST 24 147177489 ps
T1544 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3129560529 Jan 21 08:43:03 PM PST 24 Jan 21 08:43:04 PM PST 24 85506503 ps
T1545 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.3123406289 Jan 21 07:30:58 PM PST 24 Jan 21 07:31:02 PM PST 24 18982645 ps
T1546 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2206751767 Jan 21 07:31:10 PM PST 24 Jan 21 07:31:20 PM PST 24 48876007 ps
T120 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3482955405 Jan 21 07:31:34 PM PST 24 Jan 21 07:31:45 PM PST 24 214944263 ps
T1547 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.1785915080 Jan 21 07:30:54 PM PST 24 Jan 21 07:31:01 PM PST 24 92530881 ps
T1548 /workspace/coverage/cover_reg_top/41.i2c_intr_test.1290016684 Jan 21 07:31:49 PM PST 24 Jan 21 07:31:54 PM PST 24 46601103 ps
T1549 /workspace/coverage/cover_reg_top/14.i2c_intr_test.1690829694 Jan 21 07:31:30 PM PST 24 Jan 21 07:31:37 PM PST 24 31288587 ps
T1550 /workspace/coverage/cover_reg_top/26.i2c_intr_test.3102885399 Jan 21 08:04:11 PM PST 24 Jan 21 08:04:14 PM PST 24 21290672 ps
T1551 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2383759385 Jan 21 07:31:38 PM PST 24 Jan 21 07:31:46 PM PST 24 29424685 ps
T1552 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1371713835 Jan 21 07:31:02 PM PST 24 Jan 21 07:31:09 PM PST 24 89516101 ps
T92 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1686160904 Jan 21 07:30:59 PM PST 24 Jan 21 07:31:04 PM PST 24 59192612 ps
T87 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3019417437 Jan 21 07:31:14 PM PST 24 Jan 21 07:31:27 PM PST 24 1364169802 ps
T1553 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2691316505 Jan 21 07:31:01 PM PST 24 Jan 21 07:31:07 PM PST 24 92045777 ps
T1554 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.948230934 Jan 21 07:31:07 PM PST 24 Jan 21 07:31:16 PM PST 24 23557504 ps
T1555 /workspace/coverage/cover_reg_top/9.i2c_intr_test.2002299893 Jan 21 07:31:15 PM PST 24 Jan 21 07:31:29 PM PST 24 48775759 ps
T1556 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.547974372 Jan 21 07:31:10 PM PST 24 Jan 21 07:31:24 PM PST 24 48236786 ps
T1557 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.2546015272 Jan 21 07:30:56 PM PST 24 Jan 21 07:31:02 PM PST 24 58609899 ps
T1558 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2675342298 Jan 21 07:31:07 PM PST 24 Jan 21 07:31:16 PM PST 24 33071361 ps
T88 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.416170834 Jan 21 08:08:01 PM PST 24 Jan 21 08:08:08 PM PST 24 365875164 ps
T1559 /workspace/coverage/cover_reg_top/12.i2c_intr_test.866782776 Jan 21 07:31:25 PM PST 24 Jan 21 07:31:35 PM PST 24 17147739 ps
T1560 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.818619882 Jan 21 07:31:13 PM PST 24 Jan 21 07:31:25 PM PST 24 230492571 ps
T1561 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1946187631 Jan 21 07:31:40 PM PST 24 Jan 21 07:31:47 PM PST 24 29574804 ps
T89 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1257891259 Jan 21 07:30:50 PM PST 24 Jan 21 07:30:58 PM PST 24 342358756 ps
T1562 /workspace/coverage/cover_reg_top/30.i2c_intr_test.3488820464 Jan 21 07:31:47 PM PST 24 Jan 21 07:31:52 PM PST 24 18030563 ps
T93 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3106795097 Jan 21 07:31:13 PM PST 24 Jan 21 07:31:27 PM PST 24 428792361 ps
T1563 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.951681822 Jan 21 07:31:10 PM PST 24 Jan 21 07:31:20 PM PST 24 36174216 ps
T1564 /workspace/coverage/cover_reg_top/49.i2c_intr_test.3599209046 Jan 21 07:31:51 PM PST 24 Jan 21 07:31:56 PM PST 24 19575050 ps
T129 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2507204175 Jan 21 07:31:27 PM PST 24 Jan 21 07:31:36 PM PST 24 22334531 ps
T1565 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.925687906 Jan 21 07:31:18 PM PST 24 Jan 21 07:31:31 PM PST 24 44167503 ps
T1566 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2121141733 Jan 21 07:31:31 PM PST 24 Jan 21 07:31:38 PM PST 24 156512841 ps
T1567 /workspace/coverage/cover_reg_top/38.i2c_intr_test.3159679534 Jan 21 07:31:55 PM PST 24 Jan 21 07:31:58 PM PST 24 30850185 ps
T1568 /workspace/coverage/cover_reg_top/0.i2c_intr_test.3696537436 Jan 21 07:30:52 PM PST 24 Jan 21 07:30:58 PM PST 24 41112731 ps
T1569 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3966193150 Jan 21 07:31:11 PM PST 24 Jan 21 07:31:25 PM PST 24 47415612 ps
T130 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1957929051 Jan 21 07:31:31 PM PST 24 Jan 21 07:31:37 PM PST 24 24967977 ps
T1570 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.37303726 Jan 21 07:58:25 PM PST 24 Jan 21 07:58:27 PM PST 24 54788711 ps
T1571 /workspace/coverage/cover_reg_top/45.i2c_intr_test.2402029905 Jan 21 07:31:53 PM PST 24 Jan 21 07:31:57 PM PST 24 20162614 ps
T1572 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3147108438 Jan 21 07:31:03 PM PST 24 Jan 21 07:31:11 PM PST 24 88572350 ps
T1573 /workspace/coverage/cover_reg_top/11.i2c_intr_test.2036074954 Jan 21 07:31:23 PM PST 24 Jan 21 07:31:33 PM PST 24 18143954 ps
T1574 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2952965402 Jan 21 07:31:05 PM PST 24 Jan 21 07:31:13 PM PST 24 39003181 ps
T1575 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2710812164 Jan 21 07:31:14 PM PST 24 Jan 21 07:31:27 PM PST 24 23195785 ps
T1576 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.97445523 Jan 21 07:31:34 PM PST 24 Jan 21 07:31:43 PM PST 24 128835067 ps
T1577 /workspace/coverage/cover_reg_top/2.i2c_intr_test.186249322 Jan 21 07:30:57 PM PST 24 Jan 21 07:31:02 PM PST 24 49062479 ps
T1578 /workspace/coverage/cover_reg_top/17.i2c_intr_test.751070783 Jan 21 09:47:25 PM PST 24 Jan 21 09:47:33 PM PST 24 17622258 ps
T1579 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.4014124448 Jan 21 07:30:58 PM PST 24 Jan 21 07:31:02 PM PST 24 26320524 ps
T1580 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.849463976 Jan 21 07:30:59 PM PST 24 Jan 21 07:31:04 PM PST 24 145265572 ps
T1581 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3103514712 Jan 21 07:31:10 PM PST 24 Jan 21 07:31:21 PM PST 24 78384421 ps
T1582 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2240655302 Jan 21 07:31:33 PM PST 24 Jan 21 07:31:41 PM PST 24 30854301 ps
T1583 /workspace/coverage/cover_reg_top/16.i2c_intr_test.2931008134 Jan 21 08:03:43 PM PST 24 Jan 21 08:03:53 PM PST 24 43931122 ps
T1584 /workspace/coverage/cover_reg_top/18.i2c_intr_test.3113154501 Jan 21 07:31:39 PM PST 24 Jan 21 07:31:46 PM PST 24 182692924 ps
T1585 /workspace/coverage/cover_reg_top/32.i2c_intr_test.1554030407 Jan 21 07:31:46 PM PST 24 Jan 21 07:31:52 PM PST 24 16689926 ps
T1586 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2686094813 Jan 21 07:31:38 PM PST 24 Jan 21 07:31:46 PM PST 24 481654024 ps
T1587 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.261070139 Jan 21 07:31:03 PM PST 24 Jan 21 07:31:10 PM PST 24 54537624 ps
T1588 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1952683080 Jan 21 07:31:03 PM PST 24 Jan 21 07:31:10 PM PST 24 82846959 ps
T1589 /workspace/coverage/cover_reg_top/20.i2c_intr_test.3579592921 Jan 21 08:28:47 PM PST 24 Jan 21 08:28:49 PM PST 24 22696048 ps
T1590 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3708934733 Jan 21 07:31:38 PM PST 24 Jan 21 07:31:46 PM PST 24 80733696 ps
T1591 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2621221994 Jan 21 07:31:11 PM PST 24 Jan 21 07:31:24 PM PST 24 25166336 ps
T1592 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1518953101 Jan 21 07:52:06 PM PST 24 Jan 21 07:52:08 PM PST 24 40992222 ps
T1593 /workspace/coverage/cover_reg_top/4.i2c_intr_test.120557784 Jan 21 07:31:02 PM PST 24 Jan 21 07:31:08 PM PST 24 31097820 ps
T1594 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2736843826 Jan 21 07:30:50 PM PST 24 Jan 21 07:30:59 PM PST 24 39788029 ps
T1595 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2752920430 Jan 21 07:43:59 PM PST 24 Jan 21 07:44:04 PM PST 24 123609527 ps
T1596 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3331824899 Jan 21 08:07:27 PM PST 24 Jan 21 08:07:29 PM PST 24 356258802 ps
T1597 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1116552331 Jan 21 07:31:30 PM PST 24 Jan 21 07:31:37 PM PST 24 80536690 ps
T1598 /workspace/coverage/cover_reg_top/3.i2c_intr_test.2046369176 Jan 21 07:30:57 PM PST 24 Jan 21 07:31:02 PM PST 24 42283301 ps
T1599 /workspace/coverage/cover_reg_top/19.i2c_intr_test.2294907684 Jan 21 08:08:02 PM PST 24 Jan 21 08:08:07 PM PST 24 53134379 ps
T1600 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2949834607 Jan 21 07:31:32 PM PST 24 Jan 21 07:31:40 PM PST 24 31293834 ps
T1601 /workspace/coverage/cover_reg_top/34.i2c_intr_test.532793058 Jan 21 07:31:51 PM PST 24 Jan 21 07:31:55 PM PST 24 234036169 ps
T1602 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1160464139 Jan 21 07:30:49 PM PST 24 Jan 21 07:30:56 PM PST 24 29767681 ps
T1603 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3666989513 Jan 21 08:07:55 PM PST 24 Jan 21 08:08:03 PM PST 24 47348348 ps
T1604 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2682121745 Jan 21 07:31:32 PM PST 24 Jan 21 07:31:40 PM PST 24 45806766 ps
T1605 /workspace/coverage/cover_reg_top/43.i2c_intr_test.321083007 Jan 21 07:31:52 PM PST 24 Jan 21 07:31:56 PM PST 24 212329363 ps
T1606 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.4019921610 Jan 21 07:31:12 PM PST 24 Jan 21 07:31:24 PM PST 24 50356003 ps
T1607 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3843862249 Jan 21 07:31:11 PM PST 24 Jan 21 07:31:24 PM PST 24 82301359 ps
T1608 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.25084071 Jan 21 07:30:57 PM PST 24 Jan 21 07:31:05 PM PST 24 420255302 ps
T95 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3902359520 Jan 21 07:31:02 PM PST 24 Jan 21 07:31:08 PM PST 24 340822592 ps
T1609 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1898526330 Jan 21 07:54:11 PM PST 24 Jan 21 07:54:14 PM PST 24 247504443 ps
T1610 /workspace/coverage/cover_reg_top/5.i2c_intr_test.16558156 Jan 21 07:31:02 PM PST 24 Jan 21 07:31:07 PM PST 24 22369814 ps
T1611 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.4017956500 Jan 21 07:31:21 PM PST 24 Jan 21 07:31:33 PM PST 24 79982054 ps
T1612 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1998163220 Jan 21 07:31:07 PM PST 24 Jan 21 07:31:15 PM PST 24 111303253 ps
T1613 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.3774472275 Jan 21 07:31:15 PM PST 24 Jan 21 07:31:29 PM PST 24 462565340 ps
T1614 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2728714018 Jan 21 07:31:30 PM PST 24 Jan 21 07:31:38 PM PST 24 28448382 ps
T1615 /workspace/coverage/cover_reg_top/35.i2c_intr_test.3911840389 Jan 21 07:31:55 PM PST 24 Jan 21 07:31:58 PM PST 24 30741449 ps
T1616 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1775923286 Jan 21 07:31:33 PM PST 24 Jan 21 07:31:43 PM PST 24 222824209 ps
T1617 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3137428099 Jan 21 07:31:40 PM PST 24 Jan 21 07:31:48 PM PST 24 57585616 ps
T1618 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3301212522 Jan 21 07:31:12 PM PST 24 Jan 21 07:31:24 PM PST 24 121949087 ps
T1619 /workspace/coverage/cover_reg_top/8.i2c_intr_test.1676575158 Jan 21 07:31:10 PM PST 24 Jan 21 07:31:21 PM PST 24 20331090 ps
T1620 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3661677080 Jan 21 07:31:13 PM PST 24 Jan 21 07:31:26 PM PST 24 54406083 ps
T1621 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.3258067658 Jan 21 07:31:23 PM PST 24 Jan 21 07:31:33 PM PST 24 311232012 ps
T1622 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.776423592 Jan 21 08:19:35 PM PST 24 Jan 21 08:19:38 PM PST 24 306786772 ps
T1623 /workspace/coverage/cover_reg_top/6.i2c_intr_test.2662630141 Jan 21 07:31:08 PM PST 24 Jan 21 07:31:16 PM PST 24 19355284 ps
T1624 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.4256765188 Jan 21 07:31:20 PM PST 24 Jan 21 07:31:32 PM PST 24 34889078 ps
T1625 /workspace/coverage/cover_reg_top/25.i2c_intr_test.3987094195 Jan 21 07:31:39 PM PST 24 Jan 21 07:31:46 PM PST 24 27226966 ps
T96 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1925727262 Jan 21 07:30:57 PM PST 24 Jan 21 07:31:03 PM PST 24 100663361 ps
T1626 /workspace/coverage/cover_reg_top/36.i2c_intr_test.1759425512 Jan 21 07:31:45 PM PST 24 Jan 21 07:31:51 PM PST 24 54037652 ps
T1627 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1822389295 Jan 21 08:02:20 PM PST 24 Jan 21 08:02:25 PM PST 24 60278908 ps
T1628 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1221816808 Jan 21 07:31:02 PM PST 24 Jan 21 07:31:09 PM PST 24 58998852 ps
T131 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1913718603 Jan 21 07:31:34 PM PST 24 Jan 21 07:31:42 PM PST 24 18824448 ps
T1629 /workspace/coverage/cover_reg_top/37.i2c_intr_test.3355824617 Jan 21 07:31:47 PM PST 24 Jan 21 07:31:52 PM PST 24 15785992 ps
T1630 /workspace/coverage/cover_reg_top/21.i2c_intr_test.3955322040 Jan 21 08:04:27 PM PST 24 Jan 21 08:04:30 PM PST 24 44339132 ps
T1631 /workspace/coverage/cover_reg_top/22.i2c_intr_test.2587759130 Jan 21 07:31:38 PM PST 24 Jan 21 07:31:46 PM PST 24 20996709 ps
T1632 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1894787750 Jan 21 07:30:51 PM PST 24 Jan 21 07:30:58 PM PST 24 80023050 ps

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2280851883
Short name T19
Test name
Test status
Simulation time 102018096 ps
CPU time 0.71 seconds
Started Jan 21 07:30:54 PM PST 24
Finished Jan 21 07:31:00 PM PST 24
Peak memory 203284 kb
Host smart-ded4d08d-b86c-4f3b-807e-c3a4ebbcc229
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280851883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.2280851883
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.890391453
Short name T3
Test name
Test status
Simulation time 57560260084 ps
CPU time 524.78 seconds
Started Jan 21 08:44:41 PM PST 24
Finished Jan 21 08:53:27 PM PST 24
Peak memory 1352668 kb
Host smart-b58c3fcd-2aca-4cfd-8bee-b244e1abc842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890391453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.890391453
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.777539184
Short name T21
Test name
Test status
Simulation time 50231781 ps
CPU time 0.65 seconds
Started Jan 21 07:31:50 PM PST 24
Finished Jan 21 07:31:54 PM PST 24
Peak memory 203148 kb
Host smart-07b40a0b-bde0-4643-b657-6aebe385f283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777539184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.777539184
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/default/34.i2c_target_stress_all.170169701
Short name T43
Test name
Test status
Simulation time 7523588242 ps
CPU time 33.12 seconds
Started Jan 21 08:35:25 PM PST 24
Finished Jan 21 08:35:59 PM PST 24
Peak memory 247184 kb
Host smart-53061b04-92cd-4cb5-97e5-f93ef65143e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170169701 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.i2c_target_stress_all.170169701
Directory /workspace/34.i2c_target_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all_with_rand_reset.2777842252
Short name T31
Test name
Test status
Simulation time 50285502346 ps
CPU time 1000.9 seconds
Started Jan 21 08:31:23 PM PST 24
Finished Jan 21 08:48:09 PM PST 24
Peak memory 1118592 kb
Host smart-38512dba-5fff-4114-9951-50d7526ed33c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777842252 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 27.i2c_host_stress_all_with_rand_reset.2777842252
Directory /workspace/27.i2c_host_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3644996229
Short name T79
Test name
Test status
Simulation time 88500685 ps
CPU time 1.91 seconds
Started Jan 21 08:12:10 PM PST 24
Finished Jan 21 08:12:14 PM PST 24
Peak memory 203420 kb
Host smart-37bf66b7-72ee-42ca-a635-85ddf3127632
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644996229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3644996229
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_target_stress_all.2759167832
Short name T149
Test name
Test status
Simulation time 45862535664 ps
CPU time 901.97 seconds
Started Jan 21 08:17:23 PM PST 24
Finished Jan 21 08:32:26 PM PST 24
Peak memory 2664076 kb
Host smart-f3b91769-3bde-4afb-805e-18409efbdc74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759167832 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.i2c_target_stress_all.2759167832
Directory /workspace/0.i2c_target_stress_all/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.2975536072
Short name T25
Test name
Test status
Simulation time 26525382 ps
CPU time 0.69 seconds
Started Jan 21 07:31:41 PM PST 24
Finished Jan 21 07:31:49 PM PST 24
Peak memory 203128 kb
Host smart-669ff874-dee2-41a8-9a98-ed524289f22f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975536072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.2975536072
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/default/33.i2c_host_perf.412066404
Short name T44
Test name
Test status
Simulation time 8979880010 ps
CPU time 15.28 seconds
Started Jan 21 08:34:39 PM PST 24
Finished Jan 21 08:34:55 PM PST 24
Peak memory 202588 kb
Host smart-27086ccb-3cae-4819-b30e-fcdc3f2c0e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412066404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.412066404
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_override.1098705528
Short name T4
Test name
Test status
Simulation time 20831413 ps
CPU time 0.71 seconds
Started Jan 21 08:24:48 PM PST 24
Finished Jan 21 08:24:52 PM PST 24
Peak memory 201512 kb
Host smart-4179855f-f1cc-4df2-a6ed-af6383309620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098705528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1098705528
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.989269092
Short name T53
Test name
Test status
Simulation time 1005832729 ps
CPU time 4.44 seconds
Started Jan 21 08:17:06 PM PST 24
Finished Jan 21 08:17:12 PM PST 24
Peak memory 202720 kb
Host smart-f5be1a44-83c1-47e7-90d2-f4de656cb678
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989269092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.989269092
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.394008303
Short name T102
Test name
Test status
Simulation time 64889702 ps
CPU time 1.01 seconds
Started Jan 21 08:17:25 PM PST 24
Finished Jan 21 08:17:27 PM PST 24
Peak memory 219948 kb
Host smart-0fca4074-b152-48c1-936f-0f39744a524b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394008303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.394008303
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3543633347
Short name T22
Test name
Test status
Simulation time 23723246 ps
CPU time 0.8 seconds
Started Jan 21 07:31:02 PM PST 24
Finished Jan 21 07:31:07 PM PST 24
Peak memory 203240 kb
Host smart-5a997614-a854-4854-8f2e-097e5b6372fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543633347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.3543633347
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.1369463448
Short name T35
Test name
Test status
Simulation time 3489411728 ps
CPU time 92.01 seconds
Started Jan 21 08:45:06 PM PST 24
Finished Jan 21 08:46:40 PM PST 24
Peak memory 235240 kb
Host smart-6166eeab-743f-4a6e-91fa-14c30e88172d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369463448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.1369463448
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.955067574
Short name T137
Test name
Test status
Simulation time 14950868659 ps
CPU time 1061.88 seconds
Started Jan 21 08:24:32 PM PST 24
Finished Jan 21 08:42:15 PM PST 24
Peak memory 1649584 kb
Host smart-ea0666a0-855c-4fb7-92f5-6a5debdf3d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955067574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.955067574
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.1023613135
Short name T39
Test name
Test status
Simulation time 1869239145 ps
CPU time 3.94 seconds
Started Jan 21 08:20:48 PM PST 24
Finished Jan 21 08:20:54 PM PST 24
Peak memory 202496 kb
Host smart-cb3a7ead-2f22-4f42-ace7-79f234ce2226
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023613135 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.1023613135
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.4261727618
Short name T50
Test name
Test status
Simulation time 322363479 ps
CPU time 1.1 seconds
Started Jan 21 08:23:54 PM PST 24
Finished Jan 21 08:23:56 PM PST 24
Peak memory 202272 kb
Host smart-cc3171ef-d78e-4c23-b75d-977b275d85ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261727618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.4261727618
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.1575549545
Short name T175
Test name
Test status
Simulation time 105072918223 ps
CPU time 1482.13 seconds
Started Jan 21 08:38:49 PM PST 24
Finished Jan 21 09:03:35 PM PST 24
Peak memory 2218152 kb
Host smart-5e0fe7f9-07ef-4f66-939c-16ba06391725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575549545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.1575549545
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_alert_test.3489649144
Short name T234
Test name
Test status
Simulation time 68634194 ps
CPU time 0.62 seconds
Started Jan 21 08:23:17 PM PST 24
Finished Jan 21 08:23:18 PM PST 24
Peak memory 201120 kb
Host smart-fdac0bf5-20d8-404e-a03e-fe102daa37bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489649144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.3489649144
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_target_stress_all.3793016242
Short name T165
Test name
Test status
Simulation time 50393109988 ps
CPU time 68.91 seconds
Started Jan 21 08:24:36 PM PST 24
Finished Jan 21 08:25:46 PM PST 24
Peak memory 677100 kb
Host smart-c5cb1fa4-e655-473f-9499-981674f3ad7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793016242 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_target_stress_all.3793016242
Directory /workspace/13.i2c_target_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_perf.3507182957
Short name T159
Test name
Test status
Simulation time 3681578753 ps
CPU time 16.7 seconds
Started Jan 21 09:22:46 PM PST 24
Finished Jan 21 09:23:06 PM PST 24
Peak memory 226764 kb
Host smart-8bc38f3c-6af0-4514-b134-198676db3685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507182957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.3507182957
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.1476545307
Short name T12
Test name
Test status
Simulation time 28606561675 ps
CPU time 572.94 seconds
Started Jan 21 08:33:12 PM PST 24
Finished Jan 21 08:42:46 PM PST 24
Peak memory 1852612 kb
Host smart-e3241c9d-75f5-4cc6-aaec-a4cc6e353d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476545307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.1476545307
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.1919438541
Short name T56
Test name
Test status
Simulation time 40921592633 ps
CPU time 309.26 seconds
Started Jan 21 08:31:51 PM PST 24
Finished Jan 21 08:37:01 PM PST 24
Peak memory 1657684 kb
Host smart-2cc6dfce-a0b2-4d89-9347-32dd02507993
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919438541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.1919438541
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.416170834
Short name T88
Test name
Test status
Simulation time 365875164 ps
CPU time 1.82 seconds
Started Jan 21 08:08:01 PM PST 24
Finished Jan 21 08:08:08 PM PST 24
Peak memory 203444 kb
Host smart-e5b55856-613d-4ce6-ba18-4ea9ae5f7d77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416170834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.416170834
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/1.i2c_host_override.1040498963
Short name T157
Test name
Test status
Simulation time 24987599 ps
CPU time 0.64 seconds
Started Jan 21 08:17:25 PM PST 24
Finished Jan 21 08:17:26 PM PST 24
Peak memory 201548 kb
Host smart-a8347cf8-4bc9-467c-87b1-5fb57f82152e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040498963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.1040498963
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_rx_oversample.757641874
Short name T180
Test name
Test status
Simulation time 2426688367 ps
CPU time 283.51 seconds
Started Jan 21 08:55:28 PM PST 24
Finished Jan 21 09:00:32 PM PST 24
Peak memory 316720 kb
Host smart-d4d7263c-fff0-414b-b03d-fb0e706f457e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757641874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_rx_oversample.
757641874
Directory /workspace/23.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.4095183232
Short name T1140
Test name
Test status
Simulation time 901716814 ps
CPU time 2.64 seconds
Started Jan 21 08:29:56 PM PST 24
Finished Jan 21 08:29:59 PM PST 24
Peak memory 202680 kb
Host smart-d04e8513-905a-42d7-a343-d80ac6fdb328
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095183232 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.4095183232
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.827428157
Short name T139
Test name
Test status
Simulation time 10755433594 ps
CPU time 1454.73 seconds
Started Jan 21 08:32:42 PM PST 24
Finished Jan 21 08:56:58 PM PST 24
Peak memory 1807108 kb
Host smart-4dee8d28-0b46-4cfe-a464-9daf29f2f006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827428157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.827428157
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.2043048719
Short name T69
Test name
Test status
Simulation time 10136779598 ps
CPU time 13.58 seconds
Started Jan 21 08:23:06 PM PST 24
Finished Jan 21 08:23:20 PM PST 24
Peak memory 270120 kb
Host smart-a13d0825-caf0-4c41-8719-c4781a6ec5fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043048719 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.2043048719
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.209933680
Short name T91
Test name
Test status
Simulation time 116491642 ps
CPU time 1.93 seconds
Started Jan 21 07:31:23 PM PST 24
Finished Jan 21 07:31:34 PM PST 24
Peak memory 203460 kb
Host smart-de644585-5da8-4d9a-a29e-cbf7aeb0c964
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209933680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.209933680
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.288559220
Short name T709
Test name
Test status
Simulation time 666971426 ps
CPU time 3.7 seconds
Started Jan 21 09:00:09 PM PST 24
Finished Jan 21 09:00:40 PM PST 24
Peak memory 202476 kb
Host smart-d2961aa3-4020-4727-b4a2-7e3f0e8ba6eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288559220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.288559220
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.1107997282
Short name T154
Test name
Test status
Simulation time 6572296845 ps
CPU time 2.43 seconds
Started Jan 21 08:23:42 PM PST 24
Finished Jan 21 08:23:45 PM PST 24
Peak memory 202704 kb
Host smart-79962c60-58a2-4f9a-80de-0b4bf0ba0507
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107997282 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.1107997282
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_stress_all.82924734
Short name T173
Test name
Test status
Simulation time 96275845102 ps
CPU time 58.78 seconds
Started Jan 21 08:26:00 PM PST 24
Finished Jan 21 08:27:00 PM PST 24
Peak memory 471460 kb
Host smart-1103eefd-5bdc-4d2e-a225-3c374fe672b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82924734 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.i2c_target_stress_all.82924734
Directory /workspace/16.i2c_target_stress_all/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.1396629108
Short name T194
Test name
Test status
Simulation time 10072353301 ps
CPU time 35.9 seconds
Started Jan 21 08:26:22 PM PST 24
Finished Jan 21 08:26:59 PM PST 24
Peak memory 366608 kb
Host smart-f161bd63-f0f0-4060-a229-ff406934418e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396629108 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.1396629108
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.3091018606
Short name T179
Test name
Test status
Simulation time 23384449483 ps
CPU time 347.35 seconds
Started Jan 21 08:27:05 PM PST 24
Finished Jan 21 08:32:53 PM PST 24
Peak memory 1602356 kb
Host smart-42507b19-b4f8-44aa-8128-58029543edd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091018606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.3091018606
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.1589211441
Short name T198
Test name
Test status
Simulation time 60654441798 ps
CPU time 3087.18 seconds
Started Jan 21 08:27:19 PM PST 24
Finished Jan 21 09:18:48 PM PST 24
Peak memory 3474252 kb
Host smart-a0efb9f5-7f98-4ed1-809e-312db1426a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589211441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.1589211441
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.1901217054
Short name T200
Test name
Test status
Simulation time 1475228405 ps
CPU time 1.01 seconds
Started Jan 21 08:29:39 PM PST 24
Finished Jan 21 08:29:41 PM PST 24
Peak memory 202264 kb
Host smart-9e8dab02-08ea-43d7-891a-b7540fdca56c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901217054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.1901217054
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.821726663
Short name T155
Test name
Test status
Simulation time 23196891176 ps
CPU time 1289.85 seconds
Started Jan 21 09:23:01 PM PST 24
Finished Jan 21 09:44:32 PM PST 24
Peak memory 1740532 kb
Host smart-db5599ff-1d91-410f-97a3-a024e47e4af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821726663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.821726663
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2572173622
Short name T94
Test name
Test status
Simulation time 156742414 ps
CPU time 1.26 seconds
Started Jan 21 07:31:41 PM PST 24
Finished Jan 21 07:31:49 PM PST 24
Peak memory 203428 kb
Host smart-053dfb68-a590-47d3-8cdc-bb83d87024d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572173622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2572173622
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.4015890261
Short name T45
Test name
Test status
Simulation time 15019452912 ps
CPU time 1471.53 seconds
Started Jan 21 08:18:16 PM PST 24
Finished Jan 21 08:42:50 PM PST 24
Peak memory 2057300 kb
Host smart-0fc034b9-2f6a-4516-a89d-b56f6079b735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015890261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.4015890261
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.4239848330
Short name T127
Test name
Test status
Simulation time 714794461 ps
CPU time 1.3 seconds
Started Jan 21 07:30:47 PM PST 24
Finished Jan 21 07:30:56 PM PST 24
Peak memory 203660 kb
Host smart-3b145573-f47b-483d-bec4-35892486b460
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239848330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.4239848330
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3712354208
Short name T27
Test name
Test status
Simulation time 95256453 ps
CPU time 3.58 seconds
Started Jan 21 09:05:58 PM PST 24
Finished Jan 21 09:06:34 PM PST 24
Peak memory 203448 kb
Host smart-a6be5c99-8561-4d31-a75a-e96c77b6e1ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712354208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.3712354208
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1160464139
Short name T1602
Test name
Test status
Simulation time 29767681 ps
CPU time 0.74 seconds
Started Jan 21 07:30:49 PM PST 24
Finished Jan 21 07:30:56 PM PST 24
Peak memory 203272 kb
Host smart-85cfb20b-bdf8-4040-a760-f076bcc7a7d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160464139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.1160464139
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3367570286
Short name T114
Test name
Test status
Simulation time 73408817 ps
CPU time 1.15 seconds
Started Jan 21 07:30:49 PM PST 24
Finished Jan 21 07:30:57 PM PST 24
Peak memory 203512 kb
Host smart-41105c85-516f-4092-83eb-8cdc68f55bb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367570286 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.3367570286
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1894787750
Short name T1632
Test name
Test status
Simulation time 80023050 ps
CPU time 0.71 seconds
Started Jan 21 07:30:51 PM PST 24
Finished Jan 21 07:30:58 PM PST 24
Peak memory 203224 kb
Host smart-23fcdad6-8298-43f6-a2a7-9296e64c877e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894787750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1894787750
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.3696537436
Short name T1568
Test name
Test status
Simulation time 41112731 ps
CPU time 0.64 seconds
Started Jan 21 07:30:52 PM PST 24
Finished Jan 21 07:30:58 PM PST 24
Peak memory 203144 kb
Host smart-7383463e-c14d-48eb-acf3-a5168b1c0fad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696537436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3696537436
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1188742392
Short name T133
Test name
Test status
Simulation time 136074471 ps
CPU time 1 seconds
Started Jan 21 07:30:55 PM PST 24
Finished Jan 21 07:31:01 PM PST 24
Peak memory 203452 kb
Host smart-aa1d4627-6b88-4acb-8e26-d66fbd0c4186
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188742392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.1188742392
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2736843826
Short name T1594
Test name
Test status
Simulation time 39788029 ps
CPU time 2.08 seconds
Started Jan 21 07:30:50 PM PST 24
Finished Jan 21 07:30:59 PM PST 24
Peak memory 203448 kb
Host smart-84e1f359-09cb-42d3-8f42-2f5ac8da6866
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736843826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.2736843826
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1257891259
Short name T89
Test name
Test status
Simulation time 342358756 ps
CPU time 1.19 seconds
Started Jan 21 07:30:50 PM PST 24
Finished Jan 21 07:30:58 PM PST 24
Peak memory 203380 kb
Host smart-b52ccfc3-5a55-41c7-9704-c045d1f42e63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257891259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.1257891259
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1112424731
Short name T124
Test name
Test status
Simulation time 63761223 ps
CPU time 0.93 seconds
Started Jan 21 07:30:57 PM PST 24
Finished Jan 21 07:31:02 PM PST 24
Peak memory 203240 kb
Host smart-4e1edd21-1376-421f-aa0f-f66da363997d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112424731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.1112424731
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.25084071
Short name T1608
Test name
Test status
Simulation time 420255302 ps
CPU time 4.44 seconds
Started Jan 21 07:30:57 PM PST 24
Finished Jan 21 07:31:05 PM PST 24
Peak memory 203500 kb
Host smart-1170814e-9616-4125-a6bb-b215e5307ee2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25084071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.25084071
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2047999321
Short name T1541
Test name
Test status
Simulation time 20396400 ps
CPU time 0.7 seconds
Started Jan 21 08:18:13 PM PST 24
Finished Jan 21 08:18:16 PM PST 24
Peak memory 203244 kb
Host smart-bcc6e45c-f6e5-491f-9876-8fe19b2726fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047999321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2047999321
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3594544632
Short name T141
Test name
Test status
Simulation time 18419549 ps
CPU time 0.75 seconds
Started Jan 21 08:04:48 PM PST 24
Finished Jan 21 08:04:50 PM PST 24
Peak memory 203272 kb
Host smart-e60e5ffc-90d9-4108-8cb8-ad0514aec73f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594544632 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.3594544632
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.3939649124
Short name T1528
Test name
Test status
Simulation time 18228863 ps
CPU time 0.68 seconds
Started Jan 21 07:31:07 PM PST 24
Finished Jan 21 07:31:15 PM PST 24
Peak memory 203148 kb
Host smart-b8c11c85-8d93-4307-9d0c-7e9dad571038
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939649124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3939649124
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.4085189689
Short name T122
Test name
Test status
Simulation time 39510186 ps
CPU time 0.93 seconds
Started Jan 21 08:09:35 PM PST 24
Finished Jan 21 08:09:37 PM PST 24
Peak memory 203292 kb
Host smart-6007e3a9-1569-4c10-aae2-3e682c7de641
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085189689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.4085189689
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.1785915080
Short name T1547
Test name
Test status
Simulation time 92530881 ps
CPU time 1.14 seconds
Started Jan 21 07:30:54 PM PST 24
Finished Jan 21 07:31:01 PM PST 24
Peak memory 203300 kb
Host smart-c17f2cf3-6e57-4bdd-96ef-c69efd10939e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785915080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.1785915080
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1686160904
Short name T92
Test name
Test status
Simulation time 59192612 ps
CPU time 1.23 seconds
Started Jan 21 07:30:59 PM PST 24
Finished Jan 21 07:31:04 PM PST 24
Peak memory 203512 kb
Host smart-e797b1eb-0dd2-4f5b-aa49-58663a44c18a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686160904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.1686160904
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.925687906
Short name T1565
Test name
Test status
Simulation time 44167503 ps
CPU time 1.29 seconds
Started Jan 21 07:31:18 PM PST 24
Finished Jan 21 07:31:31 PM PST 24
Peak memory 203492 kb
Host smart-bb3686a7-4bc7-449e-8ac1-af34fe6f8c25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925687906 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.925687906
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2710812164
Short name T1575
Test name
Test status
Simulation time 23195785 ps
CPU time 0.77 seconds
Started Jan 21 07:31:14 PM PST 24
Finished Jan 21 07:31:27 PM PST 24
Peak memory 203200 kb
Host smart-c943bf56-47fe-4e94-a074-e3b6777b3057
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710812164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.2710812164
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.564629284
Short name T1538
Test name
Test status
Simulation time 18301389 ps
CPU time 0.66 seconds
Started Jan 21 07:31:21 PM PST 24
Finished Jan 21 07:31:32 PM PST 24
Peak memory 203144 kb
Host smart-665785d4-e1a6-4220-bd2d-aa82ff9b8398
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564629284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.564629284
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.4256765188
Short name T1624
Test name
Test status
Simulation time 34889078 ps
CPU time 0.79 seconds
Started Jan 21 07:31:20 PM PST 24
Finished Jan 21 07:31:32 PM PST 24
Peak memory 203188 kb
Host smart-460ca599-3bd8-4fab-9743-24bb2dc8127c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256765188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.4256765188
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.3258067658
Short name T1621
Test name
Test status
Simulation time 311232012 ps
CPU time 1.06 seconds
Started Jan 21 07:31:23 PM PST 24
Finished Jan 21 07:31:33 PM PST 24
Peak memory 203240 kb
Host smart-c75e0777-ca2d-4c0a-b814-81f3ab00f546
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258067658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.3258067658
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3019417437
Short name T87
Test name
Test status
Simulation time 1364169802 ps
CPU time 1.81 seconds
Started Jan 21 07:31:14 PM PST 24
Finished Jan 21 07:31:27 PM PST 24
Peak memory 203508 kb
Host smart-9fdd1e04-bacc-4bc8-b7a4-253dbdf53dbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019417437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.3019417437
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.520461064
Short name T77
Test name
Test status
Simulation time 64887469 ps
CPU time 0.92 seconds
Started Jan 21 07:31:25 PM PST 24
Finished Jan 21 07:31:35 PM PST 24
Peak memory 203348 kb
Host smart-bc624c66-597e-44ae-ac14-d3b65b299359
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520461064 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.520461064
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1576890997
Short name T1543
Test name
Test status
Simulation time 147177489 ps
CPU time 0.71 seconds
Started Jan 21 07:31:25 PM PST 24
Finished Jan 21 07:31:35 PM PST 24
Peak memory 203268 kb
Host smart-3dc55784-475c-4dba-924a-1d0f536d45b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576890997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1576890997
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.2036074954
Short name T1573
Test name
Test status
Simulation time 18143954 ps
CPU time 0.7 seconds
Started Jan 21 07:31:23 PM PST 24
Finished Jan 21 07:31:33 PM PST 24
Peak memory 203100 kb
Host smart-d6608d04-c0b1-4265-b99b-3596e256a4f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036074954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.2036074954
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1898526330
Short name T1609
Test name
Test status
Simulation time 247504443 ps
CPU time 0.99 seconds
Started Jan 21 07:54:11 PM PST 24
Finished Jan 21 07:54:14 PM PST 24
Peak memory 203272 kb
Host smart-53ad298f-d026-4c82-8adc-e075f7344149
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898526330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.1898526330
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.776423592
Short name T1622
Test name
Test status
Simulation time 306786772 ps
CPU time 1.57 seconds
Started Jan 21 08:19:35 PM PST 24
Finished Jan 21 08:19:38 PM PST 24
Peak memory 203476 kb
Host smart-24fde97d-7b23-4d7c-ab52-1baf58ab32e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776423592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.776423592
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3324097540
Short name T115
Test name
Test status
Simulation time 70392395 ps
CPU time 1.22 seconds
Started Jan 21 07:31:18 PM PST 24
Finished Jan 21 07:31:31 PM PST 24
Peak memory 203400 kb
Host smart-d5ddaa1e-cd03-4eaf-9cd6-dca4116afcb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324097540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.3324097540
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1822389295
Short name T1627
Test name
Test status
Simulation time 60278908 ps
CPU time 0.73 seconds
Started Jan 21 08:02:20 PM PST 24
Finished Jan 21 08:02:25 PM PST 24
Peak memory 203324 kb
Host smart-3dcce087-045f-42ca-9a4d-afb46e334fe4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822389295 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1822389295
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2507204175
Short name T129
Test name
Test status
Simulation time 22334531 ps
CPU time 0.78 seconds
Started Jan 21 07:31:27 PM PST 24
Finished Jan 21 07:31:36 PM PST 24
Peak memory 202936 kb
Host smart-7288e540-42a5-481d-8a52-e41b46541d58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507204175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.2507204175
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.866782776
Short name T1559
Test name
Test status
Simulation time 17147739 ps
CPU time 0.69 seconds
Started Jan 21 07:31:25 PM PST 24
Finished Jan 21 07:31:35 PM PST 24
Peak memory 203200 kb
Host smart-8a104c36-3104-4b3b-a48f-ee38ba6b7544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866782776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.866782776
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2121141733
Short name T1566
Test name
Test status
Simulation time 156512841 ps
CPU time 0.79 seconds
Started Jan 21 07:31:31 PM PST 24
Finished Jan 21 07:31:38 PM PST 24
Peak memory 203228 kb
Host smart-c25bcc87-7b3b-4539-9bd6-6745fadcb0ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121141733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.2121141733
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.4017956500
Short name T1611
Test name
Test status
Simulation time 79982054 ps
CPU time 1.73 seconds
Started Jan 21 07:31:21 PM PST 24
Finished Jan 21 07:31:33 PM PST 24
Peak memory 203444 kb
Host smart-a50e3406-94f6-41e4-aaa8-dd0f0d443ddf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017956500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.4017956500
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.97445523
Short name T1576
Test name
Test status
Simulation time 128835067 ps
CPU time 1 seconds
Started Jan 21 07:31:34 PM PST 24
Finished Jan 21 07:31:43 PM PST 24
Peak memory 203312 kb
Host smart-0779a522-91d8-4294-916d-291ec63c6e4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97445523 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.97445523
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.2819846259
Short name T1532
Test name
Test status
Simulation time 24636038 ps
CPU time 0.81 seconds
Started Jan 21 07:31:34 PM PST 24
Finished Jan 21 07:31:43 PM PST 24
Peak memory 203216 kb
Host smart-589b03fe-cef3-4fa2-a06f-f45858253d17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819846259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.2819846259
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.3379290449
Short name T166
Test name
Test status
Simulation time 20354443 ps
CPU time 0.65 seconds
Started Jan 21 08:10:45 PM PST 24
Finished Jan 21 08:10:48 PM PST 24
Peak memory 201168 kb
Host smart-9a8a4962-4d7b-43e6-92ab-17cfc0749020
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379290449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.3379290449
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3557683359
Short name T136
Test name
Test status
Simulation time 67717226 ps
CPU time 0.98 seconds
Started Jan 21 07:58:05 PM PST 24
Finished Jan 21 07:58:07 PM PST 24
Peak memory 203276 kb
Host smart-a013757d-5b11-44e3-875d-27f8f3c57b0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557683359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.3557683359
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1116552331
Short name T1597
Test name
Test status
Simulation time 80536690 ps
CPU time 1.06 seconds
Started Jan 21 07:31:30 PM PST 24
Finished Jan 21 07:31:37 PM PST 24
Peak memory 203152 kb
Host smart-8bcb8db8-b148-4d5b-8c4f-7a7829c5cf04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116552331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.1116552331
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1518953101
Short name T1592
Test name
Test status
Simulation time 40992222 ps
CPU time 1.18 seconds
Started Jan 21 07:52:06 PM PST 24
Finished Jan 21 07:52:08 PM PST 24
Peak memory 203444 kb
Host smart-245525c6-b40d-483c-8562-c2d5b1713851
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518953101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.1518953101
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2752920430
Short name T1595
Test name
Test status
Simulation time 123609527 ps
CPU time 1.32 seconds
Started Jan 21 07:43:59 PM PST 24
Finished Jan 21 07:44:04 PM PST 24
Peak memory 203536 kb
Host smart-19668e4f-0402-40ed-a609-f25aad19d824
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752920430 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.2752920430
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1200298544
Short name T116
Test name
Test status
Simulation time 23984637 ps
CPU time 0.73 seconds
Started Jan 21 07:31:30 PM PST 24
Finished Jan 21 07:31:37 PM PST 24
Peak memory 203216 kb
Host smart-fbca35ea-c929-49c0-be61-6311abdd2307
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200298544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.1200298544
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.1690829694
Short name T1549
Test name
Test status
Simulation time 31288587 ps
CPU time 0.69 seconds
Started Jan 21 07:31:30 PM PST 24
Finished Jan 21 07:31:37 PM PST 24
Peak memory 203140 kb
Host smart-66d8dfc5-5af9-453a-86ac-375382b2d5b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690829694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1690829694
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2951559434
Short name T1540
Test name
Test status
Simulation time 83906209 ps
CPU time 0.99 seconds
Started Jan 21 08:51:43 PM PST 24
Finished Jan 21 08:52:23 PM PST 24
Peak memory 203496 kb
Host smart-1384398a-6c98-4969-9207-adcd0abbb424
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951559434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.2951559434
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3482955405
Short name T120
Test name
Test status
Simulation time 214944263 ps
CPU time 2.49 seconds
Started Jan 21 07:31:34 PM PST 24
Finished Jan 21 07:31:45 PM PST 24
Peak memory 203480 kb
Host smart-0e6d4abb-de77-45d3-a01d-95ec2a6f2a80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482955405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3482955405
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.4223449853
Short name T121
Test name
Test status
Simulation time 210013104 ps
CPU time 1.29 seconds
Started Jan 21 07:31:30 PM PST 24
Finished Jan 21 07:31:38 PM PST 24
Peak memory 203340 kb
Host smart-a5fa99bf-e8ed-48ae-bcec-28d2783ef1ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223449853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.4223449853
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2235819910
Short name T1537
Test name
Test status
Simulation time 28038778 ps
CPU time 0.89 seconds
Started Jan 21 07:47:42 PM PST 24
Finished Jan 21 07:47:43 PM PST 24
Peak memory 203272 kb
Host smart-e2b61224-b6e0-4832-b982-e7130453301a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235819910 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.2235819910
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1957929051
Short name T130
Test name
Test status
Simulation time 24967977 ps
CPU time 0.77 seconds
Started Jan 21 07:31:31 PM PST 24
Finished Jan 21 07:31:37 PM PST 24
Peak memory 203236 kb
Host smart-94315d28-db2d-4c05-97a9-c1b8e105e020
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957929051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1957929051
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.2222109811
Short name T1542
Test name
Test status
Simulation time 22432250 ps
CPU time 0.64 seconds
Started Jan 21 07:31:27 PM PST 24
Finished Jan 21 07:31:35 PM PST 24
Peak memory 203096 kb
Host smart-1d19df40-bab0-46df-b40c-9e65d2fca858
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222109811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.2222109811
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3331824899
Short name T1596
Test name
Test status
Simulation time 356258802 ps
CPU time 1.01 seconds
Started Jan 21 08:07:27 PM PST 24
Finished Jan 21 08:07:29 PM PST 24
Peak memory 203372 kb
Host smart-e443eb54-7858-47bc-b1fe-90226f1d0ed6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331824899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.3331824899
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2728714018
Short name T1614
Test name
Test status
Simulation time 28448382 ps
CPU time 1.3 seconds
Started Jan 21 07:31:30 PM PST 24
Finished Jan 21 07:31:38 PM PST 24
Peak memory 203484 kb
Host smart-cead8a36-2f4c-4a63-8d24-5e224a09c0e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728714018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.2728714018
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2383759385
Short name T1551
Test name
Test status
Simulation time 29424685 ps
CPU time 0.97 seconds
Started Jan 21 07:31:38 PM PST 24
Finished Jan 21 07:31:46 PM PST 24
Peak memory 203324 kb
Host smart-204e6e5f-fcc3-4778-8aff-ce7222a020ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383759385 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.2383759385
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2240655302
Short name T1582
Test name
Test status
Simulation time 30854301 ps
CPU time 0.66 seconds
Started Jan 21 07:31:33 PM PST 24
Finished Jan 21 07:31:41 PM PST 24
Peak memory 202428 kb
Host smart-8decdffa-9f8b-4840-b651-701dc1897fa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240655302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.2240655302
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.2931008134
Short name T1583
Test name
Test status
Simulation time 43931122 ps
CPU time 0.7 seconds
Started Jan 21 08:03:43 PM PST 24
Finished Jan 21 08:03:53 PM PST 24
Peak memory 203160 kb
Host smart-468be32d-81ec-449d-ba3d-deb97b156f39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931008134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.2931008134
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2949834607
Short name T1600
Test name
Test status
Simulation time 31293834 ps
CPU time 0.82 seconds
Started Jan 21 07:31:32 PM PST 24
Finished Jan 21 07:31:40 PM PST 24
Peak memory 203200 kb
Host smart-76ae93bd-ee67-4545-a509-f64cdd6ce819
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949834607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.2949834607
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.141586807
Short name T113
Test name
Test status
Simulation time 29205416 ps
CPU time 1.48 seconds
Started Jan 21 07:31:30 PM PST 24
Finished Jan 21 07:31:38 PM PST 24
Peak memory 203416 kb
Host smart-33eb5538-580f-495e-8fea-d31a85fd70cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141586807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.141586807
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1775923286
Short name T1616
Test name
Test status
Simulation time 222824209 ps
CPU time 2.01 seconds
Started Jan 21 07:31:33 PM PST 24
Finished Jan 21 07:31:43 PM PST 24
Peak memory 203440 kb
Host smart-21f6c416-7d81-4003-86b5-db7d646d7b0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775923286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.1775923286
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3035061723
Short name T78
Test name
Test status
Simulation time 31487889 ps
CPU time 0.91 seconds
Started Jan 21 07:31:38 PM PST 24
Finished Jan 21 07:31:46 PM PST 24
Peak memory 203348 kb
Host smart-eb1aa4cf-53b3-4e4b-aafc-bc0453c5343f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035061723 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3035061723
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1913718603
Short name T131
Test name
Test status
Simulation time 18824448 ps
CPU time 0.7 seconds
Started Jan 21 07:31:34 PM PST 24
Finished Jan 21 07:31:42 PM PST 24
Peak memory 203156 kb
Host smart-311bd2e4-ae5c-4912-8ab8-e4ef44761c9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913718603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.1913718603
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.751070783
Short name T1578
Test name
Test status
Simulation time 17622258 ps
CPU time 0.67 seconds
Started Jan 21 09:47:25 PM PST 24
Finished Jan 21 09:47:33 PM PST 24
Peak memory 203164 kb
Host smart-29021038-6347-48a1-aeb3-6f60470c4365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751070783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.751070783
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1806775744
Short name T117
Test name
Test status
Simulation time 181945320 ps
CPU time 1.13 seconds
Started Jan 21 07:31:38 PM PST 24
Finished Jan 21 07:31:46 PM PST 24
Peak memory 203464 kb
Host smart-6b61246a-7958-43a9-9e03-dce480598cc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806775744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.1806775744
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2682121745
Short name T1604
Test name
Test status
Simulation time 45806766 ps
CPU time 1.27 seconds
Started Jan 21 07:31:32 PM PST 24
Finished Jan 21 07:31:40 PM PST 24
Peak memory 203504 kb
Host smart-6d82f319-98ae-4d9d-905f-6b7409011b63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682121745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.2682121745
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2686094813
Short name T1586
Test name
Test status
Simulation time 481654024 ps
CPU time 1.49 seconds
Started Jan 21 07:31:38 PM PST 24
Finished Jan 21 07:31:46 PM PST 24
Peak memory 203524 kb
Host smart-8c97fe4c-8055-4266-9b0f-37fc793fb1d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686094813 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2686094813
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3541201403
Short name T134
Test name
Test status
Simulation time 66334981 ps
CPU time 0.77 seconds
Started Jan 21 07:31:41 PM PST 24
Finished Jan 21 07:31:48 PM PST 24
Peak memory 203220 kb
Host smart-585809ba-ea79-46af-b7b1-1132d4450a50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541201403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.3541201403
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.3113154501
Short name T1584
Test name
Test status
Simulation time 182692924 ps
CPU time 0.76 seconds
Started Jan 21 07:31:39 PM PST 24
Finished Jan 21 07:31:46 PM PST 24
Peak memory 203152 kb
Host smart-62dc0548-90a8-44fe-84bc-4b61b4c4f3f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113154501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3113154501
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3708934733
Short name T1590
Test name
Test status
Simulation time 80733696 ps
CPU time 1.05 seconds
Started Jan 21 07:31:38 PM PST 24
Finished Jan 21 07:31:46 PM PST 24
Peak memory 203376 kb
Host smart-83da4f26-ddc0-49f2-ba08-09002b521a07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708934733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.3708934733
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3666989513
Short name T1603
Test name
Test status
Simulation time 47348348 ps
CPU time 2.04 seconds
Started Jan 21 08:07:55 PM PST 24
Finished Jan 21 08:08:03 PM PST 24
Peak memory 203420 kb
Host smart-1d9f3310-50f2-44ef-86d5-c223109813a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666989513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.3666989513
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1946187631
Short name T1561
Test name
Test status
Simulation time 29574804 ps
CPU time 0.98 seconds
Started Jan 21 07:31:40 PM PST 24
Finished Jan 21 07:31:47 PM PST 24
Peak memory 203352 kb
Host smart-87b2a2f6-4075-484c-aa27-17202110bb91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946187631 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.1946187631
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3137428099
Short name T1617
Test name
Test status
Simulation time 57585616 ps
CPU time 0.73 seconds
Started Jan 21 07:31:40 PM PST 24
Finished Jan 21 07:31:48 PM PST 24
Peak memory 203236 kb
Host smart-9154bfa3-c747-4ba8-894f-c4a2ca959f71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137428099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3137428099
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.2294907684
Short name T1599
Test name
Test status
Simulation time 53134379 ps
CPU time 0.71 seconds
Started Jan 21 08:08:02 PM PST 24
Finished Jan 21 08:08:07 PM PST 24
Peak memory 203132 kb
Host smart-6783f18a-709a-44df-8538-609fc7ecb745
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294907684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.2294907684
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3129560529
Short name T1544
Test name
Test status
Simulation time 85506503 ps
CPU time 0.97 seconds
Started Jan 21 08:43:03 PM PST 24
Finished Jan 21 08:43:04 PM PST 24
Peak memory 203372 kb
Host smart-3e172299-b281-4e9a-8c7b-0544d25a2cd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129560529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.3129560529
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.68102267
Short name T81
Test name
Test status
Simulation time 162942479 ps
CPU time 2.01 seconds
Started Jan 21 07:31:40 PM PST 24
Finished Jan 21 07:31:49 PM PST 24
Peak memory 203468 kb
Host smart-687897e5-9455-4bdd-8472-d1138fd89a3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68102267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.68102267
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2537483077
Short name T128
Test name
Test status
Simulation time 251883809 ps
CPU time 1.28 seconds
Started Jan 21 07:31:01 PM PST 24
Finished Jan 21 07:31:07 PM PST 24
Peak memory 203388 kb
Host smart-2d8fdf96-874c-4742-9a4e-7cd088ea0b23
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537483077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2537483077
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2093647129
Short name T119
Test name
Test status
Simulation time 152397110 ps
CPU time 2.37 seconds
Started Jan 21 08:50:58 PM PST 24
Finished Jan 21 08:51:35 PM PST 24
Peak memory 203488 kb
Host smart-b0c73c73-9d22-4708-8c0f-578b15a93ebf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093647129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.2093647129
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3128302334
Short name T126
Test name
Test status
Simulation time 19939486 ps
CPU time 0.69 seconds
Started Jan 21 08:28:35 PM PST 24
Finished Jan 21 08:28:39 PM PST 24
Peak memory 202072 kb
Host smart-97651e76-0033-4e24-a116-6716313bc247
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128302334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.3128302334
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.37303726
Short name T1570
Test name
Test status
Simulation time 54788711 ps
CPU time 0.9 seconds
Started Jan 21 07:58:25 PM PST 24
Finished Jan 21 07:58:27 PM PST 24
Peak memory 203348 kb
Host smart-e29710ec-b719-4487-938d-1c0f3beef16e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37303726 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.37303726
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.317720150
Short name T80
Test name
Test status
Simulation time 33639181 ps
CPU time 0.64 seconds
Started Jan 21 07:30:52 PM PST 24
Finished Jan 21 07:30:58 PM PST 24
Peak memory 202464 kb
Host smart-5672612f-3376-4af8-93f8-8c569f8bd20a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317720150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.317720150
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.186249322
Short name T1577
Test name
Test status
Simulation time 49062479 ps
CPU time 0.68 seconds
Started Jan 21 07:30:57 PM PST 24
Finished Jan 21 07:31:02 PM PST 24
Peak memory 203176 kb
Host smart-de3b7554-0d74-41d6-816b-a923deadade9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186249322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.186249322
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.849463976
Short name T1580
Test name
Test status
Simulation time 145265572 ps
CPU time 1.01 seconds
Started Jan 21 07:30:59 PM PST 24
Finished Jan 21 07:31:04 PM PST 24
Peak memory 203372 kb
Host smart-a0e9c5ed-4170-495d-8154-7fbe1d0381fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849463976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_out
standing.849463976
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2675342298
Short name T1558
Test name
Test status
Simulation time 33071361 ps
CPU time 1.4 seconds
Started Jan 21 07:31:07 PM PST 24
Finished Jan 21 07:31:16 PM PST 24
Peak memory 203484 kb
Host smart-bb7adf7e-7d74-4408-b8ee-ed2a640545e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675342298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.2675342298
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.313262485
Short name T75
Test name
Test status
Simulation time 59865190 ps
CPU time 1.21 seconds
Started Jan 21 08:41:20 PM PST 24
Finished Jan 21 08:41:25 PM PST 24
Peak memory 203528 kb
Host smart-fe6be335-e961-4b3a-8457-eafc69e0e3b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313262485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.313262485
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.3579592921
Short name T1589
Test name
Test status
Simulation time 22696048 ps
CPU time 0.65 seconds
Started Jan 21 08:28:47 PM PST 24
Finished Jan 21 08:28:49 PM PST 24
Peak memory 203164 kb
Host smart-886803a1-fd42-4a75-a151-5b1650fe036b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579592921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.3579592921
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.3955322040
Short name T1630
Test name
Test status
Simulation time 44339132 ps
CPU time 0.66 seconds
Started Jan 21 08:04:27 PM PST 24
Finished Jan 21 08:04:30 PM PST 24
Peak memory 203136 kb
Host smart-6600c7de-eba5-43a0-8796-5e6573f906ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955322040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.3955322040
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.2587759130
Short name T1631
Test name
Test status
Simulation time 20996709 ps
CPU time 0.66 seconds
Started Jan 21 07:31:38 PM PST 24
Finished Jan 21 07:31:46 PM PST 24
Peak memory 203140 kb
Host smart-66eaf2a2-1af6-4fc2-adcf-c737994c1bdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587759130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.2587759130
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.2215463623
Short name T23
Test name
Test status
Simulation time 26951905 ps
CPU time 0.68 seconds
Started Jan 21 07:31:37 PM PST 24
Finished Jan 21 07:31:45 PM PST 24
Peak memory 203172 kb
Host smart-0edc5df1-5715-4799-bb36-0168abff9613
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215463623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.2215463623
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.3987094195
Short name T1625
Test name
Test status
Simulation time 27226966 ps
CPU time 0.66 seconds
Started Jan 21 07:31:39 PM PST 24
Finished Jan 21 07:31:46 PM PST 24
Peak memory 203144 kb
Host smart-5dced2f5-46f4-4f6c-8b85-3687627180e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987094195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3987094195
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.3102885399
Short name T1550
Test name
Test status
Simulation time 21290672 ps
CPU time 0.68 seconds
Started Jan 21 08:04:11 PM PST 24
Finished Jan 21 08:04:14 PM PST 24
Peak memory 203116 kb
Host smart-64db6d7f-46a8-452b-9f11-1c7edc50f9bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102885399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.3102885399
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.2418686672
Short name T1529
Test name
Test status
Simulation time 18890360 ps
CPU time 0.65 seconds
Started Jan 21 07:31:49 PM PST 24
Finished Jan 21 07:31:54 PM PST 24
Peak memory 203144 kb
Host smart-f936ba94-a0bf-4e5c-b041-6b1768470303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418686672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.2418686672
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.3109722064
Short name T167
Test name
Test status
Simulation time 37992637 ps
CPU time 0.71 seconds
Started Jan 21 07:31:47 PM PST 24
Finished Jan 21 07:31:52 PM PST 24
Peak memory 203148 kb
Host smart-92861dc2-6038-44b1-909b-d40034d72109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109722064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.3109722064
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.2000903538
Short name T1536
Test name
Test status
Simulation time 34771207 ps
CPU time 0.7 seconds
Started Jan 21 07:31:49 PM PST 24
Finished Jan 21 07:31:54 PM PST 24
Peak memory 203132 kb
Host smart-61598ee9-69e0-43f0-b461-b93773a504b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000903538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.2000903538
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.86041613
Short name T28
Test name
Test status
Simulation time 108548965 ps
CPU time 1.37 seconds
Started Jan 21 07:31:00 PM PST 24
Finished Jan 21 07:31:05 PM PST 24
Peak memory 203484 kb
Host smart-74d13b31-996f-48ea-a994-80bb012c46cf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86041613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.86041613
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1221816808
Short name T1628
Test name
Test status
Simulation time 58998852 ps
CPU time 2.26 seconds
Started Jan 21 07:31:02 PM PST 24
Finished Jan 21 07:31:09 PM PST 24
Peak memory 203240 kb
Host smart-f4bfb14c-7c67-4209-b585-85f44268f0f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221816808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1221816808
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.951681822
Short name T1563
Test name
Test status
Simulation time 36174216 ps
CPU time 0.96 seconds
Started Jan 21 07:31:10 PM PST 24
Finished Jan 21 07:31:20 PM PST 24
Peak memory 203284 kb
Host smart-431d8e98-bcfb-47bd-a4ef-79eb7036bc6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951681822 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.951681822
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3764272436
Short name T1531
Test name
Test status
Simulation time 121190508 ps
CPU time 0.73 seconds
Started Jan 21 08:09:20 PM PST 24
Finished Jan 21 08:09:24 PM PST 24
Peak memory 203220 kb
Host smart-bd6edce5-ef63-47b3-90cc-25ae785ae117
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764272436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3764272436
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.2046369176
Short name T1598
Test name
Test status
Simulation time 42283301 ps
CPU time 0.69 seconds
Started Jan 21 07:30:57 PM PST 24
Finished Jan 21 07:31:02 PM PST 24
Peak memory 203100 kb
Host smart-056c911e-fb47-436f-9585-a068089e3768
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046369176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.2046369176
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.4014124448
Short name T1579
Test name
Test status
Simulation time 26320524 ps
CPU time 0.82 seconds
Started Jan 21 07:30:58 PM PST 24
Finished Jan 21 07:31:02 PM PST 24
Peak memory 203292 kb
Host smart-78229e29-0f44-4b15-ba6b-fb62f16e12d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014124448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.4014124448
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.2546015272
Short name T1557
Test name
Test status
Simulation time 58609899 ps
CPU time 1.3 seconds
Started Jan 21 07:30:56 PM PST 24
Finished Jan 21 07:31:02 PM PST 24
Peak memory 203576 kb
Host smart-18354e76-a460-41a4-9d81-711513567613
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546015272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.2546015272
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1925727262
Short name T96
Test name
Test status
Simulation time 100663361 ps
CPU time 1.88 seconds
Started Jan 21 07:30:57 PM PST 24
Finished Jan 21 07:31:03 PM PST 24
Peak memory 203548 kb
Host smart-eaa5d887-80ae-4a8f-97b0-15dba1d62fb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925727262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.1925727262
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.3488820464
Short name T1562
Test name
Test status
Simulation time 18030563 ps
CPU time 0.68 seconds
Started Jan 21 07:31:47 PM PST 24
Finished Jan 21 07:31:52 PM PST 24
Peak memory 203376 kb
Host smart-d560298f-3193-47ab-9387-dc6912d2c9c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488820464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.3488820464
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.293480147
Short name T100
Test name
Test status
Simulation time 15682828 ps
CPU time 0.67 seconds
Started Jan 21 07:31:47 PM PST 24
Finished Jan 21 07:31:52 PM PST 24
Peak memory 203376 kb
Host smart-85ead9ac-5d19-41bc-8ba5-34fd5b557b80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293480147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.293480147
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.1554030407
Short name T1585
Test name
Test status
Simulation time 16689926 ps
CPU time 0.7 seconds
Started Jan 21 07:31:46 PM PST 24
Finished Jan 21 07:31:52 PM PST 24
Peak memory 203176 kb
Host smart-cb953262-9ef9-4df2-979f-f44caacbfbd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554030407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.1554030407
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.532793058
Short name T1601
Test name
Test status
Simulation time 234036169 ps
CPU time 0.69 seconds
Started Jan 21 07:31:51 PM PST 24
Finished Jan 21 07:31:55 PM PST 24
Peak memory 203176 kb
Host smart-c4ae1de4-0aa0-477a-9ef4-f339decdeb18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532793058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.532793058
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.3911840389
Short name T1615
Test name
Test status
Simulation time 30741449 ps
CPU time 0.67 seconds
Started Jan 21 07:31:55 PM PST 24
Finished Jan 21 07:31:58 PM PST 24
Peak memory 202832 kb
Host smart-ba0cff38-43df-46e2-b5e7-cd34c745a2ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911840389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.3911840389
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1759425512
Short name T1626
Test name
Test status
Simulation time 54037652 ps
CPU time 0.7 seconds
Started Jan 21 07:31:45 PM PST 24
Finished Jan 21 07:31:51 PM PST 24
Peak memory 203116 kb
Host smart-38cfd95f-bbb7-4278-a134-07180c9560a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759425512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1759425512
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.3355824617
Short name T1629
Test name
Test status
Simulation time 15785992 ps
CPU time 0.69 seconds
Started Jan 21 07:31:47 PM PST 24
Finished Jan 21 07:31:52 PM PST 24
Peak memory 203112 kb
Host smart-077194ba-4aa6-471c-a0dd-9e54344b5615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355824617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3355824617
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.3159679534
Short name T1567
Test name
Test status
Simulation time 30850185 ps
CPU time 0.73 seconds
Started Jan 21 07:31:55 PM PST 24
Finished Jan 21 07:31:58 PM PST 24
Peak memory 203180 kb
Host smart-2d603cdd-a79e-4a67-8bcb-bd672b73a91e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159679534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.3159679534
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.2999935100
Short name T1530
Test name
Test status
Simulation time 41395525 ps
CPU time 0.67 seconds
Started Jan 21 07:31:53 PM PST 24
Finished Jan 21 07:31:57 PM PST 24
Peak memory 203120 kb
Host smart-999eed04-a28f-4ead-a415-5bc26aee0de7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999935100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.2999935100
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1994938939
Short name T1539
Test name
Test status
Simulation time 165775582 ps
CPU time 0.99 seconds
Started Jan 21 07:31:05 PM PST 24
Finished Jan 21 07:31:13 PM PST 24
Peak memory 203132 kb
Host smart-ac869a83-acd7-4799-859c-19f83ed2fce9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994938939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1994938939
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.962730587
Short name T132
Test name
Test status
Simulation time 153748449 ps
CPU time 2.51 seconds
Started Jan 21 07:31:03 PM PST 24
Finished Jan 21 07:31:12 PM PST 24
Peak memory 203392 kb
Host smart-69efd7a1-0d9a-49ee-a46a-f4d9441a85a7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962730587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.962730587
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2893449413
Short name T26
Test name
Test status
Simulation time 68021122 ps
CPU time 0.73 seconds
Started Jan 21 07:30:58 PM PST 24
Finished Jan 21 07:31:03 PM PST 24
Peak memory 203312 kb
Host smart-48516170-6db8-488d-97db-bbf1c152e71e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893449413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.2893449413
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.261070139
Short name T1587
Test name
Test status
Simulation time 54537624 ps
CPU time 0.86 seconds
Started Jan 21 07:31:03 PM PST 24
Finished Jan 21 07:31:10 PM PST 24
Peak memory 203208 kb
Host smart-3dfe3002-f4f4-4eff-ba89-0dca2eec107f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261070139 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.261070139
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.3123406289
Short name T1545
Test name
Test status
Simulation time 18982645 ps
CPU time 0.7 seconds
Started Jan 21 07:30:58 PM PST 24
Finished Jan 21 07:31:02 PM PST 24
Peak memory 202392 kb
Host smart-82acd37c-2c77-413f-8a4e-8bee1f66e304
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123406289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.3123406289
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.120557784
Short name T1593
Test name
Test status
Simulation time 31097820 ps
CPU time 0.69 seconds
Started Jan 21 07:31:02 PM PST 24
Finished Jan 21 07:31:08 PM PST 24
Peak memory 203136 kb
Host smart-7f160f78-c9a1-4ad4-a59b-3d0aa11a6be7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120557784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.120557784
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2952965402
Short name T1574
Test name
Test status
Simulation time 39003181 ps
CPU time 0.81 seconds
Started Jan 21 07:31:05 PM PST 24
Finished Jan 21 07:31:13 PM PST 24
Peak memory 203220 kb
Host smart-0df285f1-1040-498b-bd08-4105535bb3c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952965402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.2952965402
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3147108438
Short name T1572
Test name
Test status
Simulation time 88572350 ps
CPU time 1.88 seconds
Started Jan 21 07:31:03 PM PST 24
Finished Jan 21 07:31:11 PM PST 24
Peak memory 203428 kb
Host smart-82957ba6-5270-4c6a-bbc0-418baf3f9575
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147108438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.3147108438
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3902359520
Short name T95
Test name
Test status
Simulation time 340822592 ps
CPU time 1.25 seconds
Started Jan 21 07:31:02 PM PST 24
Finished Jan 21 07:31:08 PM PST 24
Peak memory 203460 kb
Host smart-092c77f0-670a-4bc0-8fe4-627aaf040119
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902359520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.3902359520
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.2848145146
Short name T1534
Test name
Test status
Simulation time 21441124 ps
CPU time 0.61 seconds
Started Jan 21 07:32:04 PM PST 24
Finished Jan 21 07:32:07 PM PST 24
Peak memory 201204 kb
Host smart-f0c13315-3b2b-49bf-85ff-c0c5b032eaed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848145146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.2848145146
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.1290016684
Short name T1548
Test name
Test status
Simulation time 46601103 ps
CPU time 0.67 seconds
Started Jan 21 07:31:49 PM PST 24
Finished Jan 21 07:31:54 PM PST 24
Peak memory 203136 kb
Host smart-f2336a32-4137-4bed-9e86-4b3767d84471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290016684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1290016684
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.3798306524
Short name T142
Test name
Test status
Simulation time 30255021 ps
CPU time 0.7 seconds
Started Jan 21 07:31:55 PM PST 24
Finished Jan 21 07:31:58 PM PST 24
Peak memory 203176 kb
Host smart-ff6aebb0-3065-487f-8fb5-5aa061219013
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798306524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.3798306524
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.321083007
Short name T1605
Test name
Test status
Simulation time 212329363 ps
CPU time 0.64 seconds
Started Jan 21 07:31:52 PM PST 24
Finished Jan 21 07:31:56 PM PST 24
Peak memory 203196 kb
Host smart-cb2bfcbd-774e-4596-adf6-0111311fa33a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321083007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.321083007
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.3670676456
Short name T66
Test name
Test status
Simulation time 36977030 ps
CPU time 0.67 seconds
Started Jan 21 07:31:55 PM PST 24
Finished Jan 21 07:31:58 PM PST 24
Peak memory 202824 kb
Host smart-741da774-9fd8-4156-906d-b89b52179a2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670676456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.3670676456
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.2402029905
Short name T1571
Test name
Test status
Simulation time 20162614 ps
CPU time 0.68 seconds
Started Jan 21 07:31:53 PM PST 24
Finished Jan 21 07:31:57 PM PST 24
Peak memory 203144 kb
Host smart-c21a6496-f855-4fde-8961-2b6b89e80794
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402029905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2402029905
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.657240466
Short name T67
Test name
Test status
Simulation time 15435480 ps
CPU time 0.64 seconds
Started Jan 21 07:32:02 PM PST 24
Finished Jan 21 07:32:03 PM PST 24
Peak memory 203132 kb
Host smart-be613efa-b47f-4c39-ac9a-05a862238b34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657240466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.657240466
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.2279098575
Short name T24
Test name
Test status
Simulation time 117575617 ps
CPU time 0.67 seconds
Started Jan 21 07:31:58 PM PST 24
Finished Jan 21 07:32:02 PM PST 24
Peak memory 203112 kb
Host smart-9724627e-2c18-4412-8d7e-000577353981
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279098575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.2279098575
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.2158817154
Short name T1533
Test name
Test status
Simulation time 18224023 ps
CPU time 0.67 seconds
Started Jan 21 07:32:04 PM PST 24
Finished Jan 21 07:32:07 PM PST 24
Peak memory 203128 kb
Host smart-cdea131b-72f3-4ac5-ba87-11263632f38e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158817154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.2158817154
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.3599209046
Short name T1564
Test name
Test status
Simulation time 19575050 ps
CPU time 0.64 seconds
Started Jan 21 07:31:51 PM PST 24
Finished Jan 21 07:31:56 PM PST 24
Peak memory 203140 kb
Host smart-a0651085-780d-4c71-ab92-573eb40f8c39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599209046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.3599209046
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2691316505
Short name T1553
Test name
Test status
Simulation time 92045777 ps
CPU time 0.83 seconds
Started Jan 21 07:31:01 PM PST 24
Finished Jan 21 07:31:07 PM PST 24
Peak memory 203316 kb
Host smart-5b46f735-3f01-4272-9c42-812116517059
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691316505 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.2691316505
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.214318863
Short name T123
Test name
Test status
Simulation time 41892557 ps
CPU time 0.76 seconds
Started Jan 21 07:31:02 PM PST 24
Finished Jan 21 07:31:07 PM PST 24
Peak memory 203192 kb
Host smart-89230897-9a0d-4075-a2a8-0466c756ba6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214318863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.214318863
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.16558156
Short name T1610
Test name
Test status
Simulation time 22369814 ps
CPU time 0.66 seconds
Started Jan 21 07:31:02 PM PST 24
Finished Jan 21 07:31:07 PM PST 24
Peak memory 203100 kb
Host smart-c0e30a2b-871b-4d32-a6a2-670e94f8474e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16558156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.16558156
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1952683080
Short name T1588
Test name
Test status
Simulation time 82846959 ps
CPU time 1.04 seconds
Started Jan 21 07:31:03 PM PST 24
Finished Jan 21 07:31:10 PM PST 24
Peak memory 203472 kb
Host smart-a4c8e5f4-72b8-4417-99a5-44856d5144b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952683080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.1952683080
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1371713835
Short name T1552
Test name
Test status
Simulation time 89516101 ps
CPU time 2.15 seconds
Started Jan 21 07:31:02 PM PST 24
Finished Jan 21 07:31:09 PM PST 24
Peak memory 203480 kb
Host smart-35f7eefb-4ff0-4e1f-bf29-5b67b6f71c66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371713835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.1371713835
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1851130378
Short name T90
Test name
Test status
Simulation time 54619532 ps
CPU time 1.4 seconds
Started Jan 21 07:31:11 PM PST 24
Finished Jan 21 07:31:25 PM PST 24
Peak memory 203408 kb
Host smart-ec0d70a2-790a-4dfa-a78b-761ffa418c03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851130378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.1851130378
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.4266696589
Short name T20
Test name
Test status
Simulation time 40233374 ps
CPU time 0.79 seconds
Started Jan 21 07:31:11 PM PST 24
Finished Jan 21 07:31:24 PM PST 24
Peak memory 203280 kb
Host smart-3e7936bd-b6ca-4459-9ffc-e7ccff28e33e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266696589 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.4266696589
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1998163220
Short name T1612
Test name
Test status
Simulation time 111303253 ps
CPU time 0.67 seconds
Started Jan 21 07:31:07 PM PST 24
Finished Jan 21 07:31:15 PM PST 24
Peak memory 203240 kb
Host smart-43c7eb48-a235-49ad-b29c-efa662e69625
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998163220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.1998163220
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.2662630141
Short name T1623
Test name
Test status
Simulation time 19355284 ps
CPU time 0.71 seconds
Started Jan 21 07:31:08 PM PST 24
Finished Jan 21 07:31:16 PM PST 24
Peak memory 203176 kb
Host smart-2ada84b8-2aaa-4584-8b3d-d9d7452bf7a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662630141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2662630141
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3301212522
Short name T1618
Test name
Test status
Simulation time 121949087 ps
CPU time 0.87 seconds
Started Jan 21 07:31:12 PM PST 24
Finished Jan 21 07:31:24 PM PST 24
Peak memory 203224 kb
Host smart-c7e5f898-39e3-4265-a48b-70579fbb6ab2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301212522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.3301212522
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3843862249
Short name T1607
Test name
Test status
Simulation time 82301359 ps
CPU time 1.34 seconds
Started Jan 21 07:31:11 PM PST 24
Finished Jan 21 07:31:24 PM PST 24
Peak memory 203488 kb
Host smart-b3037749-a811-4cb5-95a3-108a85054643
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843862249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.3843862249
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3966193150
Short name T1569
Test name
Test status
Simulation time 47415612 ps
CPU time 1.34 seconds
Started Jan 21 07:31:11 PM PST 24
Finished Jan 21 07:31:25 PM PST 24
Peak memory 203440 kb
Host smart-0d34068a-6e13-4eec-a91c-6c65ad1e4697
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966193150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.3966193150
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.948230934
Short name T1554
Test name
Test status
Simulation time 23557504 ps
CPU time 1.06 seconds
Started Jan 21 07:31:07 PM PST 24
Finished Jan 21 07:31:16 PM PST 24
Peak memory 203316 kb
Host smart-cfbdf5dc-54d8-46a8-a515-1295ab48ae5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948230934 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.948230934
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2621221994
Short name T1591
Test name
Test status
Simulation time 25166336 ps
CPU time 0.75 seconds
Started Jan 21 07:31:11 PM PST 24
Finished Jan 21 07:31:24 PM PST 24
Peak memory 203204 kb
Host smart-dba90d1b-d1f4-4787-be37-b4eb069f26f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621221994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.2621221994
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.2813469790
Short name T1535
Test name
Test status
Simulation time 34773294 ps
CPU time 0.75 seconds
Started Jan 21 07:31:11 PM PST 24
Finished Jan 21 07:31:24 PM PST 24
Peak memory 203132 kb
Host smart-d8b409ce-2b5a-428d-ab12-1786270a79b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813469790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.2813469790
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2252019559
Short name T135
Test name
Test status
Simulation time 170935271 ps
CPU time 0.97 seconds
Started Jan 21 07:31:12 PM PST 24
Finished Jan 21 07:31:24 PM PST 24
Peak memory 203088 kb
Host smart-2ebe17e0-e3f2-40f1-93ec-51da62098e58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252019559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.2252019559
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3602103343
Short name T112
Test name
Test status
Simulation time 299338325 ps
CPU time 2.3 seconds
Started Jan 21 07:31:08 PM PST 24
Finished Jan 21 07:31:17 PM PST 24
Peak memory 203484 kb
Host smart-69392cf0-1fe3-4ad1-ba39-452ff75d0284
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602103343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.3602103343
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1632090220
Short name T76
Test name
Test status
Simulation time 167341189 ps
CPU time 1.19 seconds
Started Jan 21 07:31:07 PM PST 24
Finished Jan 21 07:31:16 PM PST 24
Peak memory 203476 kb
Host smart-19b8355b-1065-4d0a-996c-7bb5f98494c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632090220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.1632090220
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3103514712
Short name T1581
Test name
Test status
Simulation time 78384421 ps
CPU time 1.11 seconds
Started Jan 21 07:31:10 PM PST 24
Finished Jan 21 07:31:21 PM PST 24
Peak memory 203460 kb
Host smart-b6d8123e-d965-48ab-8dc9-77de4799744b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103514712 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.3103514712
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2206751767
Short name T1546
Test name
Test status
Simulation time 48876007 ps
CPU time 0.66 seconds
Started Jan 21 07:31:10 PM PST 24
Finished Jan 21 07:31:20 PM PST 24
Peak memory 202344 kb
Host smart-0b374bde-6066-4544-963f-dca64cde8dd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206751767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.2206751767
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.1676575158
Short name T1619
Test name
Test status
Simulation time 20331090 ps
CPU time 0.72 seconds
Started Jan 21 07:31:10 PM PST 24
Finished Jan 21 07:31:21 PM PST 24
Peak memory 203140 kb
Host smart-e681ef36-1883-4e73-8f78-3897ed3ae96d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676575158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1676575158
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.547974372
Short name T1556
Test name
Test status
Simulation time 48236786 ps
CPU time 2.46 seconds
Started Jan 21 07:31:10 PM PST 24
Finished Jan 21 07:31:24 PM PST 24
Peak memory 203492 kb
Host smart-e94943e8-fe85-43ce-8803-58f1007e6353
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547974372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.547974372
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.818619882
Short name T1560
Test name
Test status
Simulation time 230492571 ps
CPU time 1.36 seconds
Started Jan 21 07:31:13 PM PST 24
Finished Jan 21 07:31:25 PM PST 24
Peak memory 203408 kb
Host smart-faa17223-cb34-4b3f-a76c-64d0fe65d660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818619882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.818619882
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3661677080
Short name T1620
Test name
Test status
Simulation time 54406083 ps
CPU time 1.29 seconds
Started Jan 21 07:31:13 PM PST 24
Finished Jan 21 07:31:26 PM PST 24
Peak memory 203600 kb
Host smart-b924e9b0-3d9f-47f6-9da0-394f3d59fe7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661677080 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.3661677080
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.4019921610
Short name T1606
Test name
Test status
Simulation time 50356003 ps
CPU time 0.64 seconds
Started Jan 21 07:31:12 PM PST 24
Finished Jan 21 07:31:24 PM PST 24
Peak memory 202372 kb
Host smart-e7b74444-4b5f-4981-89b8-9af426cdeac9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019921610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.4019921610
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.2002299893
Short name T1555
Test name
Test status
Simulation time 48775759 ps
CPU time 0.65 seconds
Started Jan 21 07:31:15 PM PST 24
Finished Jan 21 07:31:29 PM PST 24
Peak memory 203148 kb
Host smart-f188da27-b817-4e0c-a91d-2d4ed9f27df0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002299893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2002299893
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3250133082
Short name T125
Test name
Test status
Simulation time 20712286 ps
CPU time 0.75 seconds
Started Jan 21 07:31:23 PM PST 24
Finished Jan 21 07:31:33 PM PST 24
Peak memory 203176 kb
Host smart-246184de-aaaf-4d28-af46-b0854fc4427f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250133082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.3250133082
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.3774472275
Short name T1613
Test name
Test status
Simulation time 462565340 ps
CPU time 2.76 seconds
Started Jan 21 07:31:15 PM PST 24
Finished Jan 21 07:31:29 PM PST 24
Peak memory 203584 kb
Host smart-dbe7f4e6-882a-463a-8b16-55611f7c8b07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774472275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.3774472275
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3106795097
Short name T93
Test name
Test status
Simulation time 428792361 ps
CPU time 2.09 seconds
Started Jan 21 07:31:13 PM PST 24
Finished Jan 21 07:31:27 PM PST 24
Peak memory 203476 kb
Host smart-979c2639-d70b-4061-8204-ab917eb94e8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106795097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.3106795097
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.3251663951
Short name T832
Test name
Test status
Simulation time 16293688 ps
CPU time 0.63 seconds
Started Jan 21 08:33:52 PM PST 24
Finished Jan 21 08:33:54 PM PST 24
Peak memory 201996 kb
Host smart-94d41d88-d7b7-462b-8239-a59525dc34c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251663951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.3251663951
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.1644437054
Short name T64
Test name
Test status
Simulation time 53588034 ps
CPU time 1.46 seconds
Started Jan 21 08:17:07 PM PST 24
Finished Jan 21 08:17:10 PM PST 24
Peak memory 210748 kb
Host smart-1e4eb1d4-6723-4246-9d8f-c809bce4ace5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644437054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.1644437054
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.3586924969
Short name T746
Test name
Test status
Simulation time 2178397000 ps
CPU time 16.88 seconds
Started Jan 21 08:17:05 PM PST 24
Finished Jan 21 08:17:25 PM PST 24
Peak memory 261056 kb
Host smart-f09028c7-35c0-4fc0-9c3c-e04f26601ca4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586924969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.3586924969
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.4107056172
Short name T478
Test name
Test status
Simulation time 5903374635 ps
CPU time 101.79 seconds
Started Jan 21 08:17:09 PM PST 24
Finished Jan 21 08:18:52 PM PST 24
Peak memory 824700 kb
Host smart-f3f26273-e72a-4d3c-a92c-811d2de7da0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107056172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.4107056172
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.173844537
Short name T258
Test name
Test status
Simulation time 20799287566 ps
CPU time 708.64 seconds
Started Jan 21 08:17:02 PM PST 24
Finished Jan 21 08:28:53 PM PST 24
Peak memory 1402812 kb
Host smart-757c6d19-73f2-409c-ac41-69a8a6e91521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173844537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.173844537
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.893500631
Short name T249
Test name
Test status
Simulation time 102452048 ps
CPU time 0.94 seconds
Started Jan 21 08:42:44 PM PST 24
Finished Jan 21 08:42:46 PM PST 24
Peak memory 202328 kb
Host smart-c41c4fac-3588-49d3-8d44-698e0e3f72b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893500631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt
.893500631
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.1923237979
Short name T291
Test name
Test status
Simulation time 12184704822 ps
CPU time 404.87 seconds
Started Jan 21 08:17:03 PM PST 24
Finished Jan 21 08:23:51 PM PST 24
Peak memory 1676852 kb
Host smart-d3bd8cfb-0a8a-45f1-9d27-8a7fbad0c1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923237979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.1923237979
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.3663383043
Short name T1387
Test name
Test status
Simulation time 2885954644 ps
CPU time 74.4 seconds
Started Jan 21 08:17:26 PM PST 24
Finished Jan 21 08:18:42 PM PST 24
Peak memory 231080 kb
Host smart-318779a6-d45b-4f86-892d-d3af89533e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663383043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.3663383043
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.3040299575
Short name T887
Test name
Test status
Simulation time 50460845 ps
CPU time 0.67 seconds
Started Jan 21 08:17:03 PM PST 24
Finished Jan 21 08:17:07 PM PST 24
Peak memory 201524 kb
Host smart-7b2e7b99-9652-4c0d-ae8c-c616f2904e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040299575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.3040299575
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.3397587756
Short name T1453
Test name
Test status
Simulation time 2995710322 ps
CPU time 130.58 seconds
Started Jan 21 08:17:05 PM PST 24
Finished Jan 21 08:19:18 PM PST 24
Peak memory 219008 kb
Host smart-887b2d03-5e2a-4af6-82a9-932c16190ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397587756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.3397587756
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_rx_oversample.1712168686
Short name T1478
Test name
Test status
Simulation time 10713950016 ps
CPU time 253.3 seconds
Started Jan 21 08:50:44 PM PST 24
Finished Jan 21 08:55:22 PM PST 24
Peak memory 295608 kb
Host smart-74be12e5-224e-4fa2-88c9-ef40a57a0e74
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712168686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_rx_oversample.
1712168686
Directory /workspace/0.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.2578794636
Short name T717
Test name
Test status
Simulation time 1530871853 ps
CPU time 85.72 seconds
Started Jan 21 08:16:57 PM PST 24
Finished Jan 21 08:18:25 PM PST 24
Peak memory 233312 kb
Host smart-c0f5e457-e2e3-4e36-a6e8-18567022859d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578794636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.2578794636
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.1712582558
Short name T1264
Test name
Test status
Simulation time 3182968787 ps
CPU time 12.86 seconds
Started Jan 21 08:50:11 PM PST 24
Finished Jan 21 08:50:47 PM PST 24
Peak memory 218856 kb
Host smart-57c50852-4376-4ea2-8c2d-1b40ed410d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712582558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.1712582558
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.3195248902
Short name T225
Test name
Test status
Simulation time 1577011748 ps
CPU time 5.7 seconds
Started Jan 21 08:17:25 PM PST 24
Finished Jan 21 08:17:31 PM PST 24
Peak memory 202524 kb
Host smart-1aede311-e781-44a9-8a14-5d49c2fcc499
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195248902 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.3195248902
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.1664546138
Short name T993
Test name
Test status
Simulation time 10170659723 ps
CPU time 28.58 seconds
Started Jan 21 08:17:20 PM PST 24
Finished Jan 21 08:17:50 PM PST 24
Peak memory 358564 kb
Host smart-bd1b660e-c2a1-41db-b858-96349fa43b5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664546138 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.1664546138
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.1087535988
Short name T203
Test name
Test status
Simulation time 10469112797 ps
CPU time 17.48 seconds
Started Jan 21 08:17:23 PM PST 24
Finished Jan 21 08:17:41 PM PST 24
Peak memory 349340 kb
Host smart-894838f5-9516-4f57-89ef-acecc9bc733f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087535988 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.1087535988
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.2629035433
Short name T689
Test name
Test status
Simulation time 521258262 ps
CPU time 2.72 seconds
Started Jan 21 08:17:21 PM PST 24
Finished Jan 21 08:17:25 PM PST 24
Peak memory 202536 kb
Host smart-b9573003-3058-4e36-a0e8-02ced27c1dca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629035433 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.2629035433
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.41760740
Short name T657
Test name
Test status
Simulation time 1906328060 ps
CPU time 4.11 seconds
Started Jan 21 08:17:14 PM PST 24
Finished Jan 21 08:17:19 PM PST 24
Peak memory 202536 kb
Host smart-67e434fe-802a-4841-8566-7b50f7cd8ff8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41760740 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_intr_smoke.41760740
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.1375270668
Short name T544
Test name
Test status
Simulation time 20017951493 ps
CPU time 313.72 seconds
Started Jan 21 08:17:14 PM PST 24
Finished Jan 21 08:22:29 PM PST 24
Peak memory 2390544 kb
Host smart-0c102b02-75d3-4e27-9876-64728c88b398
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375270668 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.1375270668
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_perf.351584189
Short name T1165
Test name
Test status
Simulation time 860196685 ps
CPU time 4.83 seconds
Started Jan 21 08:17:23 PM PST 24
Finished Jan 21 08:17:29 PM PST 24
Peak memory 202592 kb
Host smart-f78be842-cdfa-43cc-b64a-9e634d3d5831
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351584189 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.i2c_target_perf.351584189
Directory /workspace/0.i2c_target_perf/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.2386657464
Short name T562
Test name
Test status
Simulation time 1024993976 ps
CPU time 28.18 seconds
Started Jan 21 08:17:09 PM PST 24
Finished Jan 21 08:17:39 PM PST 24
Peak memory 202576 kb
Host smart-4a91430c-e1ec-46b4-8b56-1f83f2961fc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386657464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.2386657464
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.1461702819
Short name T661
Test name
Test status
Simulation time 625183633 ps
CPU time 11.7 seconds
Started Jan 21 08:55:24 PM PST 24
Finished Jan 21 08:55:50 PM PST 24
Peak memory 202584 kb
Host smart-a95273c5-b3fc-4a9f-a45e-324ecb4f329d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461702819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.1461702819
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.2877011454
Short name T1227
Test name
Test status
Simulation time 66275110477 ps
CPU time 442.4 seconds
Started Jan 21 08:17:07 PM PST 24
Finished Jan 21 08:24:31 PM PST 24
Peak memory 2498884 kb
Host smart-c7109bcd-1e4a-44c3-8679-2e4b19d87f8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877011454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.2877011454
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.1120177702
Short name T1093
Test name
Test status
Simulation time 25784952092 ps
CPU time 751.65 seconds
Started Jan 21 08:17:12 PM PST 24
Finished Jan 21 08:29:46 PM PST 24
Peak memory 1719880 kb
Host smart-356eedf6-357b-49e3-a11f-c9ca47ef8cb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120177702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.1120177702
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.2670738993
Short name T1148
Test name
Test status
Simulation time 8856914695 ps
CPU time 8.76 seconds
Started Jan 21 08:17:16 PM PST 24
Finished Jan 21 08:17:26 PM PST 24
Peak memory 202600 kb
Host smart-e7ccbd6a-a41e-4961-be5d-e996a949dd54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670738993 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.2670738993
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_ovf.3978888670
Short name T468
Test name
Test status
Simulation time 3403385631 ps
CPU time 194.52 seconds
Started Jan 21 08:17:13 PM PST 24
Finished Jan 21 08:20:29 PM PST 24
Peak memory 463416 kb
Host smart-55d3cdb9-e02d-41a1-abc3-77f8c48e0ae5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978888670 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_tx_ovf.3978888670
Directory /workspace/0.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/0.i2c_target_unexp_stop.1799546614
Short name T1394
Test name
Test status
Simulation time 1226475521 ps
CPU time 6.1 seconds
Started Jan 21 08:17:21 PM PST 24
Finished Jan 21 08:17:28 PM PST 24
Peak memory 203852 kb
Host smart-946b2547-bc9f-484e-a548-65d0f851c640
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799546614 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.i2c_target_unexp_stop.1799546614
Directory /workspace/0.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/1.i2c_alert_test.23743834
Short name T325
Test name
Test status
Simulation time 15703290 ps
CPU time 0.66 seconds
Started Jan 21 08:18:10 PM PST 24
Finished Jan 21 08:18:12 PM PST 24
Peak memory 201112 kb
Host smart-9588fbf8-d8de-4e14-9014-b8d712560b8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23743834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.23743834
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.1178498628
Short name T47
Test name
Test status
Simulation time 201196252 ps
CPU time 1.53 seconds
Started Jan 21 08:17:40 PM PST 24
Finished Jan 21 08:17:42 PM PST 24
Peak memory 210768 kb
Host smart-21b223cd-86b5-4f27-ae15-5bc402b19ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178498628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.1178498628
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.2065986274
Short name T1446
Test name
Test status
Simulation time 1015012400 ps
CPU time 5.9 seconds
Started Jan 21 08:17:33 PM PST 24
Finished Jan 21 08:17:40 PM PST 24
Peak memory 263040 kb
Host smart-71054db8-8cb6-4623-953a-c2dff00f3c4a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065986274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.2065986274
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.2952055523
Short name T621
Test name
Test status
Simulation time 2917956298 ps
CPU time 281.09 seconds
Started Jan 21 08:17:39 PM PST 24
Finished Jan 21 08:22:21 PM PST 24
Peak memory 927776 kb
Host smart-3a979533-f5f4-4779-8289-65785913f865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952055523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.2952055523
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.2942530216
Short name T1367
Test name
Test status
Simulation time 34179684882 ps
CPU time 306.11 seconds
Started Jan 21 08:17:30 PM PST 24
Finished Jan 21 08:22:38 PM PST 24
Peak memory 1399632 kb
Host smart-023379b4-807e-4949-8ded-482949af4c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942530216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.2942530216
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.1364684666
Short name T1391
Test name
Test status
Simulation time 255390918 ps
CPU time 1.07 seconds
Started Jan 21 08:17:31 PM PST 24
Finished Jan 21 08:17:33 PM PST 24
Peak memory 202464 kb
Host smart-c4eb8192-aaf0-49be-9218-0a4e0863f372
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364684666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.1364684666
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.15896554
Short name T771
Test name
Test status
Simulation time 732116501 ps
CPU time 4.61 seconds
Started Jan 21 08:17:37 PM PST 24
Finished Jan 21 08:17:42 PM PST 24
Peak memory 202544 kb
Host smart-2b2eb4e8-c257-43cf-9be2-d10b749ee6ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15896554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.15896554
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.398778350
Short name T797
Test name
Test status
Simulation time 13513135492 ps
CPU time 276.51 seconds
Started Jan 21 08:17:30 PM PST 24
Finished Jan 21 08:22:08 PM PST 24
Peak memory 1351812 kb
Host smart-5f4825c0-6c4e-4714-91c8-e8a4b4e718fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398778350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.398778350
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.3470854816
Short name T1437
Test name
Test status
Simulation time 3029802308 ps
CPU time 49.14 seconds
Started Jan 21 08:18:00 PM PST 24
Finished Jan 21 08:18:51 PM PST 24
Peak memory 296248 kb
Host smart-aba924c7-4c1f-4fbc-8493-831933da3e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470854816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.3470854816
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_perf.1405148178
Short name T144
Test name
Test status
Simulation time 5702594058 ps
CPU time 30.66 seconds
Started Jan 21 08:17:35 PM PST 24
Finished Jan 21 08:18:07 PM PST 24
Peak memory 218936 kb
Host smart-2ab7cea5-b30e-4a0d-8aeb-ce91808aae62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405148178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.1405148178
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_rx_oversample.4015553367
Short name T1291
Test name
Test status
Simulation time 3913802276 ps
CPU time 118.31 seconds
Started Jan 21 08:17:30 PM PST 24
Finished Jan 21 08:19:30 PM PST 24
Peak memory 304468 kb
Host smart-aa7ef7ce-fd74-4862-a7ea-f67f0944b28c
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015553367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_rx_oversample.
4015553367
Directory /workspace/1.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.2927123824
Short name T264
Test name
Test status
Simulation time 2026404307 ps
CPU time 59.15 seconds
Started Jan 21 08:17:27 PM PST 24
Finished Jan 21 08:18:28 PM PST 24
Peak memory 266036 kb
Host smart-8d301872-ae2f-4e9f-8ca2-bee3fc2b73af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927123824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.2927123824
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.1890028287
Short name T1073
Test name
Test status
Simulation time 882570761 ps
CPU time 15.37 seconds
Started Jan 21 08:17:37 PM PST 24
Finished Jan 21 08:17:54 PM PST 24
Peak memory 210964 kb
Host smart-56a8e084-9990-48e9-8f94-e4cf70737def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890028287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.1890028287
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.4001013097
Short name T84
Test name
Test status
Simulation time 301910906 ps
CPU time 0.96 seconds
Started Jan 21 08:18:08 PM PST 24
Finished Jan 21 08:18:12 PM PST 24
Peak memory 219404 kb
Host smart-e9303c41-529c-4574-9d1b-8b7b71a89200
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001013097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.4001013097
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.635572944
Short name T401
Test name
Test status
Simulation time 2583962767 ps
CPU time 3.24 seconds
Started Jan 21 08:17:56 PM PST 24
Finished Jan 21 08:18:00 PM PST 24
Peak memory 202624 kb
Host smart-d60e9c23-937f-4346-a50e-9659d170c042
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635572944 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.635572944
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.3354346183
Short name T681
Test name
Test status
Simulation time 10060896034 ps
CPU time 58.26 seconds
Started Jan 21 09:23:58 PM PST 24
Finished Jan 21 09:25:07 PM PST 24
Peak memory 496388 kb
Host smart-98585cdd-f91c-40d8-838e-f249519228d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354346183 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.3354346183
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.2195110260
Short name T722
Test name
Test status
Simulation time 10144896723 ps
CPU time 64.26 seconds
Started Jan 21 08:17:52 PM PST 24
Finished Jan 21 08:18:57 PM PST 24
Peak memory 494936 kb
Host smart-40cc5c54-9bd5-4ab3-9ff0-a8a2251d502f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195110260 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.2195110260
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.1368948186
Short name T54
Test name
Test status
Simulation time 4202359056 ps
CPU time 4.68 seconds
Started Jan 21 09:10:34 PM PST 24
Finished Jan 21 09:10:58 PM PST 24
Peak memory 202832 kb
Host smart-87cd3522-b1f3-4b3f-a82a-9d616808d99c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368948186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.1368948186
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.790427528
Short name T161
Test name
Test status
Simulation time 430567193 ps
CPU time 2.17 seconds
Started Jan 21 08:17:52 PM PST 24
Finished Jan 21 08:17:55 PM PST 24
Peak memory 202544 kb
Host smart-8f94a6ca-ffe5-48f1-8732-bbeb7d537fca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790427528 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.i2c_target_hrst.790427528
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.4225613910
Short name T334
Test name
Test status
Simulation time 2951993307 ps
CPU time 6.43 seconds
Started Jan 21 08:51:00 PM PST 24
Finished Jan 21 08:51:45 PM PST 24
Peak memory 209128 kb
Host smart-4ba29c3c-526e-4d8e-ad12-a55c3acf29a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225613910 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.4225613910
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.3679933142
Short name T1219
Test name
Test status
Simulation time 6263158242 ps
CPU time 12.97 seconds
Started Jan 21 08:17:48 PM PST 24
Finished Jan 21 08:18:02 PM PST 24
Peak memory 427468 kb
Host smart-70856420-a63d-4d01-89c3-ba8724301f24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679933142 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.3679933142
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_perf.1117251052
Short name T443
Test name
Test status
Simulation time 2899560781 ps
CPU time 5.49 seconds
Started Jan 21 08:17:57 PM PST 24
Finished Jan 21 08:18:04 PM PST 24
Peak memory 202688 kb
Host smart-3d00794c-9cb9-4b53-bc0f-31650e8aed7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117251052 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_perf.1117251052
Directory /workspace/1.i2c_target_perf/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.3953319569
Short name T1021
Test name
Test status
Simulation time 1322607963 ps
CPU time 16.06 seconds
Started Jan 21 08:17:43 PM PST 24
Finished Jan 21 08:18:01 PM PST 24
Peak memory 202512 kb
Host smart-813947be-6e3d-4991-ab3d-a4846500ed1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953319569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.3953319569
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_all.761080091
Short name T15
Test name
Test status
Simulation time 47491287864 ps
CPU time 2038.3 seconds
Started Jan 21 08:17:55 PM PST 24
Finished Jan 21 08:51:54 PM PST 24
Peak memory 6573004 kb
Host smart-7c5385c6-591f-46e7-862e-baa4d685a37f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761080091 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.i2c_target_stress_all.761080091
Directory /workspace/1.i2c_target_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.848091231
Short name T1513
Test name
Test status
Simulation time 1366105111 ps
CPU time 22.05 seconds
Started Jan 21 08:17:42 PM PST 24
Finished Jan 21 08:18:06 PM PST 24
Peak memory 208576 kb
Host smart-223e4394-65ce-46c0-baf2-516d14dc9650
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848091231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_
target_stress_rd.848091231
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.3803935598
Short name T366
Test name
Test status
Simulation time 62446855157 ps
CPU time 627.26 seconds
Started Jan 21 09:01:31 PM PST 24
Finished Jan 21 09:12:18 PM PST 24
Peak memory 3809404 kb
Host smart-8eb0e7c1-7123-4d7d-9b3b-d3ecf9d18711
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803935598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.3803935598
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.3095935185
Short name T1171
Test name
Test status
Simulation time 12053018025 ps
CPU time 539 seconds
Started Jan 21 08:17:42 PM PST 24
Finished Jan 21 08:26:43 PM PST 24
Peak memory 2889728 kb
Host smart-55685bd3-dd96-420d-9485-7125cf012995
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095935185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.3095935185
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.1636879155
Short name T241
Test name
Test status
Simulation time 6116931046 ps
CPU time 6.9 seconds
Started Jan 21 08:17:49 PM PST 24
Finished Jan 21 08:17:57 PM PST 24
Peak memory 207572 kb
Host smart-de2001e2-04dc-49ac-9a18-f17e09f35777
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636879155 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.1636879155
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_tx_ovf.1284801452
Short name T1362
Test name
Test status
Simulation time 2405139373 ps
CPU time 62.44 seconds
Started Jan 21 09:56:11 PM PST 24
Finished Jan 21 09:57:22 PM PST 24
Peak memory 233984 kb
Host smart-51dd7ef9-28d2-4dd8-9f38-62b506ed15f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284801452 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_tx_ovf.1284801452
Directory /workspace/1.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/1.i2c_target_unexp_stop.3777887360
Short name T326
Test name
Test status
Simulation time 5987033567 ps
CPU time 8.66 seconds
Started Jan 21 08:17:51 PM PST 24
Finished Jan 21 08:18:00 PM PST 24
Peak memory 202656 kb
Host smart-95062bde-5199-4d99-ad67-a391b7168969
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777887360 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.i2c_target_unexp_stop.3777887360
Directory /workspace/1.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.4042513445
Short name T1136
Test name
Test status
Simulation time 148266040 ps
CPU time 1.26 seconds
Started Jan 21 08:23:07 PM PST 24
Finished Jan 21 08:23:09 PM PST 24
Peak memory 218908 kb
Host smart-14336d00-4849-4733-971e-070f61b2cb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042513445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.4042513445
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.2094608575
Short name T903
Test name
Test status
Simulation time 937228855 ps
CPU time 8.96 seconds
Started Jan 21 08:23:00 PM PST 24
Finished Jan 21 08:23:10 PM PST 24
Peak memory 305592 kb
Host smart-7d2d928b-8c5b-454d-87a0-8b6f6d138cb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094608575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.2094608575
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.4142420585
Short name T921
Test name
Test status
Simulation time 17005911509 ps
CPU time 130.93 seconds
Started Jan 21 08:23:02 PM PST 24
Finished Jan 21 08:25:14 PM PST 24
Peak memory 1010084 kb
Host smart-896d21fd-1088-40f1-9149-aa6c49f52ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142420585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.4142420585
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.60212545
Short name T177
Test name
Test status
Simulation time 34430659600 ps
CPU time 459.69 seconds
Started Jan 21 08:22:56 PM PST 24
Finished Jan 21 08:30:38 PM PST 24
Peak memory 1609772 kb
Host smart-d5b94bb2-2db3-40cc-b3f3-508411ccbf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60212545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.60212545
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.880644637
Short name T675
Test name
Test status
Simulation time 230891383 ps
CPU time 1.01 seconds
Started Jan 21 09:21:07 PM PST 24
Finished Jan 21 09:21:12 PM PST 24
Peak memory 202316 kb
Host smart-f264d383-00f1-47cf-b60d-fd1fd6275495
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880644637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fm
t.880644637
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.3658349900
Short name T1164
Test name
Test status
Simulation time 181865790 ps
CPU time 4.82 seconds
Started Jan 21 08:23:03 PM PST 24
Finished Jan 21 08:23:09 PM PST 24
Peak memory 234344 kb
Host smart-464e5193-ee98-4061-bed3-7bc995521686
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658349900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.3658349900
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.159494800
Short name T494
Test name
Test status
Simulation time 20588523623 ps
CPU time 425.52 seconds
Started Jan 21 08:22:56 PM PST 24
Finished Jan 21 08:30:04 PM PST 24
Peak memory 1178424 kb
Host smart-9e39517a-c9a5-40b2-a072-1675b557d740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159494800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.159494800
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.2704335081
Short name T627
Test name
Test status
Simulation time 8531921562 ps
CPU time 53.79 seconds
Started Jan 21 08:23:16 PM PST 24
Finished Jan 21 08:24:11 PM PST 24
Peak memory 290572 kb
Host smart-9febbaa4-d70d-4062-a370-409b83e54920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704335081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.2704335081
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.662298123
Short name T835
Test name
Test status
Simulation time 19003805 ps
CPU time 0.66 seconds
Started Jan 21 08:22:55 PM PST 24
Finished Jan 21 08:22:57 PM PST 24
Peak memory 201544 kb
Host smart-9cf69fa7-4816-40a4-b396-0bfe3f0f594d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662298123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.662298123
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.4171494417
Short name T413
Test name
Test status
Simulation time 28283847868 ps
CPU time 495.09 seconds
Started Jan 21 08:43:33 PM PST 24
Finished Jan 21 08:51:49 PM PST 24
Peak memory 210744 kb
Host smart-da2c1bf4-d1dd-45f1-a1c0-5651112eeb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171494417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.4171494417
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_rx_oversample.3003147479
Short name T1097
Test name
Test status
Simulation time 2970174013 ps
CPU time 321.84 seconds
Started Jan 21 08:22:56 PM PST 24
Finished Jan 21 08:28:19 PM PST 24
Peak memory 324376 kb
Host smart-58ad7d0b-9699-401f-8fbe-1f1046feadc9
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003147479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_rx_oversample
.3003147479
Directory /workspace/10.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.3805274301
Short name T932
Test name
Test status
Simulation time 1741615701 ps
CPU time 49.88 seconds
Started Jan 21 08:22:49 PM PST 24
Finished Jan 21 08:23:40 PM PST 24
Peak memory 293092 kb
Host smart-1d3f5834-beb7-4857-8eda-a9bcb1810146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805274301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.3805274301
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.570603429
Short name T926
Test name
Test status
Simulation time 34929231542 ps
CPU time 790.12 seconds
Started Jan 21 08:23:05 PM PST 24
Finished Jan 21 08:36:16 PM PST 24
Peak memory 1051560 kb
Host smart-962992ff-6034-4f3d-973e-9ccb7601f87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570603429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.570603429
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.1122789240
Short name T626
Test name
Test status
Simulation time 726554072 ps
CPU time 14.34 seconds
Started Jan 21 08:23:04 PM PST 24
Finished Jan 21 08:23:19 PM PST 24
Peak memory 216996 kb
Host smart-31a94d8c-4506-46e3-9f9e-838e78d56fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122789240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.1122789240
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.1097116704
Short name T1457
Test name
Test status
Simulation time 1122846830 ps
CPU time 4.89 seconds
Started Jan 21 08:23:16 PM PST 24
Finished Jan 21 08:23:22 PM PST 24
Peak memory 202532 kb
Host smart-02a95320-e45c-4f29-aea2-1bf030166d5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097116704 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.1097116704
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.3250598470
Short name T679
Test name
Test status
Simulation time 10103142939 ps
CPU time 11.09 seconds
Started Jan 21 08:23:14 PM PST 24
Finished Jan 21 08:23:26 PM PST 24
Peak memory 290304 kb
Host smart-d1800a4e-c0c4-41e0-ae0c-3dd13d3e36ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250598470 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.3250598470
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.244152662
Short name T788
Test name
Test status
Simulation time 1490234484 ps
CPU time 2.09 seconds
Started Jan 21 08:23:16 PM PST 24
Finished Jan 21 08:23:19 PM PST 24
Peak memory 202564 kb
Host smart-a40125d5-a403-487f-8a08-165c68c6d4c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244152662 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.i2c_target_hrst.244152662
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.648521976
Short name T1411
Test name
Test status
Simulation time 3082756484 ps
CPU time 4.54 seconds
Started Jan 21 08:48:11 PM PST 24
Finished Jan 21 08:48:35 PM PST 24
Peak memory 202692 kb
Host smart-83992abb-27ee-4c62-b072-05336f5ba170
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648521976 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_intr_smoke.648521976
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.3663446969
Short name T396
Test name
Test status
Simulation time 16705651745 ps
CPU time 159.31 seconds
Started Jan 21 08:23:07 PM PST 24
Finished Jan 21 08:25:47 PM PST 24
Peak memory 1527240 kb
Host smart-f8571b49-64dd-4824-99d7-4442aae96326
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663446969 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.3663446969
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_perf.3720579331
Short name T1044
Test name
Test status
Simulation time 677232836 ps
CPU time 3.59 seconds
Started Jan 21 08:23:16 PM PST 24
Finished Jan 21 08:23:21 PM PST 24
Peak memory 202544 kb
Host smart-eb1ec523-e455-4a21-bcea-4e2cdcea21dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720579331 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_perf.3720579331
Directory /workspace/10.i2c_target_perf/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.2437545711
Short name T666
Test name
Test status
Simulation time 7845395143 ps
CPU time 18.62 seconds
Started Jan 21 08:23:06 PM PST 24
Finished Jan 21 08:23:25 PM PST 24
Peak memory 202624 kb
Host smart-44fac907-9fd2-4905-a4a8-e7aef9dee764
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437545711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.2437545711
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.3029676806
Short name T1174
Test name
Test status
Simulation time 6734639596 ps
CPU time 29.58 seconds
Started Jan 21 08:23:11 PM PST 24
Finished Jan 21 08:23:42 PM PST 24
Peak memory 232372 kb
Host smart-ea30aa49-101c-40b3-b2c5-fcd3914e2c6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029676806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.3029676806
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.4242735577
Short name T409
Test name
Test status
Simulation time 17466681465 ps
CPU time 101.63 seconds
Started Jan 21 08:23:06 PM PST 24
Finished Jan 21 08:24:49 PM PST 24
Peak memory 1729224 kb
Host smart-1c5550e3-bc80-4be0-bad3-1ae352f986af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242735577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.4242735577
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.2665588834
Short name T527
Test name
Test status
Simulation time 16553949321 ps
CPU time 2234.71 seconds
Started Jan 21 08:23:07 PM PST 24
Finished Jan 21 09:00:22 PM PST 24
Peak memory 3957024 kb
Host smart-6d32144e-fa44-4107-8323-e2b7d3ff0d3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665588834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.2665588834
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.442348907
Short name T1166
Test name
Test status
Simulation time 7853871539 ps
CPU time 8.23 seconds
Started Jan 21 08:23:06 PM PST 24
Finished Jan 21 08:23:15 PM PST 24
Peak memory 213392 kb
Host smart-cae530e5-a8a0-4cb5-89a3-1cf29aaeb091
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442348907 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_timeout.442348907
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_tx_ovf.2180703972
Short name T507
Test name
Test status
Simulation time 2196280039 ps
CPU time 35.63 seconds
Started Jan 21 08:23:07 PM PST 24
Finished Jan 21 08:23:43 PM PST 24
Peak memory 213100 kb
Host smart-284a5028-6c6b-400a-89d5-760f34de5466
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180703972 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_tx_ovf.2180703972
Directory /workspace/10.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/10.i2c_target_unexp_stop.3440113579
Short name T880
Test name
Test status
Simulation time 13077109883 ps
CPU time 8.14 seconds
Started Jan 21 08:23:11 PM PST 24
Finished Jan 21 08:23:20 PM PST 24
Peak memory 202600 kb
Host smart-84493ebe-3cd6-4114-a915-1ca83d4e301d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440113579 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.i2c_target_unexp_stop.3440113579
Directory /workspace/10.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/11.i2c_alert_test.3650596857
Short name T1313
Test name
Test status
Simulation time 36227758 ps
CPU time 0.61 seconds
Started Jan 21 08:23:43 PM PST 24
Finished Jan 21 08:23:44 PM PST 24
Peak memory 201328 kb
Host smart-38f0498f-68dc-475f-9d6c-121864e6fa72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650596857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.3650596857
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.793413228
Short name T1308
Test name
Test status
Simulation time 44565289 ps
CPU time 1.33 seconds
Started Jan 21 08:23:42 PM PST 24
Finished Jan 21 08:23:44 PM PST 24
Peak memory 218812 kb
Host smart-50215a03-4f0d-4e53-be95-5b8e136cdabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793413228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.793413228
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.1975375880
Short name T850
Test name
Test status
Simulation time 755983577 ps
CPU time 17.44 seconds
Started Jan 21 08:23:24 PM PST 24
Finished Jan 21 08:23:42 PM PST 24
Peak memory 372392 kb
Host smart-77ba7bed-cac8-48ac-b161-27cee025966d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975375880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.1975375880
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.664272251
Short name T606
Test name
Test status
Simulation time 6219365287 ps
CPU time 144.05 seconds
Started Jan 21 08:23:26 PM PST 24
Finished Jan 21 08:25:51 PM PST 24
Peak memory 931784 kb
Host smart-c348d2f0-d8d2-4a76-8514-3cde11859457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664272251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.664272251
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.3148768328
Short name T1420
Test name
Test status
Simulation time 70135789057 ps
CPU time 343.6 seconds
Started Jan 21 08:23:26 PM PST 24
Finished Jan 21 08:29:10 PM PST 24
Peak memory 1340380 kb
Host smart-de65fe9b-ff3f-4c08-aa24-551befad5156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148768328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.3148768328
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.2706002076
Short name T1516
Test name
Test status
Simulation time 69757443 ps
CPU time 0.79 seconds
Started Jan 21 08:23:27 PM PST 24
Finished Jan 21 08:23:29 PM PST 24
Peak memory 201460 kb
Host smart-c10e9c22-f27c-4bc6-977e-d9a0a4d73a11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706002076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.2706002076
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.2505535657
Short name T870
Test name
Test status
Simulation time 169633354 ps
CPU time 4.66 seconds
Started Jan 21 08:23:27 PM PST 24
Finished Jan 21 08:23:33 PM PST 24
Peak memory 232192 kb
Host smart-71c97103-7172-4a99-b0d4-f1fac199ddb7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505535657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.2505535657
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.3555706261
Short name T303
Test name
Test status
Simulation time 6185237562 ps
CPU time 362.79 seconds
Started Jan 21 08:23:28 PM PST 24
Finished Jan 21 08:29:31 PM PST 24
Peak memory 1699016 kb
Host smart-da1c0bed-53ac-41a1-915c-798cb9fb77ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555706261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.3555706261
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.4189429217
Short name T549
Test name
Test status
Simulation time 1821715432 ps
CPU time 93.34 seconds
Started Jan 21 08:23:42 PM PST 24
Finished Jan 21 08:25:17 PM PST 24
Peak memory 235244 kb
Host smart-bad05a3b-c94b-4aa6-a2b2-dbf82470d584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189429217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.4189429217
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.941905604
Short name T784
Test name
Test status
Simulation time 18690465 ps
CPU time 0.69 seconds
Started Jan 21 08:23:22 PM PST 24
Finished Jan 21 08:23:24 PM PST 24
Peak memory 202192 kb
Host smart-c62e4e86-7ce6-4df8-ab2c-1aa801ecb277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941905604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.941905604
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.3623877817
Short name T373
Test name
Test status
Simulation time 26192742725 ps
CPU time 588.51 seconds
Started Jan 21 08:23:39 PM PST 24
Finished Jan 21 08:33:29 PM PST 24
Peak memory 515524 kb
Host smart-c007fcde-ee13-4745-8189-00730ea5f0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623877817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.3623877817
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_rx_oversample.918718881
Short name T186
Test name
Test status
Simulation time 6907633706 ps
CPU time 424.87 seconds
Started Jan 21 08:23:26 PM PST 24
Finished Jan 21 08:30:32 PM PST 24
Peak memory 332052 kb
Host smart-91c56eee-adae-4140-a459-44f3bc8f9932
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918718881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_rx_oversample.
918718881
Directory /workspace/11.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.3095224333
Short name T1495
Test name
Test status
Simulation time 10712665791 ps
CPU time 157.96 seconds
Started Jan 21 08:23:22 PM PST 24
Finished Jan 21 08:26:01 PM PST 24
Peak memory 269800 kb
Host smart-88d6ad35-977a-4052-b7d9-c5403cef4251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095224333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.3095224333
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.1901230349
Short name T323
Test name
Test status
Simulation time 4836591353 ps
CPU time 18.77 seconds
Started Jan 21 08:23:42 PM PST 24
Finished Jan 21 08:24:01 PM PST 24
Peak memory 218636 kb
Host smart-bd2bb0b2-008d-4e4d-8b4b-d9764e93ab7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901230349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.1901230349
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.1474618323
Short name T592
Test name
Test status
Simulation time 7623372949 ps
CPU time 3.2 seconds
Started Jan 21 08:23:39 PM PST 24
Finished Jan 21 08:23:43 PM PST 24
Peak memory 202664 kb
Host smart-562c6e2b-3185-4aaf-bb38-2269a6d03ddf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474618323 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.1474618323
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.232587960
Short name T1200
Test name
Test status
Simulation time 10143300005 ps
CPU time 36.06 seconds
Started Jan 21 08:23:42 PM PST 24
Finished Jan 21 08:24:19 PM PST 24
Peak memory 356792 kb
Host smart-e2e9b32d-e416-4ebc-91a2-ddb24ed73e37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232587960 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_acq.232587960
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.2818227574
Short name T519
Test name
Test status
Simulation time 10091604332 ps
CPU time 76.26 seconds
Started Jan 21 08:23:37 PM PST 24
Finished Jan 21 08:24:54 PM PST 24
Peak memory 693140 kb
Host smart-3a365573-2a42-4694-9955-c486d0f9301b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818227574 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.2818227574
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.549881948
Short name T632
Test name
Test status
Simulation time 4485168009 ps
CPU time 4.85 seconds
Started Jan 21 08:23:42 PM PST 24
Finished Jan 21 08:23:47 PM PST 24
Peak memory 202680 kb
Host smart-e2fe449e-4f91-4445-9de7-930385c21dd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549881948 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_intr_smoke.549881948
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.598204613
Short name T259
Test name
Test status
Simulation time 11209315130 ps
CPU time 279.99 seconds
Started Jan 21 08:23:38 PM PST 24
Finished Jan 21 08:28:19 PM PST 24
Peak memory 2567220 kb
Host smart-cf6013da-d5b4-4aad-985c-278978f49671
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598204613 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.598204613
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_perf.867951041
Short name T1376
Test name
Test status
Simulation time 910310297 ps
CPU time 5.89 seconds
Started Jan 21 08:23:39 PM PST 24
Finished Jan 21 08:23:45 PM PST 24
Peak memory 206388 kb
Host smart-a466c16c-590a-4f8b-ad7e-328bcd038799
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867951041 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.i2c_target_perf.867951041
Directory /workspace/11.i2c_target_perf/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.2642431644
Short name T462
Test name
Test status
Simulation time 1557289728 ps
CPU time 15.53 seconds
Started Jan 21 08:23:31 PM PST 24
Finished Jan 21 08:23:47 PM PST 24
Peak memory 202584 kb
Host smart-f4b91ede-f4b2-4cb4-a74a-53889fe211d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642431644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.2642431644
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_all.1566409237
Short name T1180
Test name
Test status
Simulation time 27169153536 ps
CPU time 131.65 seconds
Started Jan 21 08:23:39 PM PST 24
Finished Jan 21 08:25:52 PM PST 24
Peak memory 254496 kb
Host smart-962cd06c-5723-47a4-8ebe-8cc2a6a863a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566409237 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.i2c_target_stress_all.1566409237
Directory /workspace/11.i2c_target_stress_all/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.540137604
Short name T299
Test name
Test status
Simulation time 2423184061 ps
CPU time 22.84 seconds
Started Jan 21 08:23:33 PM PST 24
Finished Jan 21 08:23:57 PM PST 24
Peak memory 202664 kb
Host smart-55d65387-897a-430f-951e-2b8f8961091a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540137604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_rd.540137604
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.567963643
Short name T1185
Test name
Test status
Simulation time 20328416440 ps
CPU time 455.99 seconds
Started Jan 21 08:23:34 PM PST 24
Finished Jan 21 08:31:11 PM PST 24
Peak memory 4007904 kb
Host smart-43dd69ad-ce37-4b28-aee9-1b0e2aeebd3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567963643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_wr.567963643
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.2322003488
Short name T761
Test name
Test status
Simulation time 8335922268 ps
CPU time 7.91 seconds
Started Jan 21 08:23:33 PM PST 24
Finished Jan 21 08:23:42 PM PST 24
Peak memory 207804 kb
Host smart-dbcd48c2-178f-4d42-9b1e-b98e1f1ed9a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322003488 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.2322003488
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_ovf.172243045
Short name T957
Test name
Test status
Simulation time 5368227522 ps
CPU time 53.1 seconds
Started Jan 21 08:23:38 PM PST 24
Finished Jan 21 08:24:32 PM PST 24
Peak memory 218804 kb
Host smart-f93ea68d-dd00-474d-881c-c5df3b20fa47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172243045 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_tx_ovf.172243045
Directory /workspace/11.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/11.i2c_target_unexp_stop.13131398
Short name T422
Test name
Test status
Simulation time 8000527517 ps
CPU time 6.65 seconds
Started Jan 21 08:23:31 PM PST 24
Finished Jan 21 08:23:38 PM PST 24
Peak memory 202600 kb
Host smart-4f22f797-43cc-43a5-86d2-d83656e4a606
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13131398 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_unexp_stop.13131398
Directory /workspace/11.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/12.i2c_alert_test.3918729366
Short name T97
Test name
Test status
Simulation time 46310382 ps
CPU time 0.62 seconds
Started Jan 21 08:24:05 PM PST 24
Finished Jan 21 08:24:06 PM PST 24
Peak memory 201936 kb
Host smart-013c632b-79a9-478d-ad78-429a6eefd77f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918729366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.3918729366
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.2935548913
Short name T347
Test name
Test status
Simulation time 42924107 ps
CPU time 1.3 seconds
Started Jan 21 08:24:04 PM PST 24
Finished Jan 21 08:24:05 PM PST 24
Peak memory 210696 kb
Host smart-dc623409-8755-4275-ae0a-db0d58a1804d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935548913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.2935548913
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.672398074
Short name T1456
Test name
Test status
Simulation time 392502848 ps
CPU time 6.43 seconds
Started Jan 21 08:23:55 PM PST 24
Finished Jan 21 08:24:02 PM PST 24
Peak memory 258712 kb
Host smart-183199a8-9b4c-4233-a470-e633e9f5fc07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672398074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_empt
y.672398074
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.1954085527
Short name T518
Test name
Test status
Simulation time 5163232684 ps
CPU time 97.51 seconds
Started Jan 21 08:23:55 PM PST 24
Finished Jan 21 08:25:34 PM PST 24
Peak memory 846656 kb
Host smart-e4bf8e34-1143-49f0-9b2d-719a9cbbc616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954085527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.1954085527
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.22647242
Short name T472
Test name
Test status
Simulation time 9506705230 ps
CPU time 564.61 seconds
Started Jan 21 08:23:44 PM PST 24
Finished Jan 21 08:33:10 PM PST 24
Peak memory 1326716 kb
Host smart-436d8d4c-ce6c-4f53-95a6-0e04b66d73d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22647242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.22647242
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.949318357
Short name T1183
Test name
Test status
Simulation time 1153080831 ps
CPU time 9.52 seconds
Started Jan 21 08:23:58 PM PST 24
Finished Jan 21 08:24:08 PM PST 24
Peak memory 202496 kb
Host smart-120cd057-daaf-4cb3-9d63-f9c7ec4a81d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949318357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx.
949318357
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.18306951
Short name T1452
Test name
Test status
Simulation time 8959782295 ps
CPU time 319.22 seconds
Started Jan 21 08:23:43 PM PST 24
Finished Jan 21 08:29:03 PM PST 24
Peak memory 943684 kb
Host smart-4cd04858-e243-41ae-8309-c69d13032141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18306951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.18306951
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.2635117602
Short name T1158
Test name
Test status
Simulation time 3174186317 ps
CPU time 167.97 seconds
Started Jan 21 08:24:07 PM PST 24
Finished Jan 21 08:26:56 PM PST 24
Peak memory 248428 kb
Host smart-9fdce4d8-66ab-48cc-97b7-aac569b6d908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635117602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.2635117602
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.1106913311
Short name T1330
Test name
Test status
Simulation time 46360031 ps
CPU time 0.63 seconds
Started Jan 21 08:23:43 PM PST 24
Finished Jan 21 08:23:45 PM PST 24
Peak memory 201504 kb
Host smart-d0cdf5bc-1a59-4b75-8d5b-2acd6856df90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106913311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.1106913311
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.2428162505
Short name T1296
Test name
Test status
Simulation time 5411243961 ps
CPU time 112.59 seconds
Started Jan 21 08:23:55 PM PST 24
Finished Jan 21 08:25:48 PM PST 24
Peak memory 250672 kb
Host smart-f060b47e-6a85-480f-93e8-38906c6a6ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428162505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.2428162505
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_rx_oversample.81192025
Short name T1213
Test name
Test status
Simulation time 2745080743 ps
CPU time 88.53 seconds
Started Jan 21 08:23:43 PM PST 24
Finished Jan 21 08:25:12 PM PST 24
Peak memory 229060 kb
Host smart-6d264584-5476-4690-851c-cd34eeb7dfef
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81192025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_rx_oversample.81192025
Directory /workspace/12.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.2247543434
Short name T439
Test name
Test status
Simulation time 2688604545 ps
CPU time 71.92 seconds
Started Jan 21 08:23:45 PM PST 24
Finished Jan 21 08:24:57 PM PST 24
Peak memory 260772 kb
Host smart-3a99a348-7447-44be-a009-01ced5f74a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247543434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.2247543434
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.4019229026
Short name T1079
Test name
Test status
Simulation time 42731526558 ps
CPU time 1056.32 seconds
Started Jan 21 08:23:56 PM PST 24
Finished Jan 21 08:41:33 PM PST 24
Peak memory 1709916 kb
Host smart-6c942c53-8f7e-480b-9d85-8a2375117ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019229026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.4019229026
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.3418354702
Short name T1363
Test name
Test status
Simulation time 2415455694 ps
CPU time 28.74 seconds
Started Jan 21 08:23:57 PM PST 24
Finished Jan 21 08:24:26 PM PST 24
Peak memory 210768 kb
Host smart-8a7647b6-745e-4355-9e9d-32901183bbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418354702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.3418354702
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.4276707853
Short name T981
Test name
Test status
Simulation time 4892417463 ps
CPU time 5.21 seconds
Started Jan 21 08:24:07 PM PST 24
Finished Jan 21 08:24:14 PM PST 24
Peak memory 202600 kb
Host smart-6d3977a5-6690-4487-b08b-2cfae7e750e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276707853 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.4276707853
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.3256499721
Short name T358
Test name
Test status
Simulation time 10315926473 ps
CPU time 11.78 seconds
Started Jan 21 08:24:04 PM PST 24
Finished Jan 21 08:24:17 PM PST 24
Peak memory 289656 kb
Host smart-621ba95d-cfc7-476c-869a-6631aa8f0c6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256499721 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.3256499721
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.1125084298
Short name T866
Test name
Test status
Simulation time 10105300891 ps
CPU time 12.67 seconds
Started Jan 21 08:24:09 PM PST 24
Finished Jan 21 08:24:22 PM PST 24
Peak memory 283472 kb
Host smart-1442ebee-f4f3-46f1-b1a0-75ffb3bf0c79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125084298 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.1125084298
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.761310489
Short name T683
Test name
Test status
Simulation time 1776633275 ps
CPU time 2.71 seconds
Started Jan 21 08:54:40 PM PST 24
Finished Jan 21 08:54:49 PM PST 24
Peak memory 202620 kb
Host smart-3c6fc967-6f74-4379-8074-f573dee94798
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761310489 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.i2c_target_hrst.761310489
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.253982254
Short name T1069
Test name
Test status
Simulation time 7707296556 ps
CPU time 7.26 seconds
Started Jan 21 08:24:06 PM PST 24
Finished Jan 21 08:24:14 PM PST 24
Peak memory 208404 kb
Host smart-6e5ff3f1-77d0-4d6a-91ec-f0e0c50421cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253982254 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_intr_smoke.253982254
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.2178894142
Short name T1347
Test name
Test status
Simulation time 12602832188 ps
CPU time 58.24 seconds
Started Jan 21 08:24:04 PM PST 24
Finished Jan 21 08:25:03 PM PST 24
Peak memory 874004 kb
Host smart-d05af8cf-e31f-4cbf-be33-f402c82b35e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178894142 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.2178894142
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_perf.53568595
Short name T643
Test name
Test status
Simulation time 468011542 ps
CPU time 3.01 seconds
Started Jan 21 08:27:11 PM PST 24
Finished Jan 21 08:27:15 PM PST 24
Peak memory 202568 kb
Host smart-c56345a6-0ed8-4002-b5c1-b4930b1f062e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53568595 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.i2c_target_perf.53568595
Directory /workspace/12.i2c_target_perf/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.812112350
Short name T464
Test name
Test status
Simulation time 1572805278 ps
CPU time 43.38 seconds
Started Jan 21 08:23:57 PM PST 24
Finished Jan 21 08:24:41 PM PST 24
Peak memory 202544 kb
Host smart-774f86ee-9b17-47e5-8d99-2e5cefdbf09e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812112350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_tar
get_smoke.812112350
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_all.3357549454
Short name T1246
Test name
Test status
Simulation time 9132609616 ps
CPU time 42.65 seconds
Started Jan 21 08:24:06 PM PST 24
Finished Jan 21 08:24:50 PM PST 24
Peak memory 245612 kb
Host smart-71428f2f-3f88-4638-9308-1f3e073fa19a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357549454 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.i2c_target_stress_all.3357549454
Directory /workspace/12.i2c_target_stress_all/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.1977012486
Short name T1121
Test name
Test status
Simulation time 2293360082 ps
CPU time 10.8 seconds
Started Jan 21 08:23:56 PM PST 24
Finished Jan 21 08:24:08 PM PST 24
Peak memory 204856 kb
Host smart-18421b8b-fb77-4a57-93af-c0a26a064459
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977012486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.1977012486
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.562556391
Short name T1056
Test name
Test status
Simulation time 23406027528 ps
CPU time 53.85 seconds
Started Jan 21 08:23:57 PM PST 24
Finished Jan 21 08:24:52 PM PST 24
Peak memory 998888 kb
Host smart-732c1047-0f29-448a-8e2e-cce9be853986
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562556391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c
_target_stress_wr.562556391
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.178683885
Short name T298
Test name
Test status
Simulation time 18796224096 ps
CPU time 3044.99 seconds
Started Jan 21 08:23:57 PM PST 24
Finished Jan 21 09:14:43 PM PST 24
Peak memory 4633424 kb
Host smart-9f60a139-9b21-4d55-8405-1a91d683bfaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178683885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_t
arget_stretch.178683885
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.781014033
Short name T1025
Test name
Test status
Simulation time 2953387049 ps
CPU time 7.21 seconds
Started Jan 21 08:24:06 PM PST 24
Finished Jan 21 08:24:14 PM PST 24
Peak memory 209412 kb
Host smart-3d38c225-391a-4e8b-a156-a2f4801604f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781014033 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_timeout.781014033
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_ovf.2260466953
Short name T508
Test name
Test status
Simulation time 3179346995 ps
CPU time 171.63 seconds
Started Jan 21 08:24:05 PM PST 24
Finished Jan 21 08:26:57 PM PST 24
Peak memory 367312 kb
Host smart-d5aed017-a8bf-44ca-bdf2-8b18aaaeaa5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260466953 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_tx_ovf.2260466953
Directory /workspace/12.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/12.i2c_target_unexp_stop.3501098092
Short name T1497
Test name
Test status
Simulation time 4628984303 ps
CPU time 6.99 seconds
Started Jan 21 08:24:07 PM PST 24
Finished Jan 21 08:24:15 PM PST 24
Peak memory 212820 kb
Host smart-58368dee-db40-4cd2-902a-0c5dcd551382
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501098092 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.i2c_target_unexp_stop.3501098092
Directory /workspace/12.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/13.i2c_alert_test.2822363767
Short name T362
Test name
Test status
Simulation time 18751278 ps
CPU time 0.63 seconds
Started Jan 21 08:24:40 PM PST 24
Finished Jan 21 08:24:47 PM PST 24
Peak memory 201068 kb
Host smart-7e213f00-155e-4366-ad7e-7fff089d9bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822363767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.2822363767
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.4247044973
Short name T1131
Test name
Test status
Simulation time 380751962 ps
CPU time 1.64 seconds
Started Jan 21 08:24:26 PM PST 24
Finished Jan 21 08:24:28 PM PST 24
Peak memory 210684 kb
Host smart-6b173659-dbc9-4900-b675-275176f341b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247044973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.4247044973
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.3172544883
Short name T778
Test name
Test status
Simulation time 447213811 ps
CPU time 10.35 seconds
Started Jan 21 08:41:19 PM PST 24
Finished Jan 21 08:41:34 PM PST 24
Peak memory 302248 kb
Host smart-28e0cad9-eedd-42fb-8fbe-957e540823ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172544883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.3172544883
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.1995180224
Short name T341
Test name
Test status
Simulation time 9146588520 ps
CPU time 147.47 seconds
Started Jan 21 08:24:21 PM PST 24
Finished Jan 21 08:26:50 PM PST 24
Peak memory 680796 kb
Host smart-0149a644-1151-4b1b-a14c-86258fd36f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995180224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.1995180224
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.3896760592
Short name T510
Test name
Test status
Simulation time 51056525596 ps
CPU time 693.27 seconds
Started Jan 21 09:20:57 PM PST 24
Finished Jan 21 09:32:37 PM PST 24
Peak memory 1366668 kb
Host smart-0f77591b-2910-4d74-a3cb-92495c672aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896760592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.3896760592
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.3794003209
Short name T740
Test name
Test status
Simulation time 160289148 ps
CPU time 1.06 seconds
Started Jan 21 08:46:25 PM PST 24
Finished Jan 21 08:47:14 PM PST 24
Peak memory 202344 kb
Host smart-404351a5-5343-4f58-b3de-9350ed183fe0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794003209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.3794003209
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.3238593781
Short name T570
Test name
Test status
Simulation time 372347867 ps
CPU time 4.63 seconds
Started Jan 21 08:24:19 PM PST 24
Finished Jan 21 08:24:24 PM PST 24
Peak memory 202496 kb
Host smart-dfd03215-13e8-4fdb-b2da-e924fdaaabe7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238593781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.3238593781
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.378333795
Short name T1198
Test name
Test status
Simulation time 33343818248 ps
CPU time 291.26 seconds
Started Jan 21 08:24:11 PM PST 24
Finished Jan 21 08:29:03 PM PST 24
Peak memory 1323368 kb
Host smart-500e6189-9674-4cc9-860b-7fcd69995b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378333795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.378333795
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.1782255430
Short name T1523
Test name
Test status
Simulation time 2828519414 ps
CPU time 74.45 seconds
Started Jan 21 08:24:37 PM PST 24
Finished Jan 21 08:25:54 PM PST 24
Peak memory 245784 kb
Host smart-dc90b314-e46c-46d2-b67f-9d53208f5281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782255430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.1782255430
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.283348295
Short name T418
Test name
Test status
Simulation time 16824691 ps
CPU time 0.64 seconds
Started Jan 21 08:24:12 PM PST 24
Finished Jan 21 08:24:13 PM PST 24
Peak memory 201456 kb
Host smart-9868ad5b-5b46-405f-a6b5-f222a348caa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283348295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.283348295
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.2119003585
Short name T752
Test name
Test status
Simulation time 52330583653 ps
CPU time 1378.08 seconds
Started Jan 21 09:24:48 PM PST 24
Finished Jan 21 09:47:47 PM PST 24
Peak memory 214132 kb
Host smart-141a2a5e-e501-4f2d-83a1-d09ea9acd17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119003585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.2119003585
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_rx_oversample.3506743810
Short name T469
Test name
Test status
Simulation time 8148480881 ps
CPU time 87.98 seconds
Started Jan 21 08:24:12 PM PST 24
Finished Jan 21 08:25:41 PM PST 24
Peak memory 289456 kb
Host smart-ef72d191-2834-44f4-a79e-4a4de093fb09
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506743810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_rx_oversample
.3506743810
Directory /workspace/13.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.3704101769
Short name T320
Test name
Test status
Simulation time 4317384136 ps
CPU time 68.29 seconds
Started Jan 21 08:24:09 PM PST 24
Finished Jan 21 08:25:19 PM PST 24
Peak memory 291948 kb
Host smart-e3cd14f2-ac7c-4fc9-bf88-4a83047a5a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704101769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.3704101769
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all_with_rand_reset.1450699645
Short name T86
Test name
Test status
Simulation time 149050214711 ps
CPU time 558.96 seconds
Started Jan 21 08:24:35 PM PST 24
Finished Jan 21 08:33:55 PM PST 24
Peak memory 745280 kb
Host smart-71651e03-7ec3-42a2-a256-76f88c7cc764
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450699645 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 13.i2c_host_stress_all_with_rand_reset.1450699645
Directory /workspace/13.i2c_host_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.1132928485
Short name T1060
Test name
Test status
Simulation time 880232758 ps
CPU time 39.76 seconds
Started Jan 21 08:24:17 PM PST 24
Finished Jan 21 08:24:58 PM PST 24
Peak memory 210764 kb
Host smart-4c435876-db90-4a78-a9d7-b87cb68d30bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132928485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.1132928485
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.1698164995
Short name T919
Test name
Test status
Simulation time 3237839242 ps
CPU time 3.45 seconds
Started Jan 21 08:24:35 PM PST 24
Finished Jan 21 08:24:39 PM PST 24
Peak memory 202536 kb
Host smart-10d4c669-4b83-4459-a45e-204b20690c19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698164995 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.1698164995
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.1894836123
Short name T1261
Test name
Test status
Simulation time 10093420590 ps
CPU time 12.05 seconds
Started Jan 21 08:24:36 PM PST 24
Finished Jan 21 08:24:49 PM PST 24
Peak memory 282684 kb
Host smart-995a79fa-335b-4fa8-b965-7e5a3925a3e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894836123 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.1894836123
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.1282274562
Short name T1371
Test name
Test status
Simulation time 10149624443 ps
CPU time 12.82 seconds
Started Jan 21 08:24:34 PM PST 24
Finished Jan 21 08:24:47 PM PST 24
Peak memory 291176 kb
Host smart-3cc9e6d0-40fb-4301-9ce3-f5b06653bd79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282274562 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.1282274562
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.1653666230
Short name T1150
Test name
Test status
Simulation time 3192267751 ps
CPU time 2.63 seconds
Started Jan 21 08:24:37 PM PST 24
Finished Jan 21 08:24:41 PM PST 24
Peak memory 202900 kb
Host smart-114485fc-e84d-4f76-bb4c-6a21708f7a7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653666230 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.1653666230
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.1684317780
Short name T1378
Test name
Test status
Simulation time 3363554332 ps
CPU time 6.61 seconds
Started Jan 21 10:35:43 PM PST 24
Finished Jan 21 10:35:59 PM PST 24
Peak memory 202696 kb
Host smart-e6e8e03f-00ee-44f8-908f-5c1505d593fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684317780 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.1684317780
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.178503152
Short name T1505
Test name
Test status
Simulation time 13189726937 ps
CPU time 451.95 seconds
Started Jan 21 08:24:29 PM PST 24
Finished Jan 21 08:32:01 PM PST 24
Peak memory 3057160 kb
Host smart-78c1e6cc-0164-4c9a-8679-35d6f8e5aa83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178503152 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.178503152
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_perf.1137068080
Short name T700
Test name
Test status
Simulation time 1051797097 ps
CPU time 5.21 seconds
Started Jan 21 10:20:21 PM PST 24
Finished Jan 21 10:20:31 PM PST 24
Peak memory 205880 kb
Host smart-b20b5db7-a02b-415d-8aec-8892d452eee4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137068080 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_perf.1137068080
Directory /workspace/13.i2c_target_perf/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.586738196
Short name T1485
Test name
Test status
Simulation time 5605228955 ps
CPU time 9.4 seconds
Started Jan 21 08:24:30 PM PST 24
Finished Jan 21 08:24:40 PM PST 24
Peak memory 202700 kb
Host smart-9bd5bcf5-02d8-408f-b431-0f4a5c695d45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586738196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_tar
get_smoke.586738196
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.4046413210
Short name T829
Test name
Test status
Simulation time 1212824937 ps
CPU time 10.34 seconds
Started Jan 21 08:24:29 PM PST 24
Finished Jan 21 08:24:40 PM PST 24
Peak memory 202576 kb
Host smart-cb0400e1-02a6-4bea-b0aa-d75be4d5fe8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046413210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.4046413210
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.206347461
Short name T1351
Test name
Test status
Simulation time 22589447757 ps
CPU time 102.54 seconds
Started Jan 21 08:24:35 PM PST 24
Finished Jan 21 08:26:19 PM PST 24
Peak memory 1448456 kb
Host smart-7afb678b-88b2-417d-b0c3-125b5d246a63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206347461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_wr.206347461
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.3110383289
Short name T983
Test name
Test status
Simulation time 43130905020 ps
CPU time 350.16 seconds
Started Jan 21 08:24:29 PM PST 24
Finished Jan 21 08:30:20 PM PST 24
Peak memory 2297412 kb
Host smart-16de2d9a-7746-4c78-be04-c6be93a1b6c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110383289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.3110383289
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.3386738108
Short name T1428
Test name
Test status
Simulation time 3263705873 ps
CPU time 6.91 seconds
Started Jan 21 08:24:33 PM PST 24
Finished Jan 21 08:24:41 PM PST 24
Peak memory 202680 kb
Host smart-402cab96-7e3d-48a5-8608-0cb1369090ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386738108 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.3386738108
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_tx_ovf.2719484543
Short name T316
Test name
Test status
Simulation time 16865693315 ps
CPU time 196.99 seconds
Started Jan 21 08:24:27 PM PST 24
Finished Jan 21 08:27:45 PM PST 24
Peak memory 380940 kb
Host smart-3739fd3a-61b0-4bd6-8244-1284cd3d6d6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719484543 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_tx_ovf.2719484543
Directory /workspace/13.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/13.i2c_target_unexp_stop.2903612294
Short name T914
Test name
Test status
Simulation time 7870113964 ps
CPU time 4.46 seconds
Started Jan 21 08:24:30 PM PST 24
Finished Jan 21 08:24:35 PM PST 24
Peak memory 202640 kb
Host smart-72a6f670-ec0e-4c59-814e-ef03928d613f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903612294 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.i2c_target_unexp_stop.2903612294
Directory /workspace/13.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/14.i2c_alert_test.3035546573
Short name T1285
Test name
Test status
Simulation time 30078959 ps
CPU time 0.61 seconds
Started Jan 21 08:25:05 PM PST 24
Finished Jan 21 08:25:10 PM PST 24
Peak memory 201024 kb
Host smart-9717571e-3aa8-4d3f-9113-80a96e16a28c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035546573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.3035546573
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.1991344462
Short name T663
Test name
Test status
Simulation time 39614131 ps
CPU time 1.23 seconds
Started Jan 21 08:24:54 PM PST 24
Finished Jan 21 08:24:57 PM PST 24
Peak memory 210648 kb
Host smart-0eba62ae-10f6-4d54-8db4-054c46160414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991344462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.1991344462
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.673018996
Short name T394
Test name
Test status
Simulation time 466913184 ps
CPU time 9.9 seconds
Started Jan 21 08:24:46 PM PST 24
Finished Jan 21 08:24:59 PM PST 24
Peak memory 280676 kb
Host smart-8aaae3db-4e53-4228-803f-bfeb412ba8b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673018996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empt
y.673018996
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.3928549391
Short name T485
Test name
Test status
Simulation time 7696790623 ps
CPU time 54.06 seconds
Started Jan 21 08:49:05 PM PST 24
Finished Jan 21 08:50:06 PM PST 24
Peak memory 210748 kb
Host smart-30d324a1-bc8d-4a45-95d5-e9c5277b11da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928549391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.3928549391
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.722385453
Short name T1493
Test name
Test status
Simulation time 11264896299 ps
CPU time 772.05 seconds
Started Jan 21 08:24:54 PM PST 24
Finished Jan 21 08:37:48 PM PST 24
Peak memory 1552976 kb
Host smart-01b9a7e6-f740-4f16-a005-8fd6aeb396c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722385453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.722385453
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.1883094452
Short name T503
Test name
Test status
Simulation time 107536787 ps
CPU time 0.84 seconds
Started Jan 21 08:24:54 PM PST 24
Finished Jan 21 08:24:57 PM PST 24
Peak memory 202300 kb
Host smart-8b91a5fc-80f4-499e-b05d-62364f6bf377
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883094452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.1883094452
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.1703607205
Short name T1403
Test name
Test status
Simulation time 274306517 ps
CPU time 7.78 seconds
Started Jan 21 08:24:49 PM PST 24
Finished Jan 21 08:24:59 PM PST 24
Peak memory 202556 kb
Host smart-b4465ba3-6cd3-4189-b598-383ce1173475
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703607205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.1703607205
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.3015506550
Short name T1204
Test name
Test status
Simulation time 8171066607 ps
CPU time 214.44 seconds
Started Jan 21 08:24:48 PM PST 24
Finished Jan 21 08:28:26 PM PST 24
Peak memory 1223024 kb
Host smart-45de1bc3-d70a-4aa7-b380-4a6429849b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015506550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.3015506550
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.3256705273
Short name T1305
Test name
Test status
Simulation time 22251313987 ps
CPU time 38.25 seconds
Started Jan 21 08:25:08 PM PST 24
Finished Jan 21 08:25:49 PM PST 24
Peak memory 314676 kb
Host smart-d40dfc4b-216d-4bfb-966b-b723cb4fa9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256705273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.3256705273
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_perf.3831577996
Short name T1385
Test name
Test status
Simulation time 53084711713 ps
CPU time 2626.32 seconds
Started Jan 21 08:24:49 PM PST 24
Finished Jan 21 09:08:38 PM PST 24
Peak memory 202616 kb
Host smart-31983fd1-05d3-446d-a17e-32281d28c93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831577996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.3831577996
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_rx_oversample.2158042314
Short name T437
Test name
Test status
Simulation time 3315377373 ps
CPU time 227.99 seconds
Started Jan 21 08:24:42 PM PST 24
Finished Jan 21 08:28:34 PM PST 24
Peak memory 364796 kb
Host smart-5a09a7e2-ce22-4a4a-ab68-f0d25710d272
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158042314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_rx_oversample
.2158042314
Directory /workspace/14.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.3099081168
Short name T1055
Test name
Test status
Simulation time 3923988811 ps
CPU time 40.35 seconds
Started Jan 21 08:24:48 PM PST 24
Finished Jan 21 08:25:32 PM PST 24
Peak memory 265384 kb
Host smart-81bfdba5-6763-4437-8deb-c5259268ba9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099081168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.3099081168
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.213025503
Short name T959
Test name
Test status
Simulation time 46668634899 ps
CPU time 1286.64 seconds
Started Jan 21 08:24:54 PM PST 24
Finished Jan 21 08:46:23 PM PST 24
Peak memory 1858584 kb
Host smart-6abdfccd-b6fc-421a-8b9a-67d835c9c1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213025503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.213025503
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.1911319561
Short name T301
Test name
Test status
Simulation time 3600574029 ps
CPU time 40.81 seconds
Started Jan 21 08:24:46 PM PST 24
Finished Jan 21 08:25:31 PM PST 24
Peak memory 210724 kb
Host smart-3ca8ed15-a86d-424e-824e-ac60a1061f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911319561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.1911319561
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.3564963263
Short name T197
Test name
Test status
Simulation time 2788026178 ps
CPU time 5.05 seconds
Started Jan 21 08:35:03 PM PST 24
Finished Jan 21 08:35:10 PM PST 24
Peak memory 202696 kb
Host smart-6dac6f22-7b74-4dd9-9325-6f981846058d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564963263 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.3564963263
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.982793686
Short name T277
Test name
Test status
Simulation time 10085237043 ps
CPU time 11.15 seconds
Started Jan 21 08:25:01 PM PST 24
Finished Jan 21 08:25:18 PM PST 24
Peak memory 264884 kb
Host smart-343f2662-3309-419b-8a82-8f09fcf36930
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982793686 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_acq.982793686
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.3550490081
Short name T1263
Test name
Test status
Simulation time 10161329866 ps
CPU time 15.44 seconds
Started Jan 21 08:25:06 PM PST 24
Finished Jan 21 08:25:25 PM PST 24
Peak memory 317536 kb
Host smart-b5d89ab0-8a84-4a00-84fe-b89909a21c1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550490081 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.3550490081
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.1429566003
Short name T378
Test name
Test status
Simulation time 2165088916 ps
CPU time 2.85 seconds
Started Jan 21 08:24:59 PM PST 24
Finished Jan 21 08:25:09 PM PST 24
Peak memory 202664 kb
Host smart-3dbac6b4-2e32-4dd3-9067-370d8f9231b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429566003 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.1429566003
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.1924340399
Short name T333
Test name
Test status
Simulation time 7407634696 ps
CPU time 7.09 seconds
Started Jan 21 08:24:52 PM PST 24
Finished Jan 21 08:25:00 PM PST 24
Peak memory 202652 kb
Host smart-60e15125-4e86-40f3-9bb2-794b743562ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924340399 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.1924340399
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.3794836053
Short name T1467
Test name
Test status
Simulation time 8278360969 ps
CPU time 99.48 seconds
Started Jan 21 08:24:53 PM PST 24
Finished Jan 21 08:26:33 PM PST 24
Peak memory 1532108 kb
Host smart-409e8e98-7810-414f-8d12-1b619073a68e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794836053 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.3794836053
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_perf.1177278966
Short name T201
Test name
Test status
Simulation time 1184374447 ps
CPU time 2.26 seconds
Started Jan 21 08:48:59 PM PST 24
Finished Jan 21 08:49:10 PM PST 24
Peak memory 202596 kb
Host smart-8409ce8a-069f-4ded-a8c9-a0872e44a253
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177278966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_perf.1177278966
Directory /workspace/14.i2c_target_perf/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.889888872
Short name T1084
Test name
Test status
Simulation time 5338274343 ps
CPU time 35.43 seconds
Started Jan 21 09:41:47 PM PST 24
Finished Jan 21 09:42:25 PM PST 24
Peak memory 202584 kb
Host smart-c68aec78-e663-49fe-a88b-b5e8f2b029f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889888872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_tar
get_smoke.889888872
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_all.570514054
Short name T1053
Test name
Test status
Simulation time 37513172794 ps
CPU time 1046.75 seconds
Started Jan 21 09:55:46 PM PST 24
Finished Jan 21 10:13:20 PM PST 24
Peak memory 5170884 kb
Host smart-2f53ca7a-5195-4569-a07f-aa55347c663c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570514054 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.i2c_target_stress_all.570514054
Directory /workspace/14.i2c_target_stress_all/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.3390484289
Short name T1208
Test name
Test status
Simulation time 1091637582 ps
CPU time 19.84 seconds
Started Jan 21 08:29:34 PM PST 24
Finished Jan 21 08:29:55 PM PST 24
Peak memory 208808 kb
Host smart-a846e319-6220-45b9-879a-c2529d0103c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390484289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.3390484289
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.3684802774
Short name T1104
Test name
Test status
Simulation time 7689834190 ps
CPU time 2.36 seconds
Started Jan 21 08:24:53 PM PST 24
Finished Jan 21 08:24:56 PM PST 24
Peak memory 202788 kb
Host smart-b87a7bdb-cb4d-46c1-80b3-6a59dc60a6fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684802774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.3684802774
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.1157637149
Short name T1379
Test name
Test status
Simulation time 34605681842 ps
CPU time 288.11 seconds
Started Jan 21 08:24:56 PM PST 24
Finished Jan 21 08:29:51 PM PST 24
Peak memory 1747472 kb
Host smart-4c8a67a4-9f63-4325-8606-ec068a70f9b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157637149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.1157637149
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.3520243720
Short name T7
Test name
Test status
Simulation time 1786191108 ps
CPU time 7.68 seconds
Started Jan 21 08:40:03 PM PST 24
Finished Jan 21 08:40:11 PM PST 24
Peak memory 202536 kb
Host smart-8070885a-d999-48cd-9b5e-56c306d7cc25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520243720 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.3520243720
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_ovf.2147674424
Short name T1402
Test name
Test status
Simulation time 32121567079 ps
CPU time 111.98 seconds
Started Jan 21 08:24:52 PM PST 24
Finished Jan 21 08:26:45 PM PST 24
Peak memory 332928 kb
Host smart-3a36ea7f-f229-4b63-a4f0-4f58d88cdbed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147674424 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_tx_ovf.2147674424
Directory /workspace/14.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/14.i2c_target_unexp_stop.2465345839
Short name T423
Test name
Test status
Simulation time 2422374990 ps
CPU time 6.49 seconds
Started Jan 21 08:24:59 PM PST 24
Finished Jan 21 08:25:13 PM PST 24
Peak memory 204120 kb
Host smart-13fc4fd9-b276-4733-9f9b-2fe459876292
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465345839 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.i2c_target_unexp_stop.2465345839
Directory /workspace/14.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/15.i2c_alert_test.2105414592
Short name T1286
Test name
Test status
Simulation time 46066373 ps
CPU time 0.61 seconds
Started Jan 21 08:25:35 PM PST 24
Finished Jan 21 08:25:37 PM PST 24
Peak memory 201084 kb
Host smart-c3bac336-707e-4695-9a33-4fb7cf5f211e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105414592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.2105414592
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.582609002
Short name T1054
Test name
Test status
Simulation time 209637445 ps
CPU time 1.33 seconds
Started Jan 21 08:25:11 PM PST 24
Finished Jan 21 08:25:14 PM PST 24
Peak memory 210688 kb
Host smart-f4548dca-d955-43ba-8e13-c8da82adf0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582609002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.582609002
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.3847140894
Short name T731
Test name
Test status
Simulation time 236671966 ps
CPU time 4.54 seconds
Started Jan 21 08:25:13 PM PST 24
Finished Jan 21 08:25:20 PM PST 24
Peak memory 248732 kb
Host smart-3f1e431b-fe94-4656-bf24-b98dbbc71a3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847140894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.3847140894
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.3869465644
Short name T946
Test name
Test status
Simulation time 13358617839 ps
CPU time 347.01 seconds
Started Jan 21 08:25:07 PM PST 24
Finished Jan 21 08:30:58 PM PST 24
Peak memory 1100808 kb
Host smart-6b140bf9-3751-49f1-85e3-62541b4df5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869465644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.3869465644
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.2491666703
Short name T239
Test name
Test status
Simulation time 4934335249 ps
CPU time 385.86 seconds
Started Jan 21 08:25:10 PM PST 24
Finished Jan 21 08:31:38 PM PST 24
Peak memory 1463560 kb
Host smart-8cb3b082-046a-4b8f-888f-d0895af70d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491666703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.2491666703
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.2654749583
Short name T1212
Test name
Test status
Simulation time 212350292 ps
CPU time 1 seconds
Started Jan 21 08:25:14 PM PST 24
Finished Jan 21 08:25:17 PM PST 24
Peak memory 202480 kb
Host smart-9a40559a-8977-41fe-8b1d-9825b643153b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654749583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.2654749583
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.2691803842
Short name T521
Test name
Test status
Simulation time 484584704 ps
CPU time 4.78 seconds
Started Jan 21 08:25:09 PM PST 24
Finished Jan 21 08:25:16 PM PST 24
Peak memory 202540 kb
Host smart-6bfe5b56-74e8-44a6-a5fb-3ac61a7ffcbd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691803842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.2691803842
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.1503422497
Short name T185
Test name
Test status
Simulation time 4618494289 ps
CPU time 534.17 seconds
Started Jan 21 08:25:11 PM PST 24
Finished Jan 21 08:34:07 PM PST 24
Peak memory 1353836 kb
Host smart-dd8d28d4-0642-46b8-8355-9dc99c0e04dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503422497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.1503422497
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.2925960785
Short name T646
Test name
Test status
Simulation time 12812372129 ps
CPU time 261.05 seconds
Started Jan 21 08:25:39 PM PST 24
Finished Jan 21 08:30:01 PM PST 24
Peak memory 517152 kb
Host smart-cd858b9b-6508-46b5-b693-b28993182efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925960785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.2925960785
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.772327124
Short name T109
Test name
Test status
Simulation time 30523770 ps
CPU time 0.64 seconds
Started Jan 21 08:25:08 PM PST 24
Finished Jan 21 08:25:11 PM PST 24
Peak memory 201520 kb
Host smart-0c36e40d-5d63-4d4a-b073-874d898a2c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772327124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.772327124
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.175382537
Short name T306
Test name
Test status
Simulation time 30932544537 ps
CPU time 463.82 seconds
Started Jan 21 08:25:09 PM PST 24
Finished Jan 21 08:32:55 PM PST 24
Peak memory 218272 kb
Host smart-939d0c7a-053f-4578-9ba6-0e5cb52f5ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175382537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.175382537
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_rx_oversample.2399504939
Short name T557
Test name
Test status
Simulation time 13065444628 ps
CPU time 217.54 seconds
Started Jan 21 08:25:06 PM PST 24
Finished Jan 21 08:28:47 PM PST 24
Peak memory 379388 kb
Host smart-1f8ff0ed-b785-42b8-82e9-936122c0cdf2
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399504939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_rx_oversample
.2399504939
Directory /workspace/15.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.4006161397
Short name T328
Test name
Test status
Simulation time 1990576114 ps
CPU time 59.37 seconds
Started Jan 21 08:25:07 PM PST 24
Finished Jan 21 08:26:10 PM PST 24
Peak memory 283496 kb
Host smart-a188909c-c4bd-4a59-90b5-f1e974e88e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006161397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.4006161397
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.3591205823
Short name T209
Test name
Test status
Simulation time 4420754974 ps
CPU time 16.24 seconds
Started Jan 21 08:25:11 PM PST 24
Finished Jan 21 08:25:29 PM PST 24
Peak memory 227048 kb
Host smart-8491383c-1c0e-4cfe-ab88-aa462af2beff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591205823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.3591205823
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.602217969
Short name T1176
Test name
Test status
Simulation time 3633637902 ps
CPU time 3.85 seconds
Started Jan 21 08:25:33 PM PST 24
Finished Jan 21 08:25:39 PM PST 24
Peak memory 202660 kb
Host smart-7fd08a55-6206-42e0-8b1f-d8164b89afa2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602217969 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.602217969
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.2897500081
Short name T547
Test name
Test status
Simulation time 10042776232 ps
CPU time 52.41 seconds
Started Jan 21 08:25:25 PM PST 24
Finished Jan 21 08:26:20 PM PST 24
Peak memory 446184 kb
Host smart-7dada9c4-634a-448d-b40c-0aefbdc553cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897500081 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.2897500081
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.4288456770
Short name T1031
Test name
Test status
Simulation time 10246756734 ps
CPU time 15.9 seconds
Started Jan 21 08:44:45 PM PST 24
Finished Jan 21 08:45:01 PM PST 24
Peak memory 322440 kb
Host smart-094b2eef-198f-4413-b79b-1355c2516e24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288456770 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.4288456770
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.1163557792
Short name T844
Test name
Test status
Simulation time 657210742 ps
CPU time 3.11 seconds
Started Jan 21 08:25:31 PM PST 24
Finished Jan 21 08:25:35 PM PST 24
Peak memory 202836 kb
Host smart-30d5fb03-ab08-488f-b7c3-82565c455e10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163557792 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.1163557792
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.3602435761
Short name T749
Test name
Test status
Simulation time 1758094884 ps
CPU time 7.02 seconds
Started Jan 21 08:25:23 PM PST 24
Finished Jan 21 08:25:32 PM PST 24
Peak memory 206512 kb
Host smart-e2767eb3-bfd8-458e-a49c-1ee5db68ced4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602435761 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.3602435761
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.2176650256
Short name T1370
Test name
Test status
Simulation time 8509963359 ps
CPU time 150.8 seconds
Started Jan 21 08:53:40 PM PST 24
Finished Jan 21 08:56:28 PM PST 24
Peak memory 1729192 kb
Host smart-dd7290a8-f6f3-4741-bc23-e9fcd2871309
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176650256 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.2176650256
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_perf.3313112435
Short name T701
Test name
Test status
Simulation time 628194732 ps
CPU time 4 seconds
Started Jan 21 08:25:31 PM PST 24
Finished Jan 21 08:25:37 PM PST 24
Peak memory 207268 kb
Host smart-a69075fe-6928-4d6e-8569-cab1e92fd9ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313112435 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_perf.3313112435
Directory /workspace/15.i2c_target_perf/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.810456638
Short name T838
Test name
Test status
Simulation time 981910881 ps
CPU time 26.7 seconds
Started Jan 21 08:51:05 PM PST 24
Finished Jan 21 08:52:16 PM PST 24
Peak memory 202520 kb
Host smart-3a53c411-c870-4d62-be2d-3399543210bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810456638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_tar
get_smoke.810456638
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_all.1234843604
Short name T854
Test name
Test status
Simulation time 84296118447 ps
CPU time 988.06 seconds
Started Jan 21 08:25:32 PM PST 24
Finished Jan 21 08:42:02 PM PST 24
Peak memory 2357512 kb
Host smart-368892b5-b0a3-4a5a-9389-acd7ff642ae1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234843604 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.i2c_target_stress_all.1234843604
Directory /workspace/15.i2c_target_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.3509112826
Short name T923
Test name
Test status
Simulation time 2398659477 ps
CPU time 23.98 seconds
Started Jan 21 08:25:21 PM PST 24
Finished Jan 21 08:25:48 PM PST 24
Peak memory 202632 kb
Host smart-c87941cd-d257-4576-b9af-2b0797b1c9df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509112826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.3509112826
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.3458899335
Short name T1193
Test name
Test status
Simulation time 38590734059 ps
CPU time 88.22 seconds
Started Jan 21 08:25:16 PM PST 24
Finished Jan 21 08:26:50 PM PST 24
Peak memory 1144084 kb
Host smart-e8b39ebb-8355-401a-9acd-f8ee339e65aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458899335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.3458899335
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.1513550800
Short name T833
Test name
Test status
Simulation time 39585831340 ps
CPU time 488.48 seconds
Started Jan 21 08:25:20 PM PST 24
Finished Jan 21 08:33:32 PM PST 24
Peak memory 2651980 kb
Host smart-043b1615-283d-4cc4-b7f7-3878b13399a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513550800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.1513550800
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.1694888731
Short name T352
Test name
Test status
Simulation time 8045056720 ps
CPU time 7.41 seconds
Started Jan 21 08:25:31 PM PST 24
Finished Jan 21 08:25:40 PM PST 24
Peak memory 202644 kb
Host smart-83a97c91-b16b-410a-8a15-781d126629b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694888731 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.1694888731
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_tx_ovf.3142869326
Short name T1119
Test name
Test status
Simulation time 13178735951 ps
CPU time 99.07 seconds
Started Jan 21 08:25:26 PM PST 24
Finished Jan 21 08:27:07 PM PST 24
Peak memory 349836 kb
Host smart-abd35bc3-c82e-4a56-89cd-88d22d8be462
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142869326 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_tx_ovf.3142869326
Directory /workspace/15.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/15.i2c_target_unexp_stop.746800853
Short name T811
Test name
Test status
Simulation time 1381663233 ps
CPU time 7.71 seconds
Started Jan 21 08:25:28 PM PST 24
Finished Jan 21 08:25:37 PM PST 24
Peak memory 202556 kb
Host smart-bad301a5-0dcc-40e5-9360-426239f52691
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746800853 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_unexp_stop.746800853
Directory /workspace/15.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/16.i2c_alert_test.4029542405
Short name T1191
Test name
Test status
Simulation time 34017824 ps
CPU time 0.61 seconds
Started Jan 21 08:26:09 PM PST 24
Finished Jan 21 08:26:11 PM PST 24
Peak memory 201128 kb
Host smart-79127221-6e32-4277-9d3b-4587d9721832
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029542405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.4029542405
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.4154490858
Short name T1299
Test name
Test status
Simulation time 88720707 ps
CPU time 1.41 seconds
Started Jan 21 08:25:44 PM PST 24
Finished Jan 21 08:25:46 PM PST 24
Peak memory 210768 kb
Host smart-86bb2b7d-454e-4b68-ad09-a56eaf1f473c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154490858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.4154490858
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.4260126778
Short name T727
Test name
Test status
Simulation time 363246084 ps
CPU time 5.85 seconds
Started Jan 21 08:25:45 PM PST 24
Finished Jan 21 08:25:52 PM PST 24
Peak memory 243516 kb
Host smart-e52622c8-e1ca-46b1-9700-7a89e3621a4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260126778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.4260126778
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.1300703503
Short name T772
Test name
Test status
Simulation time 8038940574 ps
CPU time 127.59 seconds
Started Jan 21 08:25:47 PM PST 24
Finished Jan 21 08:27:58 PM PST 24
Peak memory 881836 kb
Host smart-96b79742-df7f-43d7-93e0-e0f4f5e406f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300703503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.1300703503
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.3990534927
Short name T1211
Test name
Test status
Simulation time 13405465260 ps
CPU time 517.74 seconds
Started Jan 21 08:25:37 PM PST 24
Finished Jan 21 08:34:16 PM PST 24
Peak memory 1840136 kb
Host smart-ee56a5d2-72d6-4292-95d8-fcc932db29fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990534927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.3990534927
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.2020239309
Short name T618
Test name
Test status
Simulation time 688025368 ps
CPU time 0.76 seconds
Started Jan 21 08:25:44 PM PST 24
Finished Jan 21 08:25:46 PM PST 24
Peak memory 201452 kb
Host smart-603f8b46-61de-4417-b2bd-f3d12001a482
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020239309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.2020239309
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.2939563710
Short name T949
Test name
Test status
Simulation time 184885440 ps
CPU time 4.9 seconds
Started Jan 21 08:25:45 PM PST 24
Finished Jan 21 08:25:51 PM PST 24
Peak memory 235984 kb
Host smart-cc20cd02-3fa3-4199-ac5c-8de8ccdeb2b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939563710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.2939563710
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.1616750556
Short name T619
Test name
Test status
Simulation time 12303813999 ps
CPU time 316.23 seconds
Started Jan 21 08:25:38 PM PST 24
Finished Jan 21 08:30:55 PM PST 24
Peak memory 970320 kb
Host smart-816988e3-ee2e-4152-946c-635f0667e5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616750556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.1616750556
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.519470029
Short name T1243
Test name
Test status
Simulation time 9187371339 ps
CPU time 59.4 seconds
Started Jan 21 08:25:59 PM PST 24
Finished Jan 21 08:27:00 PM PST 24
Peak memory 277776 kb
Host smart-9544f2ae-b452-42d1-b6d3-a8adc79a159d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519470029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.519470029
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.1930384777
Short name T1250
Test name
Test status
Simulation time 17101447 ps
CPU time 0.65 seconds
Started Jan 21 08:25:38 PM PST 24
Finished Jan 21 08:25:39 PM PST 24
Peak memory 201432 kb
Host smart-95070761-9b31-4ea6-bcf1-ba84f2a14f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930384777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.1930384777
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.3947491763
Short name T684
Test name
Test status
Simulation time 5253630140 ps
CPU time 87.74 seconds
Started Jan 21 08:25:47 PM PST 24
Finished Jan 21 08:27:20 PM PST 24
Peak memory 271596 kb
Host smart-8875ae57-67f0-4d93-a6ed-c7699fb161ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947491763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.3947491763
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_rx_oversample.3554588348
Short name T550
Test name
Test status
Simulation time 3093432303 ps
CPU time 240.96 seconds
Started Jan 21 08:25:37 PM PST 24
Finished Jan 21 08:29:40 PM PST 24
Peak memory 414004 kb
Host smart-cbbe76fa-2464-403c-b03a-9c44d95e89fb
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554588348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_rx_oversample
.3554588348
Directory /workspace/16.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.1666232564
Short name T1390
Test name
Test status
Simulation time 10303795060 ps
CPU time 56.19 seconds
Started Jan 21 08:25:38 PM PST 24
Finished Jan 21 08:26:35 PM PST 24
Peak memory 275676 kb
Host smart-1b445812-d87a-4bdf-be21-e97659e1a7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666232564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.1666232564
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.4181019203
Short name T1444
Test name
Test status
Simulation time 1367542495 ps
CPU time 17.25 seconds
Started Jan 21 08:25:46 PM PST 24
Finished Jan 21 08:26:05 PM PST 24
Peak memory 216092 kb
Host smart-6d2aaf25-49b2-4546-8b1a-9e3db8c084af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181019203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.4181019203
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.882156435
Short name T1476
Test name
Test status
Simulation time 3165344617 ps
CPU time 3.39 seconds
Started Jan 21 08:26:01 PM PST 24
Finished Jan 21 08:26:05 PM PST 24
Peak memory 202640 kb
Host smart-ec961433-c0ef-4fc3-b342-a8b2377df700
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882156435 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.882156435
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.95363694
Short name T1339
Test name
Test status
Simulation time 10048053328 ps
CPU time 61.14 seconds
Started Jan 21 08:25:56 PM PST 24
Finished Jan 21 08:26:58 PM PST 24
Peak memory 464672 kb
Host smart-3d7229c5-c34f-4899-b24b-276d9e18fc67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95363694 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_fifo_reset_acq.95363694
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.2457666095
Short name T612
Test name
Test status
Simulation time 10723430273 ps
CPU time 15.55 seconds
Started Jan 21 08:25:55 PM PST 24
Finished Jan 21 08:26:11 PM PST 24
Peak memory 310636 kb
Host smart-0e1158de-7251-4652-9772-3e863d0796c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457666095 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.2457666095
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.124347648
Short name T1147
Test name
Test status
Simulation time 2156078794 ps
CPU time 3.02 seconds
Started Jan 21 08:26:01 PM PST 24
Finished Jan 21 08:26:05 PM PST 24
Peak memory 202700 kb
Host smart-c37c3b7a-6002-4f85-9181-10a997099657
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124347648 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.i2c_target_hrst.124347648
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.2709359390
Short name T1040
Test name
Test status
Simulation time 943822046 ps
CPU time 4.7 seconds
Started Jan 21 08:50:45 PM PST 24
Finished Jan 21 08:51:15 PM PST 24
Peak memory 202560 kb
Host smart-d7e45531-a177-44ee-aa6d-5f05be78b41e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709359390 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.2709359390
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.3359564089
Short name T375
Test name
Test status
Simulation time 64670788491 ps
CPU time 1903.85 seconds
Started Jan 21 08:25:55 PM PST 24
Finished Jan 21 08:57:40 PM PST 24
Peak memory 7504196 kb
Host smart-5ab3f6e9-ea7d-4996-9f98-49aa5c6a9cf8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359564089 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.3359564089
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_perf.3409057288
Short name T1003
Test name
Test status
Simulation time 3403266045 ps
CPU time 4.91 seconds
Started Jan 21 08:25:55 PM PST 24
Finished Jan 21 08:26:01 PM PST 24
Peak memory 202588 kb
Host smart-727f13f0-65d7-4eab-90cb-75a11fcea9b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409057288 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_perf.3409057288
Directory /workspace/16.i2c_target_perf/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.3860226085
Short name T1312
Test name
Test status
Simulation time 5658647947 ps
CPU time 40.71 seconds
Started Jan 21 08:25:46 PM PST 24
Finished Jan 21 08:26:28 PM PST 24
Peak memory 202604 kb
Host smart-84c61ad4-5457-4bad-b31c-862d82ee0867
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860226085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.3860226085
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.4223583456
Short name T1143
Test name
Test status
Simulation time 2985599067 ps
CPU time 29.03 seconds
Started Jan 21 08:25:46 PM PST 24
Finished Jan 21 08:26:17 PM PST 24
Peak memory 221660 kb
Host smart-ba924783-c3da-4bfb-973b-d0a46d7e95de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223583456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.4223583456
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.2820602373
Short name T435
Test name
Test status
Simulation time 43576708129 ps
CPU time 2635.54 seconds
Started Jan 21 09:11:15 PM PST 24
Finished Jan 21 09:55:20 PM PST 24
Peak memory 9658492 kb
Host smart-43ab7870-19f0-42e5-a80a-c863b33f6d9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820602373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.2820602373
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.1235314548
Short name T448
Test name
Test status
Simulation time 13071888233 ps
CPU time 1243.2 seconds
Started Jan 21 09:56:49 PM PST 24
Finished Jan 21 10:17:40 PM PST 24
Peak memory 2636112 kb
Host smart-1bc91fd6-205c-4c6c-b1f1-f07d3157e754
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235314548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.1235314548
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.2002070206
Short name T808
Test name
Test status
Simulation time 3802901705 ps
CPU time 7.86 seconds
Started Jan 21 09:23:10 PM PST 24
Finished Jan 21 09:23:21 PM PST 24
Peak memory 202640 kb
Host smart-3fec54ca-6b84-4ead-8778-ba8314ce42a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002070206 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.2002070206
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_ovf.1434799427
Short name T941
Test name
Test status
Simulation time 4452346861 ps
CPU time 61.33 seconds
Started Jan 21 08:25:55 PM PST 24
Finished Jan 21 08:26:57 PM PST 24
Peak memory 230004 kb
Host smart-39d584be-63ee-4e30-b068-3f7e8a8faf93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434799427 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_tx_ovf.1434799427
Directory /workspace/16.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/16.i2c_target_unexp_stop.745390724
Short name T996
Test name
Test status
Simulation time 16984978928 ps
CPU time 6.84 seconds
Started Jan 21 08:25:54 PM PST 24
Finished Jan 21 08:26:02 PM PST 24
Peak memory 202628 kb
Host smart-2f866b17-708c-4419-96df-aeb4a27d3aaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745390724 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_unexp_stop.745390724
Directory /workspace/16.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/17.i2c_alert_test.3202136272
Short name T1358
Test name
Test status
Simulation time 38820666 ps
CPU time 0.59 seconds
Started Jan 21 08:26:34 PM PST 24
Finished Jan 21 08:26:36 PM PST 24
Peak memory 201140 kb
Host smart-99461dcd-84a2-4023-94de-034f112cc8b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202136272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.3202136272
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.3577081013
Short name T371
Test name
Test status
Simulation time 43433675 ps
CPU time 1.22 seconds
Started Jan 21 08:26:18 PM PST 24
Finished Jan 21 08:26:20 PM PST 24
Peak memory 218800 kb
Host smart-a16ab53d-b31b-47f7-880b-d5ec40b5d748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577081013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.3577081013
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.2258041249
Short name T863
Test name
Test status
Simulation time 499627889 ps
CPU time 12.38 seconds
Started Jan 21 08:26:12 PM PST 24
Finished Jan 21 08:26:26 PM PST 24
Peak memory 246280 kb
Host smart-19e9874c-6f59-4859-9e5a-53acf8e48f2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258041249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.2258041249
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.724397004
Short name T694
Test name
Test status
Simulation time 3300038672 ps
CPU time 299.97 seconds
Started Jan 21 08:26:14 PM PST 24
Finished Jan 21 08:31:16 PM PST 24
Peak memory 990168 kb
Host smart-2dc60c40-7476-4749-b233-0a49cf890616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724397004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.724397004
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.2606136739
Short name T522
Test name
Test status
Simulation time 6025716492 ps
CPU time 953.98 seconds
Started Jan 21 08:26:10 PM PST 24
Finished Jan 21 08:42:07 PM PST 24
Peak memory 1698772 kb
Host smart-5c6204b9-83d7-4728-ab58-f6813f15bfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606136739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.2606136739
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.863983482
Short name T51
Test name
Test status
Simulation time 109577652 ps
CPU time 1.03 seconds
Started Jan 21 08:26:07 PM PST 24
Finished Jan 21 08:26:10 PM PST 24
Peak memory 202496 kb
Host smart-db4259bb-8c9e-4e84-9db3-db24cfd7e80d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863983482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fm
t.863983482
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.1043686626
Short name T1106
Test name
Test status
Simulation time 760731049 ps
CPU time 11.88 seconds
Started Jan 21 08:26:08 PM PST 24
Finished Jan 21 08:26:21 PM PST 24
Peak memory 239308 kb
Host smart-5b12808d-94b6-4a8f-a9e6-667e630ae67a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043686626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.1043686626
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.625412376
Short name T367
Test name
Test status
Simulation time 10950437892 ps
CPU time 274.91 seconds
Started Jan 21 08:26:08 PM PST 24
Finished Jan 21 08:30:45 PM PST 24
Peak memory 1545480 kb
Host smart-bedb5d12-b4bd-415c-83ce-26fea9169396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625412376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.625412376
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.3936944409
Short name T13
Test name
Test status
Simulation time 2965394587 ps
CPU time 32.63 seconds
Started Jan 21 08:26:33 PM PST 24
Finished Jan 21 08:27:07 PM PST 24
Peak memory 234704 kb
Host smart-21798d89-0646-4384-8a82-5dcbdbe50893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936944409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.3936944409
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.1629891612
Short name T610
Test name
Test status
Simulation time 16894375 ps
CPU time 0.68 seconds
Started Jan 21 08:26:08 PM PST 24
Finished Jan 21 08:26:10 PM PST 24
Peak memory 201524 kb
Host smart-78a74614-929e-461f-a60f-3076c417061c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629891612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.1629891612
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.2406036385
Short name T787
Test name
Test status
Simulation time 2877556634 ps
CPU time 133.36 seconds
Started Jan 21 08:26:10 PM PST 24
Finished Jan 21 08:28:25 PM PST 24
Peak memory 218956 kb
Host smart-d02917d1-4b9a-42b3-8ddd-2c160ed6d845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406036385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.2406036385
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_rx_oversample.2521492962
Short name T1049
Test name
Test status
Simulation time 10265774043 ps
CPU time 146.63 seconds
Started Jan 21 08:26:10 PM PST 24
Finished Jan 21 08:28:39 PM PST 24
Peak memory 331644 kb
Host smart-a4152f3b-8734-42f2-838b-f19383d388ce
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521492962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_rx_oversample
.2521492962
Directory /workspace/17.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.3101800442
Short name T219
Test name
Test status
Simulation time 1489634325 ps
CPU time 78.74 seconds
Started Jan 21 08:26:09 PM PST 24
Finished Jan 21 08:27:30 PM PST 24
Peak memory 226132 kb
Host smart-f2888749-74f6-4363-af35-5d1a7aa11bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101800442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.3101800442
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.3962642941
Short name T1108
Test name
Test status
Simulation time 27438390271 ps
CPU time 2837 seconds
Started Jan 21 08:26:19 PM PST 24
Finished Jan 21 09:13:37 PM PST 24
Peak memory 2459928 kb
Host smart-4025df69-2670-4399-850b-a561eef6588c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962642941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.3962642941
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.911907188
Short name T907
Test name
Test status
Simulation time 2113958239 ps
CPU time 47.42 seconds
Started Jan 21 08:26:20 PM PST 24
Finished Jan 21 08:27:08 PM PST 24
Peak memory 218644 kb
Host smart-b29e7cec-dbba-4471-b71e-c0d6733d3479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911907188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.911907188
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.1893454555
Short name T498
Test name
Test status
Simulation time 2795340142 ps
CPU time 3.4 seconds
Started Jan 21 08:26:31 PM PST 24
Finished Jan 21 08:26:35 PM PST 24
Peak memory 202836 kb
Host smart-8813cb5f-1406-48ef-a9a4-7dce1a569b06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893454555 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.1893454555
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.2237228159
Short name T353
Test name
Test status
Simulation time 10070222257 ps
CPU time 73.88 seconds
Started Jan 21 08:26:29 PM PST 24
Finished Jan 21 08:27:43 PM PST 24
Peak memory 609644 kb
Host smart-e8ec48a9-3490-4cc5-b54d-2394f3225b9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237228159 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.2237228159
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.85610021
Short name T703
Test name
Test status
Simulation time 2473346873 ps
CPU time 2.96 seconds
Started Jan 21 08:26:31 PM PST 24
Finished Jan 21 08:26:35 PM PST 24
Peak memory 202724 kb
Host smart-f22a5f5b-a9da-4568-a874-9250b6d7659b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85610021 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.i2c_target_hrst.85610021
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.3132458700
Short name T551
Test name
Test status
Simulation time 1199514015 ps
CPU time 5.14 seconds
Started Jan 21 08:26:25 PM PST 24
Finished Jan 21 08:26:30 PM PST 24
Peak memory 202572 kb
Host smart-e8cbbe6c-819d-46a1-afb6-751653cd396b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132458700 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.3132458700
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.3316373626
Short name T944
Test name
Test status
Simulation time 3359088352 ps
CPU time 17.61 seconds
Started Jan 21 08:26:23 PM PST 24
Finished Jan 21 08:26:42 PM PST 24
Peak memory 564760 kb
Host smart-45a93d76-bbf9-4e7a-b094-c9366e991109
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316373626 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.3316373626
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_perf.3485823381
Short name T889
Test name
Test status
Simulation time 871728476 ps
CPU time 5.58 seconds
Started Jan 21 08:26:24 PM PST 24
Finished Jan 21 08:26:31 PM PST 24
Peak memory 210916 kb
Host smart-6c7f6326-42c5-4f61-bf04-47dadcaa3fd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485823381 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_perf.3485823381
Directory /workspace/17.i2c_target_perf/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.360721960
Short name T988
Test name
Test status
Simulation time 2154700491 ps
CPU time 58.1 seconds
Started Jan 21 08:26:18 PM PST 24
Finished Jan 21 08:27:17 PM PST 24
Peak memory 202628 kb
Host smart-30378826-a710-489b-8a44-bf3c50c026da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360721960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_tar
get_smoke.360721960
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_all.564908250
Short name T556
Test name
Test status
Simulation time 37020492854 ps
CPU time 38.8 seconds
Started Jan 21 08:54:06 PM PST 24
Finished Jan 21 08:54:56 PM PST 24
Peak memory 219724 kb
Host smart-8cdf92f1-c53b-4951-a3f5-a3aae8d23836
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564908250 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.i2c_target_stress_all.564908250
Directory /workspace/17.i2c_target_stress_all/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.3570467066
Short name T764
Test name
Test status
Simulation time 660853254 ps
CPU time 4.88 seconds
Started Jan 21 08:26:17 PM PST 24
Finished Jan 21 08:26:23 PM PST 24
Peak memory 202572 kb
Host smart-fe8a30d7-e6b7-4fb2-a1d1-91c0a45d3657
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570467066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.3570467066
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.1323208720
Short name T1466
Test name
Test status
Simulation time 34290056211 ps
CPU time 695.38 seconds
Started Jan 21 08:26:21 PM PST 24
Finished Jan 21 08:37:57 PM PST 24
Peak memory 1780148 kb
Host smart-8ddde092-e982-4e23-ae02-bf52dc35ca91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323208720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.1323208720
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.1525286234
Short name T1202
Test name
Test status
Simulation time 3677660203 ps
CPU time 8.47 seconds
Started Jan 21 08:26:29 PM PST 24
Finished Jan 21 08:26:38 PM PST 24
Peak memory 208544 kb
Host smart-e347b9bd-bb27-4112-923c-bccf63098849
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525286234 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.1525286234
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_ovf.3573882780
Short name T676
Test name
Test status
Simulation time 5112382502 ps
CPU time 42.77 seconds
Started Jan 21 08:26:22 PM PST 24
Finished Jan 21 08:27:06 PM PST 24
Peak memory 211692 kb
Host smart-ded17e23-26f3-48cc-8b64-26a8d576cd59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573882780 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_tx_ovf.3573882780
Directory /workspace/17.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/17.i2c_target_unexp_stop.2740955375
Short name T991
Test name
Test status
Simulation time 1371476356 ps
CPU time 4.13 seconds
Started Jan 21 08:26:23 PM PST 24
Finished Jan 21 08:26:28 PM PST 24
Peak memory 202572 kb
Host smart-519e97ba-6aa6-4108-80c8-c781c22615d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740955375 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.i2c_target_unexp_stop.2740955375
Directory /workspace/17.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/18.i2c_alert_test.2121915141
Short name T272
Test name
Test status
Simulation time 21421859 ps
CPU time 0.65 seconds
Started Jan 21 08:27:04 PM PST 24
Finished Jan 21 08:27:06 PM PST 24
Peak memory 201092 kb
Host smart-7beae417-25f1-4113-bbc9-1d2ff54d68f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121915141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.2121915141
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.3876150473
Short name T46
Test name
Test status
Simulation time 108553617 ps
CPU time 1.26 seconds
Started Jan 21 08:26:43 PM PST 24
Finished Jan 21 08:26:45 PM PST 24
Peak memory 211932 kb
Host smart-95d3981a-95d4-49de-b849-165011348cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876150473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.3876150473
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.334831398
Short name T820
Test name
Test status
Simulation time 274706164 ps
CPU time 13.19 seconds
Started Jan 21 08:26:37 PM PST 24
Finished Jan 21 08:26:51 PM PST 24
Peak memory 251808 kb
Host smart-b606995f-06e8-44b4-a403-8e25fb0d9a37
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334831398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empt
y.334831398
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.1360426017
Short name T1050
Test name
Test status
Simulation time 17059044266 ps
CPU time 69.53 seconds
Started Jan 21 08:26:37 PM PST 24
Finished Jan 21 08:27:48 PM PST 24
Peak memory 714112 kb
Host smart-53ec925d-1830-487f-af7f-2bb15a37ef6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360426017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.1360426017
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.3962395301
Short name T107
Test name
Test status
Simulation time 25605259473 ps
CPU time 959.13 seconds
Started Jan 21 08:47:17 PM PST 24
Finished Jan 21 09:03:46 PM PST 24
Peak memory 1684020 kb
Host smart-f252e305-d88c-4a3b-8b69-f7a2bd29e5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962395301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.3962395301
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.3794137648
Short name T751
Test name
Test status
Simulation time 200207229 ps
CPU time 0.88 seconds
Started Jan 21 08:26:40 PM PST 24
Finished Jan 21 08:26:42 PM PST 24
Peak memory 202312 kb
Host smart-0f907acb-2bfd-4ebc-9b40-7bd7ee7a9ac7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794137648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.3794137648
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.1605892681
Short name T667
Test name
Test status
Simulation time 824404046 ps
CPU time 5.51 seconds
Started Jan 21 08:26:37 PM PST 24
Finished Jan 21 08:26:44 PM PST 24
Peak memory 202536 kb
Host smart-a42bbaaa-a8fa-4ce3-b956-82d58d0977d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605892681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.1605892681
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.494899974
Short name T1349
Test name
Test status
Simulation time 49988605917 ps
CPU time 316.31 seconds
Started Jan 21 08:46:20 PM PST 24
Finished Jan 21 08:52:26 PM PST 24
Peak memory 1397556 kb
Host smart-bf638790-b019-4502-9a76-a9ff86de0ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494899974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.494899974
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_override.1216639299
Short name T256
Test name
Test status
Simulation time 27858149 ps
CPU time 0.64 seconds
Started Jan 21 08:26:33 PM PST 24
Finished Jan 21 08:26:35 PM PST 24
Peak memory 201512 kb
Host smart-fdf9ec66-0cf0-4799-a45c-ad11fd7d3762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216639299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.1216639299
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.3278308249
Short name T104
Test name
Test status
Simulation time 756876249 ps
CPU time 4.4 seconds
Started Jan 21 08:26:35 PM PST 24
Finished Jan 21 08:26:40 PM PST 24
Peak memory 210764 kb
Host smart-38223a55-0279-4e36-a114-803c3ae18cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278308249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.3278308249
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_rx_oversample.2196291462
Short name T484
Test name
Test status
Simulation time 8732901454 ps
CPU time 134.06 seconds
Started Jan 21 08:26:33 PM PST 24
Finished Jan 21 08:28:48 PM PST 24
Peak memory 339032 kb
Host smart-574de318-fd8c-40dc-9e54-b553387ce8ee
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196291462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_rx_oversample
.2196291462
Directory /workspace/18.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.1096216658
Short name T1326
Test name
Test status
Simulation time 4169047982 ps
CPU time 67.63 seconds
Started Jan 21 08:26:33 PM PST 24
Finished Jan 21 08:27:42 PM PST 24
Peak memory 292424 kb
Host smart-9a33159e-5470-4871-99df-84a345c966c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096216658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.1096216658
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.2160912482
Short name T1404
Test name
Test status
Simulation time 33725570769 ps
CPU time 710.85 seconds
Started Jan 21 08:26:41 PM PST 24
Finished Jan 21 08:38:33 PM PST 24
Peak memory 659320 kb
Host smart-925eca11-3ffc-4659-8e28-89b88191733f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160912482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.2160912482
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.4034988049
Short name T211
Test name
Test status
Simulation time 1779592035 ps
CPU time 39.5 seconds
Started Jan 21 08:26:41 PM PST 24
Finished Jan 21 08:27:22 PM PST 24
Peak memory 210720 kb
Host smart-2ab072b2-0999-42fc-9117-4306f096c6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034988049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.4034988049
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.2662654597
Short name T1282
Test name
Test status
Simulation time 2847837965 ps
CPU time 3.37 seconds
Started Jan 21 08:27:01 PM PST 24
Finished Jan 21 08:27:05 PM PST 24
Peak memory 202604 kb
Host smart-405c7f39-36c2-4800-a25b-ef27a9dec22f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662654597 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.2662654597
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.2979498967
Short name T1162
Test name
Test status
Simulation time 10374176989 ps
CPU time 12.33 seconds
Started Jan 21 08:26:56 PM PST 24
Finished Jan 21 08:27:09 PM PST 24
Peak memory 286376 kb
Host smart-75ff60c2-29c3-4e30-82f9-eaa79c26a158
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979498967 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.2979498967
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.3114942289
Short name T673
Test name
Test status
Simulation time 10068171062 ps
CPU time 29.53 seconds
Started Jan 21 08:26:59 PM PST 24
Finished Jan 21 08:27:30 PM PST 24
Peak memory 429096 kb
Host smart-2ea77926-9e66-44d3-b071-f1f9394a6dfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114942289 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.3114942289
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.2333607727
Short name T548
Test name
Test status
Simulation time 307888153 ps
CPU time 2.09 seconds
Started Jan 21 08:27:02 PM PST 24
Finished Jan 21 08:27:05 PM PST 24
Peak memory 202584 kb
Host smart-3b021782-c284-48de-855c-d2992b169c14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333607727 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.2333607727
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.1425380484
Short name T573
Test name
Test status
Simulation time 12633253619 ps
CPU time 4.19 seconds
Started Jan 21 08:49:09 PM PST 24
Finished Jan 21 08:49:19 PM PST 24
Peak memory 203016 kb
Host smart-6b781d6e-da4f-4eaa-95f0-6d76a9b1689c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425380484 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.1425380484
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.1756039660
Short name T908
Test name
Test status
Simulation time 18839589814 ps
CPU time 340.4 seconds
Started Jan 21 08:26:51 PM PST 24
Finished Jan 21 08:32:32 PM PST 24
Peak memory 2291820 kb
Host smart-68d37601-77e9-4217-a983-b1bcee5fbffd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756039660 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.1756039660
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_perf.3122423798
Short name T809
Test name
Test status
Simulation time 713066454 ps
CPU time 4.46 seconds
Started Jan 21 08:26:55 PM PST 24
Finished Jan 21 08:27:00 PM PST 24
Peak memory 204140 kb
Host smart-b4e72489-d4b3-4d1c-bd90-0fcb6f6d7179
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122423798 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_perf.3122423798
Directory /workspace/18.i2c_target_perf/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.1097371021
Short name T1325
Test name
Test status
Simulation time 5688341583 ps
CPU time 12.29 seconds
Started Jan 21 08:26:44 PM PST 24
Finished Jan 21 08:26:57 PM PST 24
Peak memory 202632 kb
Host smart-d285b45b-d857-474f-9a52-c41a5cd380c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097371021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.1097371021
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_all.2615669868
Short name T1241
Test name
Test status
Simulation time 39877863487 ps
CPU time 168.1 seconds
Started Jan 21 08:26:59 PM PST 24
Finished Jan 21 08:29:48 PM PST 24
Peak memory 1296104 kb
Host smart-a40e93c0-d592-402a-8bce-815c88167123
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615669868 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.i2c_target_stress_all.2615669868
Directory /workspace/18.i2c_target_stress_all/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.482965386
Short name T971
Test name
Test status
Simulation time 409606551 ps
CPU time 6.44 seconds
Started Jan 21 09:05:17 PM PST 24
Finished Jan 21 09:05:29 PM PST 24
Peak memory 202576 kb
Host smart-9fd67363-abe3-4578-b7a7-15559c4f5731
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482965386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_rd.482965386
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.2501659200
Short name T57
Test name
Test status
Simulation time 43615627172 ps
CPU time 1138.45 seconds
Started Jan 21 09:45:40 PM PST 24
Finished Jan 21 10:04:43 PM PST 24
Peak memory 2116828 kb
Host smart-dc3bd7b1-0ab6-4b07-b932-498f4b0ad836
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501659200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.2501659200
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.4293955301
Short name T1429
Test name
Test status
Simulation time 1625181948 ps
CPU time 7.31 seconds
Started Jan 21 08:26:57 PM PST 24
Finished Jan 21 08:27:05 PM PST 24
Peak memory 202552 kb
Host smart-04547065-6684-40e7-af60-0e6d6b670090
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293955301 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.4293955301
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_ovf.1561455757
Short name T790
Test name
Test status
Simulation time 2664903298 ps
CPU time 48.94 seconds
Started Jan 21 08:26:58 PM PST 24
Finished Jan 21 08:27:48 PM PST 24
Peak memory 217608 kb
Host smart-2973c3f4-0b8d-4357-89cc-ede949d43217
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561455757 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_tx_ovf.1561455757
Directory /workspace/18.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/18.i2c_target_unexp_stop.2215133511
Short name T1329
Test name
Test status
Simulation time 10675527325 ps
CPU time 6.64 seconds
Started Jan 21 08:26:54 PM PST 24
Finished Jan 21 08:27:02 PM PST 24
Peak memory 202716 kb
Host smart-338f937b-4aa7-4859-874e-bf346e6d1737
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215133511 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.i2c_target_unexp_stop.2215133511
Directory /workspace/18.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/19.i2c_alert_test.1842239044
Short name T1268
Test name
Test status
Simulation time 43250311 ps
CPU time 0.63 seconds
Started Jan 21 08:27:34 PM PST 24
Finished Jan 21 08:27:36 PM PST 24
Peak memory 201116 kb
Host smart-5fd5b12a-e3e8-42be-82a0-26c8be171531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842239044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.1842239044
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.1350354015
Short name T1522
Test name
Test status
Simulation time 42139223 ps
CPU time 1.91 seconds
Started Jan 21 08:27:21 PM PST 24
Finished Jan 21 08:27:24 PM PST 24
Peak memory 210724 kb
Host smart-2f13773a-dbae-4033-af9b-8f11ce1c11da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350354015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.1350354015
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.647087455
Short name T1265
Test name
Test status
Simulation time 382061997 ps
CPU time 7.69 seconds
Started Jan 21 10:03:50 PM PST 24
Finished Jan 21 10:03:59 PM PST 24
Peak memory 282664 kb
Host smart-e6ae4391-02d4-4004-9554-bcf169f42b47
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647087455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empt
y.647087455
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.3965354045
Short name T1209
Test name
Test status
Simulation time 2085434944 ps
CPU time 51.96 seconds
Started Jan 21 08:27:12 PM PST 24
Finished Jan 21 08:28:05 PM PST 24
Peak memory 359236 kb
Host smart-5225a567-9b0b-471d-9bae-954afc416c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965354045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.3965354045
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.791029072
Short name T1014
Test name
Test status
Simulation time 6744565922 ps
CPU time 507.43 seconds
Started Jan 21 08:33:53 PM PST 24
Finished Jan 21 08:42:21 PM PST 24
Peak memory 1793320 kb
Host smart-a9294eb1-264a-444c-a5da-966bb1717883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791029072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.791029072
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.1061002986
Short name T998
Test name
Test status
Simulation time 546667962 ps
CPU time 1.03 seconds
Started Jan 21 08:27:08 PM PST 24
Finished Jan 21 08:27:10 PM PST 24
Peak memory 202288 kb
Host smart-14e618d4-69c6-45d4-acae-8d3038619d32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061002986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.1061002986
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.625220869
Short name T1141
Test name
Test status
Simulation time 250688122 ps
CPU time 3.6 seconds
Started Jan 21 08:27:13 PM PST 24
Finished Jan 21 08:27:18 PM PST 24
Peak memory 221224 kb
Host smart-71ad44a3-3f8e-4480-9769-831b74417295
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625220869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.
625220869
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.1832929428
Short name T466
Test name
Test status
Simulation time 2213477955 ps
CPU time 128.74 seconds
Started Jan 21 08:27:31 PM PST 24
Finished Jan 21 08:29:41 PM PST 24
Peak memory 259688 kb
Host smart-1b08f8a4-903e-4015-81af-e98a8450d178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832929428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.1832929428
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.1007564402
Short name T6
Test name
Test status
Simulation time 19319020 ps
CPU time 0.65 seconds
Started Jan 21 09:10:57 PM PST 24
Finished Jan 21 09:11:12 PM PST 24
Peak memory 201476 kb
Host smart-7dc958f3-f95d-49be-8214-8595502af24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007564402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.1007564402
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.2357226836
Short name T455
Test name
Test status
Simulation time 2874110060 ps
CPU time 143.41 seconds
Started Jan 21 08:27:20 PM PST 24
Finished Jan 21 08:29:44 PM PST 24
Peak memory 218928 kb
Host smart-f33d0897-44d2-4692-87e9-5d95b6980d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357226836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.2357226836
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_rx_oversample.2098340548
Short name T697
Test name
Test status
Simulation time 16462973258 ps
CPU time 163.75 seconds
Started Jan 21 08:27:04 PM PST 24
Finished Jan 21 08:29:48 PM PST 24
Peak memory 283500 kb
Host smart-66162662-1390-4dfa-bb45-eb7fe2eca446
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098340548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_rx_oversample
.2098340548
Directory /workspace/19.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.2012870557
Short name T645
Test name
Test status
Simulation time 6518300647 ps
CPU time 40.34 seconds
Started Jan 21 08:27:06 PM PST 24
Finished Jan 21 08:27:47 PM PST 24
Peak memory 283124 kb
Host smart-3588da20-12aa-4926-a19b-2762241901a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012870557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2012870557
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.2867862336
Short name T1454
Test name
Test status
Simulation time 4108031662 ps
CPU time 17.88 seconds
Started Jan 21 08:27:18 PM PST 24
Finished Jan 21 08:27:37 PM PST 24
Peak memory 227272 kb
Host smart-563febe4-a1f5-4ba8-9408-e2ed45ac20b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867862336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.2867862336
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.1500393684
Short name T1507
Test name
Test status
Simulation time 733485950 ps
CPU time 3.44 seconds
Started Jan 21 09:01:24 PM PST 24
Finished Jan 21 09:01:49 PM PST 24
Peak memory 202604 kb
Host smart-941c3d88-e63a-43a9-963d-d11a29b653d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500393684 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.1500393684
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.3687522392
Short name T633
Test name
Test status
Simulation time 10256741654 ps
CPU time 11.5 seconds
Started Jan 21 08:27:27 PM PST 24
Finished Jan 21 08:27:39 PM PST 24
Peak memory 264800 kb
Host smart-10c0d703-b6a1-482b-85e2-fad3a954aff5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687522392 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.3687522392
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.1066081135
Short name T564
Test name
Test status
Simulation time 10135773971 ps
CPU time 12.04 seconds
Started Jan 21 08:49:10 PM PST 24
Finished Jan 21 08:49:28 PM PST 24
Peak memory 291420 kb
Host smart-917309da-abb8-4ec0-b832-54888d00b438
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066081135 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.1066081135
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.1829981859
Short name T489
Test name
Test status
Simulation time 538958375 ps
CPU time 2.54 seconds
Started Jan 21 08:27:31 PM PST 24
Finished Jan 21 08:27:34 PM PST 24
Peak memory 202536 kb
Host smart-0f46540d-954a-4ca7-bfa7-06b9a2a167d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829981859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.1829981859
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.390500167
Short name T174
Test name
Test status
Simulation time 1010192034 ps
CPU time 4.21 seconds
Started Jan 21 08:27:24 PM PST 24
Finished Jan 21 08:27:29 PM PST 24
Peak memory 202552 kb
Host smart-c1e7f929-940f-4bf0-a3c1-7284904be0db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390500167 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.390500167
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.3292840704
Short name T398
Test name
Test status
Simulation time 4518311675 ps
CPU time 42.58 seconds
Started Jan 21 08:27:24 PM PST 24
Finished Jan 21 08:28:08 PM PST 24
Peak memory 916248 kb
Host smart-e39ea421-004e-4d9a-8a4a-faf72b1e72b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292840704 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.3292840704
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_perf.1575728516
Short name T647
Test name
Test status
Simulation time 3073251086 ps
CPU time 4.57 seconds
Started Jan 21 08:27:26 PM PST 24
Finished Jan 21 08:27:32 PM PST 24
Peak memory 202648 kb
Host smart-63f01d49-0c83-4ffb-9b2e-a89c412c4ac7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575728516 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_perf.1575728516
Directory /workspace/19.i2c_target_perf/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.2225419870
Short name T232
Test name
Test status
Simulation time 1579118912 ps
CPU time 42.76 seconds
Started Jan 21 08:27:20 PM PST 24
Finished Jan 21 08:28:03 PM PST 24
Peak memory 202540 kb
Host smart-d0e5b8f9-06b5-470d-a0ec-47a1ad63c1a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225419870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.2225419870
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_all.1142354931
Short name T719
Test name
Test status
Simulation time 73321396369 ps
CPU time 1989.8 seconds
Started Jan 21 08:48:02 PM PST 24
Finished Jan 21 09:21:32 PM PST 24
Peak memory 6806536 kb
Host smart-358d91ef-90e7-4074-827b-82c823217d65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142354931 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_target_stress_all.1142354931
Directory /workspace/19.i2c_target_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.2410014495
Short name T329
Test name
Test status
Simulation time 6419322218 ps
CPU time 61.65 seconds
Started Jan 21 08:27:22 PM PST 24
Finished Jan 21 08:28:24 PM PST 24
Peak memory 202712 kb
Host smart-75009c67-f306-4f8b-9078-99d8852ffce2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410014495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.2410014495
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.1073291162
Short name T244
Test name
Test status
Simulation time 57668004020 ps
CPU time 583.47 seconds
Started Jan 21 08:27:23 PM PST 24
Finished Jan 21 08:37:07 PM PST 24
Peak memory 3514072 kb
Host smart-0b377b82-bc26-4489-976d-fbdb71e9d530
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073291162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.1073291162
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.1113577394
Short name T733
Test name
Test status
Simulation time 31922117154 ps
CPU time 735.65 seconds
Started Jan 21 08:27:25 PM PST 24
Finished Jan 21 08:39:41 PM PST 24
Peak memory 1672120 kb
Host smart-25c5178f-caa6-41ba-99a7-a23617d7721b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113577394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.1113577394
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.2739584597
Short name T819
Test name
Test status
Simulation time 1484202027 ps
CPU time 6.65 seconds
Started Jan 21 08:58:53 PM PST 24
Finished Jan 21 08:59:26 PM PST 24
Peak memory 202552 kb
Host smart-8aaa2fd0-84a1-4de9-8201-53ef3d376d23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739584597 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.2739584597
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_ovf.723244110
Short name T344
Test name
Test status
Simulation time 6675404465 ps
CPU time 44.36 seconds
Started Jan 21 08:27:27 PM PST 24
Finished Jan 21 08:28:12 PM PST 24
Peak memory 227528 kb
Host smart-b538a10e-adaa-456f-82cf-870c8b7554e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723244110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_tx_ovf.723244110
Directory /workspace/19.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/19.i2c_target_unexp_stop.3542542760
Short name T750
Test name
Test status
Simulation time 6461115605 ps
CPU time 6.22 seconds
Started Jan 21 08:27:29 PM PST 24
Finished Jan 21 08:27:36 PM PST 24
Peak memory 203180 kb
Host smart-9a8ddaab-bb0f-4827-9ebd-48747082fbb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542542760 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.i2c_target_unexp_stop.3542542760
Directory /workspace/19.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/2.i2c_alert_test.2701002919
Short name T1005
Test name
Test status
Simulation time 87797882 ps
CPU time 0.66 seconds
Started Jan 21 08:19:16 PM PST 24
Finished Jan 21 08:19:19 PM PST 24
Peak memory 201132 kb
Host smart-0178a306-cbe3-47c7-b9d6-361d328e7ad6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701002919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.2701002919
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.2085053341
Short name T1234
Test name
Test status
Simulation time 56224277 ps
CPU time 1.6 seconds
Started Jan 21 08:18:20 PM PST 24
Finished Jan 21 08:18:28 PM PST 24
Peak memory 202544 kb
Host smart-f6508b18-1ef0-4916-806d-fa513f6f7fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085053341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.2085053341
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.2547316628
Short name T374
Test name
Test status
Simulation time 311484999 ps
CPU time 7.37 seconds
Started Jan 21 08:18:17 PM PST 24
Finished Jan 21 08:18:27 PM PST 24
Peak memory 266532 kb
Host smart-42c3fe4d-0fca-4d27-899d-80c08b357e75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547316628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.2547316628
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.1412332115
Short name T848
Test name
Test status
Simulation time 3101844793 ps
CPU time 44.43 seconds
Started Jan 21 08:18:13 PM PST 24
Finished Jan 21 08:19:00 PM PST 24
Peak memory 467632 kb
Host smart-d22191ba-515b-44ff-aa67-68a25adc9df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412332115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.1412332115
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.2289423043
Short name T351
Test name
Test status
Simulation time 25253396966 ps
CPU time 979.55 seconds
Started Jan 21 08:18:15 PM PST 24
Finished Jan 21 08:34:38 PM PST 24
Peak memory 1742460 kb
Host smart-b112f8b6-eac6-4d18-b353-efa1b26dac2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289423043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.2289423043
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.4285731435
Short name T1083
Test name
Test status
Simulation time 140169437 ps
CPU time 0.91 seconds
Started Jan 21 08:18:12 PM PST 24
Finished Jan 21 08:18:16 PM PST 24
Peak memory 202384 kb
Host smart-fd4ab9f0-0cf9-4082-a73c-a3c3d8bcff0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285731435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.4285731435
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.2198691741
Short name T597
Test name
Test status
Simulation time 718345171 ps
CPU time 10.88 seconds
Started Jan 21 08:18:13 PM PST 24
Finished Jan 21 08:18:26 PM PST 24
Peak memory 235436 kb
Host smart-82da698d-e013-43bb-a84e-a6f5f671ef95
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198691741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
2198691741
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.1147918543
Short name T490
Test name
Test status
Simulation time 4225947224 ps
CPU time 492.17 seconds
Started Jan 21 08:18:13 PM PST 24
Finished Jan 21 08:26:28 PM PST 24
Peak memory 1244312 kb
Host smart-8190781c-9f1c-4d52-b37d-c4ade5ae8781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147918543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.1147918543
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.1547570378
Short name T614
Test name
Test status
Simulation time 3040229279 ps
CPU time 157.62 seconds
Started Jan 21 08:19:08 PM PST 24
Finished Jan 21 08:21:47 PM PST 24
Peak memory 245180 kb
Host smart-6d0bc9dc-17df-4b2a-8776-7b48c513847f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547570378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.1547570378
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.2052411937
Short name T318
Test name
Test status
Simulation time 36950605 ps
CPU time 0.63 seconds
Started Jan 21 08:18:13 PM PST 24
Finished Jan 21 08:18:16 PM PST 24
Peak memory 201504 kb
Host smart-05487536-35d2-41db-8ffb-96e7f0730497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052411937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.2052411937
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.1121362730
Short name T623
Test name
Test status
Simulation time 5274198613 ps
CPU time 266.47 seconds
Started Jan 21 08:18:11 PM PST 24
Finished Jan 21 08:22:41 PM PST 24
Peak memory 218888 kb
Host smart-bcfaffb9-a379-456e-a6ef-3f6ffcd72d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121362730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.1121362730
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_rx_oversample.3659194508
Short name T1038
Test name
Test status
Simulation time 2363429360 ps
CPU time 110.63 seconds
Started Jan 21 08:18:12 PM PST 24
Finished Jan 21 08:20:06 PM PST 24
Peak memory 299132 kb
Host smart-38da9e1e-db0a-4621-adb0-5d4003171153
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659194508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_rx_oversample.
3659194508
Directory /workspace/2.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.1918172405
Short name T302
Test name
Test status
Simulation time 2184939826 ps
CPU time 135.13 seconds
Started Jan 21 09:54:50 PM PST 24
Finished Jan 21 09:57:10 PM PST 24
Peak memory 251424 kb
Host smart-868188a6-9bf9-4a77-8497-c36986f59458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918172405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.1918172405
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.1372185778
Short name T857
Test name
Test status
Simulation time 843685962 ps
CPU time 12.58 seconds
Started Jan 21 08:18:16 PM PST 24
Finished Jan 21 08:18:32 PM PST 24
Peak memory 218412 kb
Host smart-11444501-f88c-4aab-9337-0f9e300f111a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372185778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.1372185778
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.1390988293
Short name T83
Test name
Test status
Simulation time 242232354 ps
CPU time 0.95 seconds
Started Jan 21 08:19:07 PM PST 24
Finished Jan 21 08:19:09 PM PST 24
Peak memory 219652 kb
Host smart-47353241-4622-4a3c-9b60-28301ce007ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390988293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.1390988293
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.2815427955
Short name T958
Test name
Test status
Simulation time 3226573808 ps
CPU time 3.39 seconds
Started Jan 21 08:19:08 PM PST 24
Finished Jan 21 08:19:12 PM PST 24
Peak memory 202636 kb
Host smart-c5b3524a-19aa-4644-ad34-4b824fa26a5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815427955 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.2815427955
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.2862185139
Short name T886
Test name
Test status
Simulation time 11693977777 ps
CPU time 3.62 seconds
Started Jan 21 09:08:09 PM PST 24
Finished Jan 21 09:08:37 PM PST 24
Peak memory 208776 kb
Host smart-f6bac21a-8505-4f38-8feb-a851debb9cea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862185139 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.2862185139
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.250370453
Short name T1279
Test name
Test status
Simulation time 10565991444 ps
CPU time 15.07 seconds
Started Jan 21 10:55:57 PM PST 24
Finished Jan 21 10:56:13 PM PST 24
Peak memory 298808 kb
Host smart-76cb2228-284a-4311-9899-aa823660eb69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250370453 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_fifo_reset_tx.250370453
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.390759262
Short name T153
Test name
Test status
Simulation time 2770207289 ps
CPU time 1.95 seconds
Started Jan 21 08:19:07 PM PST 24
Finished Jan 21 08:19:10 PM PST 24
Peak memory 202688 kb
Host smart-6d5eb8f9-d903-4566-8cd0-c31c41c3f584
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390759262 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.i2c_target_hrst.390759262
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.2092840384
Short name T229
Test name
Test status
Simulation time 4679083772 ps
CPU time 5.32 seconds
Started Jan 21 08:18:16 PM PST 24
Finished Jan 21 08:18:24 PM PST 24
Peak memory 202592 kb
Host smart-7bc662b3-b441-4188-9773-ea7ff6289e04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092840384 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.2092840384
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.121645898
Short name T1338
Test name
Test status
Simulation time 21410155896 ps
CPU time 168.61 seconds
Started Jan 21 08:18:20 PM PST 24
Finished Jan 21 08:21:15 PM PST 24
Peak memory 1484360 kb
Host smart-4004c3c2-43a4-4229-b7a0-80c3f718f0c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121645898 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.121645898
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_perf.66655172
Short name T1115
Test name
Test status
Simulation time 835965077 ps
CPU time 4.76 seconds
Started Jan 21 08:19:05 PM PST 24
Finished Jan 21 08:19:11 PM PST 24
Peak memory 202584 kb
Host smart-fe2666b2-f8a3-4eb3-83d1-b6e47c062f6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66655172 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.i2c_target_perf.66655172
Directory /workspace/2.i2c_target_perf/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.1632244115
Short name T214
Test name
Test status
Simulation time 622295673 ps
CPU time 8.3 seconds
Started Jan 21 08:18:17 PM PST 24
Finished Jan 21 08:18:28 PM PST 24
Peak memory 202568 kb
Host smart-b745ceb4-f299-4c99-8a51-ea34cbbd175a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632244115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.1632244115
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_all.3438370869
Short name T884
Test name
Test status
Simulation time 19067519938 ps
CPU time 1010.8 seconds
Started Jan 21 08:19:08 PM PST 24
Finished Jan 21 08:36:00 PM PST 24
Peak memory 1196172 kb
Host smart-28782918-7a3f-4837-98f3-6d8f5fb2ee00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438370869 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_stress_all.3438370869
Directory /workspace/2.i2c_target_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.3555809623
Short name T994
Test name
Test status
Simulation time 1773807802 ps
CPU time 66.59 seconds
Started Jan 21 08:18:20 PM PST 24
Finished Jan 21 08:19:33 PM PST 24
Peak memory 202596 kb
Host smart-f8a6bdb8-e625-43b4-90ea-d228a77ee351
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555809623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.3555809623
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.344000716
Short name T937
Test name
Test status
Simulation time 43095609653 ps
CPU time 2779.15 seconds
Started Jan 21 08:18:20 PM PST 24
Finished Jan 21 09:04:46 PM PST 24
Peak memory 9583904 kb
Host smart-cfcf808e-0920-4fff-b6a5-3ab10542503c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344000716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_wr.344000716
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.2077692228
Short name T685
Test name
Test status
Simulation time 7407143462 ps
CPU time 8.58 seconds
Started Jan 21 08:18:23 PM PST 24
Finished Jan 21 08:18:35 PM PST 24
Peak memory 215984 kb
Host smart-fa7649a1-377a-4a1d-940a-04cf83ca13db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077692228 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.2077692228
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_ovf.3788408506
Short name T1316
Test name
Test status
Simulation time 19722704971 ps
CPU time 181.67 seconds
Started Jan 21 08:18:18 PM PST 24
Finished Jan 21 08:21:25 PM PST 24
Peak memory 403648 kb
Host smart-82ce233a-7078-47e9-a302-f960d9a5f12d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788408506 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_tx_ovf.3788408506
Directory /workspace/2.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/2.i2c_target_unexp_stop.1369836515
Short name T975
Test name
Test status
Simulation time 1757514493 ps
CPU time 3.65 seconds
Started Jan 21 08:33:31 PM PST 24
Finished Jan 21 08:33:36 PM PST 24
Peak memory 202528 kb
Host smart-4e53db66-5403-4898-9462-4a3c26fb56b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369836515 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.i2c_target_unexp_stop.1369836515
Directory /workspace/2.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/20.i2c_alert_test.1201160187
Short name T98
Test name
Test status
Simulation time 55488347 ps
CPU time 0.62 seconds
Started Jan 21 08:28:03 PM PST 24
Finished Jan 21 08:28:08 PM PST 24
Peak memory 202032 kb
Host smart-cec8d33b-d2f3-4122-bcda-7380be7715b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201160187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.1201160187
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.3664119788
Short name T713
Test name
Test status
Simulation time 170711483 ps
CPU time 1.21 seconds
Started Jan 21 08:27:45 PM PST 24
Finished Jan 21 08:27:50 PM PST 24
Peak memory 210688 kb
Host smart-6e614b4a-2ee8-4570-84a7-7c0457f6dde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664119788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.3664119788
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.3576888701
Short name T212
Test name
Test status
Simulation time 383225601 ps
CPU time 8.47 seconds
Started Jan 21 08:27:45 PM PST 24
Finished Jan 21 08:27:57 PM PST 24
Peak memory 284312 kb
Host smart-d2e7c362-6262-4991-bc51-449cc9910112
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576888701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.3576888701
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.235979570
Short name T1075
Test name
Test status
Simulation time 15854018620 ps
CPU time 65.3 seconds
Started Jan 21 08:27:46 PM PST 24
Finished Jan 21 08:28:56 PM PST 24
Peak memory 358836 kb
Host smart-efa1c7bf-cf0f-40c1-81da-b3adbe273c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235979570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.235979570
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.3421060899
Short name T176
Test name
Test status
Simulation time 28064885354 ps
CPU time 538.93 seconds
Started Jan 21 08:27:44 PM PST 24
Finished Jan 21 08:36:45 PM PST 24
Peak memory 1986812 kb
Host smart-f4a8188a-1638-4c5c-9caf-634114ae22dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421060899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.3421060899
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.2695835915
Short name T846
Test name
Test status
Simulation time 536933958 ps
CPU time 1.03 seconds
Started Jan 21 08:27:49 PM PST 24
Finished Jan 21 08:27:52 PM PST 24
Peak memory 202488 kb
Host smart-e95f2129-bf43-48d0-8e6f-0629e4013d73
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695835915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.2695835915
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.1541256419
Short name T1284
Test name
Test status
Simulation time 136511069 ps
CPU time 8.28 seconds
Started Jan 21 08:27:46 PM PST 24
Finished Jan 21 08:27:58 PM PST 24
Peak memory 225000 kb
Host smart-cdca334e-3c13-4adf-8f3a-3e9334ccdbba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541256419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.1541256419
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.1093610344
Short name T956
Test name
Test status
Simulation time 4943358925 ps
CPU time 593.24 seconds
Started Jan 21 08:27:45 PM PST 24
Finished Jan 21 08:37:42 PM PST 24
Peak memory 1451100 kb
Host smart-f4043892-0ab7-4e7b-961f-e65645a7b5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093610344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.1093610344
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.1011255947
Short name T836
Test name
Test status
Simulation time 1615793319 ps
CPU time 43.64 seconds
Started Jan 21 08:28:00 PM PST 24
Finished Jan 21 08:28:45 PM PST 24
Peak memory 282896 kb
Host smart-9c6aade5-2ffa-47da-9f6d-560382e54a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011255947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.1011255947
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.1861896067
Short name T1020
Test name
Test status
Simulation time 54178050 ps
CPU time 0.64 seconds
Started Jan 21 08:27:40 PM PST 24
Finished Jan 21 08:27:46 PM PST 24
Peak memory 201472 kb
Host smart-1db55f31-d197-41d0-bf3d-67bc47f4b016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861896067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.1861896067
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.4030962562
Short name T509
Test name
Test status
Simulation time 25693421009 ps
CPU time 483.49 seconds
Started Jan 21 08:27:43 PM PST 24
Finished Jan 21 08:35:49 PM PST 24
Peak memory 218916 kb
Host smart-212b286a-4f8c-4223-af68-727c10825fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030962562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.4030962562
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_rx_oversample.820498632
Short name T893
Test name
Test status
Simulation time 5209508463 ps
CPU time 207.18 seconds
Started Jan 21 08:27:45 PM PST 24
Finished Jan 21 08:31:14 PM PST 24
Peak memory 381620 kb
Host smart-d950f4e6-0295-4c84-a844-fbc4e179208c
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820498632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_rx_oversample.
820498632
Directory /workspace/20.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.1231439848
Short name T574
Test name
Test status
Simulation time 2532836501 ps
CPU time 166.07 seconds
Started Jan 21 10:17:47 PM PST 24
Finished Jan 21 10:20:39 PM PST 24
Peak memory 279892 kb
Host smart-5c98c09b-2fc1-486e-83a2-50a337235bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231439848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.1231439848
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.1816243085
Short name T181
Test name
Test status
Simulation time 25601249958 ps
CPU time 3208.38 seconds
Started Jan 21 08:27:43 PM PST 24
Finished Jan 21 09:21:14 PM PST 24
Peak memory 2051268 kb
Host smart-5fbce3e7-b556-4067-8cc7-1f58255d4352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816243085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.1816243085
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.745844373
Short name T205
Test name
Test status
Simulation time 955972203 ps
CPU time 8.06 seconds
Started Jan 21 08:27:46 PM PST 24
Finished Jan 21 08:27:58 PM PST 24
Peak memory 210604 kb
Host smart-fa143b2c-470f-467b-99d5-e19f6f05de1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745844373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.745844373
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.2532012345
Short name T1418
Test name
Test status
Simulation time 1109097102 ps
CPU time 2.82 seconds
Started Jan 21 08:27:55 PM PST 24
Finished Jan 21 08:27:59 PM PST 24
Peak memory 202580 kb
Host smart-f3bf65ed-f99d-4ca7-b89d-481c27fb06ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532012345 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.2532012345
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.1737038920
Short name T491
Test name
Test status
Simulation time 10414398068 ps
CPU time 12.81 seconds
Started Jan 21 08:27:51 PM PST 24
Finished Jan 21 08:28:04 PM PST 24
Peak memory 270932 kb
Host smart-9820ac53-72cd-4556-996e-df010147dda9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737038920 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.1737038920
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.3812457426
Short name T433
Test name
Test status
Simulation time 10087549976 ps
CPU time 106.49 seconds
Started Jan 21 08:27:52 PM PST 24
Finished Jan 21 08:29:39 PM PST 24
Peak memory 677548 kb
Host smart-00232d01-d448-4caa-ab95-9e05ae25743e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812457426 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.3812457426
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.3108253045
Short name T560
Test name
Test status
Simulation time 899345611 ps
CPU time 2.39 seconds
Started Jan 21 08:27:54 PM PST 24
Finished Jan 21 08:27:57 PM PST 24
Peak memory 202620 kb
Host smart-fdefcebf-786c-4f4a-9228-fe084ab11ffd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108253045 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.3108253045
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.2808921434
Short name T429
Test name
Test status
Simulation time 1053595358 ps
CPU time 3.9 seconds
Started Jan 21 08:27:51 PM PST 24
Finished Jan 21 08:27:56 PM PST 24
Peak memory 202572 kb
Host smart-92122c08-da5b-47d0-8f33-5217e2c3443b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808921434 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.2808921434
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.190644006
Short name T1091
Test name
Test status
Simulation time 7571157410 ps
CPU time 8.9 seconds
Started Jan 21 08:27:49 PM PST 24
Finished Jan 21 08:28:00 PM PST 24
Peak memory 342616 kb
Host smart-a03a03fd-7b0d-433d-bf41-7954dc564c48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190644006 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.190644006
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_perf.1762705452
Short name T1047
Test name
Test status
Simulation time 12683728026 ps
CPU time 3.93 seconds
Started Jan 21 08:27:55 PM PST 24
Finished Jan 21 08:27:59 PM PST 24
Peak memory 204236 kb
Host smart-a1a34681-8297-445b-80bf-bc8225faec19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762705452 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_perf.1762705452
Directory /workspace/20.i2c_target_perf/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.3515993616
Short name T1301
Test name
Test status
Simulation time 4633626621 ps
CPU time 30.5 seconds
Started Jan 21 08:27:49 PM PST 24
Finished Jan 21 08:28:21 PM PST 24
Peak memory 202640 kb
Host smart-937242dd-d2d3-4679-b485-050b671aea30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515993616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.3515993616
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_all.1754541951
Short name T1297
Test name
Test status
Simulation time 57112073706 ps
CPU time 517.03 seconds
Started Jan 21 08:27:57 PM PST 24
Finished Jan 21 08:36:35 PM PST 24
Peak memory 1305416 kb
Host smart-3549dbbb-cd43-495f-81dc-91ea3b7375d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754541951 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.i2c_target_stress_all.1754541951
Directory /workspace/20.i2c_target_stress_all/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.2491662037
Short name T414
Test name
Test status
Simulation time 2022326137 ps
CPU time 18.5 seconds
Started Jan 21 08:27:49 PM PST 24
Finished Jan 21 08:28:09 PM PST 24
Peak memory 206136 kb
Host smart-dbe02a7a-8609-4082-93e0-4ad5a5d573f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491662037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.2491662037
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.300942428
Short name T874
Test name
Test status
Simulation time 42724852527 ps
CPU time 971.9 seconds
Started Jan 21 08:27:50 PM PST 24
Finished Jan 21 08:44:03 PM PST 24
Peak memory 2226928 kb
Host smart-7d8db50a-90fe-4ac9-9fad-2a592fe57283
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300942428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_t
arget_stretch.300942428
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.2839050348
Short name T572
Test name
Test status
Simulation time 2243810301 ps
CPU time 7.22 seconds
Started Jan 21 08:55:20 PM PST 24
Finished Jan 21 08:55:39 PM PST 24
Peak memory 208016 kb
Host smart-9a55a33b-d645-4b9d-a70f-828a4f1dd03c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839050348 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.2839050348
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_ovf.2361159528
Short name T1469
Test name
Test status
Simulation time 9733618673 ps
CPU time 158.28 seconds
Started Jan 21 08:27:51 PM PST 24
Finished Jan 21 08:30:31 PM PST 24
Peak memory 395896 kb
Host smart-95607baf-87fb-4f3c-bbc3-b9a598743418
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361159528 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_tx_ovf.2361159528
Directory /workspace/20.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/20.i2c_target_unexp_stop.386413207
Short name T1099
Test name
Test status
Simulation time 5736200096 ps
CPU time 7.93 seconds
Started Jan 21 08:27:51 PM PST 24
Finished Jan 21 08:28:00 PM PST 24
Peak memory 202624 kb
Host smart-b4bbfb00-727d-469d-a23a-c567118a711a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386413207 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_unexp_stop.386413207
Directory /workspace/20.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/21.i2c_alert_test.236290894
Short name T1482
Test name
Test status
Simulation time 28585559 ps
CPU time 0.63 seconds
Started Jan 21 08:28:36 PM PST 24
Finished Jan 21 08:28:39 PM PST 24
Peak memory 201160 kb
Host smart-d1d8339a-4767-4a8f-abc9-17a6d331a0e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236290894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.236290894
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.2167884888
Short name T49
Test name
Test status
Simulation time 104992460 ps
CPU time 1.44 seconds
Started Jan 21 08:28:13 PM PST 24
Finished Jan 21 08:28:15 PM PST 24
Peak memory 210704 kb
Host smart-2593e54a-49ee-4b9c-947b-7792bfe84592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167884888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.2167884888
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.2028165437
Short name T741
Test name
Test status
Simulation time 269866042 ps
CPU time 14.79 seconds
Started Jan 21 08:28:07 PM PST 24
Finished Jan 21 08:28:23 PM PST 24
Peak memory 255676 kb
Host smart-ecd49fe4-d81b-4c76-9d9b-05052f496744
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028165437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.2028165437
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.2943657449
Short name T616
Test name
Test status
Simulation time 13621438907 ps
CPU time 49.12 seconds
Started Jan 21 08:28:11 PM PST 24
Finished Jan 21 08:29:01 PM PST 24
Peak memory 462536 kb
Host smart-02537fcf-bc6d-4164-a517-01b395b5f7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943657449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.2943657449
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.1708809059
Short name T11
Test name
Test status
Simulation time 25656484868 ps
CPU time 946.09 seconds
Started Jan 21 08:28:11 PM PST 24
Finished Jan 21 08:43:58 PM PST 24
Peak memory 1642260 kb
Host smart-bc6fbc01-873e-4c57-aac8-affdb3bc63fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708809059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.1708809059
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.4048834784
Short name T8
Test name
Test status
Simulation time 546205828 ps
CPU time 1.07 seconds
Started Jan 21 08:28:09 PM PST 24
Finished Jan 21 08:28:12 PM PST 24
Peak memory 202468 kb
Host smart-4adcb0c5-361b-432b-9d10-282f8053a145
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048834784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.4048834784
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.1578778442
Short name T1287
Test name
Test status
Simulation time 1502592862 ps
CPU time 5.48 seconds
Started Jan 21 08:28:08 PM PST 24
Finished Jan 21 08:28:16 PM PST 24
Peak memory 202508 kb
Host smart-08e9ad5f-e966-406d-95d7-66f21c4a07f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578778442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.1578778442
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.1486513915
Short name T348
Test name
Test status
Simulation time 13346364270 ps
CPU time 867.97 seconds
Started Jan 21 08:28:03 PM PST 24
Finished Jan 21 08:42:35 PM PST 24
Peak memory 1830252 kb
Host smart-9d4b376b-e82a-46ff-b2c7-000edd8a2eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486513915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.1486513915
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.2636655941
Short name T1080
Test name
Test status
Simulation time 5965424756 ps
CPU time 371.22 seconds
Started Jan 21 08:28:37 PM PST 24
Finished Jan 21 08:34:50 PM PST 24
Peak memory 433468 kb
Host smart-61fb5f1e-ce40-452b-b3b7-323b35c10dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636655941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.2636655941
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.1884280996
Short name T653
Test name
Test status
Simulation time 18888150 ps
CPU time 0.67 seconds
Started Jan 21 08:28:02 PM PST 24
Finished Jan 21 08:28:08 PM PST 24
Peak memory 201532 kb
Host smart-f1440daa-9101-480b-adde-7eb721f3786c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884280996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.1884280996
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.1220738627
Short name T710
Test name
Test status
Simulation time 9043625333 ps
CPU time 116.37 seconds
Started Jan 21 08:28:13 PM PST 24
Finished Jan 21 08:30:10 PM PST 24
Peak memory 232416 kb
Host smart-0816da09-092e-46e1-9322-1e228d2b4e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220738627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.1220738627
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_rx_oversample.2946157244
Short name T580
Test name
Test status
Simulation time 1404316058 ps
CPU time 84.74 seconds
Started Jan 21 08:28:00 PM PST 24
Finished Jan 21 08:29:26 PM PST 24
Peak memory 235056 kb
Host smart-2fc36256-80ce-4193-9d4e-2a9bcfd13d8c
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946157244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_rx_oversample
.2946157244
Directory /workspace/21.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.786078076
Short name T979
Test name
Test status
Simulation time 9131039446 ps
CPU time 69.46 seconds
Started Jan 21 08:27:58 PM PST 24
Finished Jan 21 08:29:09 PM PST 24
Peak memory 297908 kb
Host smart-2a10679e-c265-4243-996f-ce5e9ea29177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786078076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.786078076
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.3827355159
Short name T1082
Test name
Test status
Simulation time 28193312715 ps
CPU time 1766.63 seconds
Started Jan 21 08:28:20 PM PST 24
Finished Jan 21 08:57:48 PM PST 24
Peak memory 3219280 kb
Host smart-cdd78044-2059-4088-b423-e0c60506c010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827355159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.3827355159
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.2282629716
Short name T397
Test name
Test status
Simulation time 10710440632 ps
CPU time 25.91 seconds
Started Jan 21 08:28:14 PM PST 24
Finished Jan 21 08:28:40 PM PST 24
Peak memory 227040 kb
Host smart-15b7f8d4-4de4-46c9-8726-2840f3272551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282629716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.2282629716
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.1886170297
Short name T905
Test name
Test status
Simulation time 941723017 ps
CPU time 3.79 seconds
Started Jan 21 08:28:28 PM PST 24
Finished Jan 21 08:28:37 PM PST 24
Peak memory 202532 kb
Host smart-fdbaaaee-3402-45a3-ac87-9d1ad5d13582
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886170297 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.1886170297
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.1055374090
Short name T71
Test name
Test status
Simulation time 10141333895 ps
CPU time 12.83 seconds
Started Jan 21 08:28:29 PM PST 24
Finished Jan 21 08:28:46 PM PST 24
Peak memory 253716 kb
Host smart-e4790ae3-9494-41d2-af2d-389e19a59655
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055374090 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.1055374090
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.268736337
Short name T430
Test name
Test status
Simulation time 10246021922 ps
CPU time 36.37 seconds
Started Jan 21 08:28:28 PM PST 24
Finished Jan 21 08:29:10 PM PST 24
Peak memory 490344 kb
Host smart-036b2868-03da-4564-b9d9-b4dca7817919
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268736337 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_fifo_reset_tx.268736337
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.2872205562
Short name T910
Test name
Test status
Simulation time 605156806 ps
CPU time 2.93 seconds
Started Jan 21 08:28:26 PM PST 24
Finished Jan 21 08:28:30 PM PST 24
Peak memory 202836 kb
Host smart-ffb2f811-caf5-4684-a7ac-8cc2b8408bc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872205562 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.2872205562
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.2618933792
Short name T629
Test name
Test status
Simulation time 1938939467 ps
CPU time 4.4 seconds
Started Jan 21 08:28:19 PM PST 24
Finished Jan 21 08:28:25 PM PST 24
Peak memory 202504 kb
Host smart-db220141-0666-4ddd-a839-cbce30fc6fe6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618933792 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.2618933792
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.1502542914
Short name T1445
Test name
Test status
Simulation time 13808331726 ps
CPU time 158.26 seconds
Started Jan 21 08:28:17 PM PST 24
Finished Jan 21 08:30:56 PM PST 24
Peak memory 1700796 kb
Host smart-c2b2449b-1958-418a-ae04-a70a3a16489b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502542914 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.1502542914
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_perf.955560016
Short name T404
Test name
Test status
Simulation time 722132902 ps
CPU time 4.51 seconds
Started Jan 21 08:28:27 PM PST 24
Finished Jan 21 08:28:37 PM PST 24
Peak memory 204680 kb
Host smart-fc095db0-c5f7-40df-851d-4e435326f016
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955560016 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.i2c_target_perf.955560016
Directory /workspace/21.i2c_target_perf/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.3244614736
Short name T742
Test name
Test status
Simulation time 1596368455 ps
CPU time 42.59 seconds
Started Jan 21 08:56:24 PM PST 24
Finished Jan 21 08:57:49 PM PST 24
Peak memory 202604 kb
Host smart-d24d3ede-b8de-44f3-965c-22ef51ceea3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244614736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.3244614736
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_all.865221552
Short name T164
Test name
Test status
Simulation time 51821092625 ps
CPU time 2999.35 seconds
Started Jan 21 08:28:28 PM PST 24
Finished Jan 21 09:18:33 PM PST 24
Peak memory 9690520 kb
Host smart-35720ce6-dc9f-42e8-9a1c-8ec298408ee0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865221552 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.i2c_target_stress_all.865221552
Directory /workspace/21.i2c_target_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.2906377542
Short name T1256
Test name
Test status
Simulation time 1687559640 ps
CPU time 32.53 seconds
Started Jan 21 08:28:15 PM PST 24
Finished Jan 21 08:28:49 PM PST 24
Peak memory 217292 kb
Host smart-9b65beb1-4eef-4cf9-bae6-008a2c2fd8fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906377542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.2906377542
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.4272059622
Short name T875
Test name
Test status
Simulation time 58675935197 ps
CPU time 583.08 seconds
Started Jan 21 08:28:19 PM PST 24
Finished Jan 21 08:38:03 PM PST 24
Peak memory 3544120 kb
Host smart-514409f0-fa11-4be8-b7b5-dcec64e44059
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272059622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.4272059622
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.2456203962
Short name T546
Test name
Test status
Simulation time 13375102673 ps
CPU time 48.86 seconds
Started Jan 21 08:56:28 PM PST 24
Finished Jan 21 08:57:58 PM PST 24
Peak memory 642136 kb
Host smart-c38d680d-9496-42d7-a415-ccb9e2d22568
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456203962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.2456203962
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.1623964374
Short name T449
Test name
Test status
Simulation time 1345118337 ps
CPU time 6.99 seconds
Started Jan 21 08:28:23 PM PST 24
Finished Jan 21 08:28:31 PM PST 24
Peak memory 202584 kb
Host smart-f607ef1f-18ad-4457-a653-e865654fa8a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623964374 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.1623964374
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_ovf.3525948297
Short name T1458
Test name
Test status
Simulation time 4837477533 ps
CPU time 57.79 seconds
Started Jan 21 08:28:18 PM PST 24
Finished Jan 21 08:29:17 PM PST 24
Peak memory 227872 kb
Host smart-6327e4ab-6613-4b35-9b21-5b15543c5d24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525948297 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_tx_ovf.3525948297
Directory /workspace/21.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/21.i2c_target_unexp_stop.1174198229
Short name T1010
Test name
Test status
Simulation time 1732467540 ps
CPU time 8.18 seconds
Started Jan 21 08:28:22 PM PST 24
Finished Jan 21 08:28:31 PM PST 24
Peak memory 205292 kb
Host smart-17c20799-b28a-45c6-856c-06c0f2cee9b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174198229 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.i2c_target_unexp_stop.1174198229
Directory /workspace/21.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/22.i2c_alert_test.3565077771
Short name T1074
Test name
Test status
Simulation time 21345124 ps
CPU time 0.61 seconds
Started Jan 21 08:29:02 PM PST 24
Finished Jan 21 08:29:03 PM PST 24
Peak memory 201124 kb
Host smart-30d91d39-9fd3-4f28-a675-21ba0474eb87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565077771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.3565077771
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.108914795
Short name T236
Test name
Test status
Simulation time 36370002 ps
CPU time 1.25 seconds
Started Jan 21 08:28:48 PM PST 24
Finished Jan 21 08:28:51 PM PST 24
Peak memory 210712 kb
Host smart-6404c13e-6493-4140-b442-6c64e28832f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108914795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.108914795
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.1404985114
Short name T242
Test name
Test status
Simulation time 1161266532 ps
CPU time 11.01 seconds
Started Jan 21 08:28:41 PM PST 24
Finished Jan 21 08:28:53 PM PST 24
Peak memory 240756 kb
Host smart-383da045-01f2-438f-a18a-38823a8799f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404985114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.1404985114
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.4051441915
Short name T336
Test name
Test status
Simulation time 3826838792 ps
CPU time 371.76 seconds
Started Jan 21 08:28:37 PM PST 24
Finished Jan 21 08:34:50 PM PST 24
Peak memory 1100536 kb
Host smart-fd522067-cace-4f23-9241-c67117f1b6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051441915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.4051441915
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.3802416616
Short name T974
Test name
Test status
Simulation time 6503052320 ps
CPU time 575.63 seconds
Started Jan 21 09:50:52 PM PST 24
Finished Jan 21 10:00:32 PM PST 24
Peak memory 1764284 kb
Host smart-c32ea716-05df-45aa-93c1-a50ec9341257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802416616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.3802416616
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.2249573548
Short name T1123
Test name
Test status
Simulation time 123735677 ps
CPU time 0.99 seconds
Started Jan 21 08:28:40 PM PST 24
Finished Jan 21 08:28:42 PM PST 24
Peak memory 202520 kb
Host smart-6b0d67d1-49d0-4053-a0db-2c7425f92569
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249573548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.2249573548
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.1250598027
Short name T488
Test name
Test status
Simulation time 418620873 ps
CPU time 6.22 seconds
Started Jan 21 08:28:41 PM PST 24
Finished Jan 21 08:28:49 PM PST 24
Peak memory 241832 kb
Host smart-bc0bf700-d258-4471-9de1-f7a760556fdf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250598027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.1250598027
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.2491682528
Short name T955
Test name
Test status
Simulation time 12179998471 ps
CPU time 788.65 seconds
Started Jan 21 08:28:34 PM PST 24
Finished Jan 21 08:41:46 PM PST 24
Peak memory 1721048 kb
Host smart-0018a741-812b-49de-97ae-16277e357062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491682528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.2491682528
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.3786824936
Short name T436
Test name
Test status
Simulation time 2360782067 ps
CPU time 59.78 seconds
Started Jan 21 08:29:03 PM PST 24
Finished Jan 21 08:30:04 PM PST 24
Peak memory 283588 kb
Host smart-e47573a6-9f49-465b-b70e-ae50175a9b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786824936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.3786824936
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.1188585397
Short name T1289
Test name
Test status
Simulation time 15824907 ps
CPU time 0.64 seconds
Started Jan 21 08:28:34 PM PST 24
Finished Jan 21 08:28:38 PM PST 24
Peak memory 201484 kb
Host smart-017efaa7-99b0-4ad8-8aee-cb5494656bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188585397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.1188585397
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.4183836475
Short name T1089
Test name
Test status
Simulation time 2623818455 ps
CPU time 58.53 seconds
Started Jan 21 08:28:40 PM PST 24
Finished Jan 21 08:29:40 PM PST 24
Peak memory 295460 kb
Host smart-6dc9cb60-3f5e-496d-bf83-26b76bc3481e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183836475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.4183836475
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_rx_oversample.3802226633
Short name T416
Test name
Test status
Simulation time 3476381819 ps
CPU time 233.05 seconds
Started Jan 21 08:28:34 PM PST 24
Finished Jan 21 08:32:30 PM PST 24
Peak memory 309380 kb
Host smart-c8fad877-d2d3-4534-8c58-4afd3d67d495
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802226633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_rx_oversample
.3802226633
Directory /workspace/22.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.3805777570
Short name T566
Test name
Test status
Simulation time 9563438346 ps
CPU time 85.35 seconds
Started Jan 21 08:53:42 PM PST 24
Finished Jan 21 08:55:24 PM PST 24
Peak memory 310172 kb
Host smart-7d448266-57a8-480b-8107-c704f7d1494e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805777570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.3805777570
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.1927791210
Short name T861
Test name
Test status
Simulation time 12229422991 ps
CPU time 875.78 seconds
Started Jan 21 08:28:49 PM PST 24
Finished Jan 21 08:43:27 PM PST 24
Peak memory 878560 kb
Host smart-a9996fc6-948a-496c-b48a-003f72bc8b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927791210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.1927791210
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.4092397409
Short name T1015
Test name
Test status
Simulation time 532513759 ps
CPU time 8.97 seconds
Started Jan 21 08:28:49 PM PST 24
Finished Jan 21 08:29:00 PM PST 24
Peak memory 218828 kb
Host smart-b95c7f82-73d2-44f9-91fc-8ca5eca099ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092397409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.4092397409
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.1011537565
Short name T1129
Test name
Test status
Simulation time 1039586412 ps
CPU time 3.28 seconds
Started Jan 21 09:06:51 PM PST 24
Finished Jan 21 09:07:12 PM PST 24
Peak memory 202660 kb
Host smart-25478d08-643d-4534-978b-0c5d6ff0c524
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011537565 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.1011537565
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.1832575890
Short name T295
Test name
Test status
Simulation time 10021501786 ps
CPU time 72.75 seconds
Started Jan 21 08:28:54 PM PST 24
Finished Jan 21 08:30:08 PM PST 24
Peak memory 583008 kb
Host smart-cf362ba4-f12e-4f96-9feb-357d42b36968
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832575890 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.1832575890
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.2485254215
Short name T1088
Test name
Test status
Simulation time 10287627459 ps
CPU time 7.53 seconds
Started Jan 21 08:28:51 PM PST 24
Finished Jan 21 08:29:00 PM PST 24
Peak memory 280028 kb
Host smart-54724872-e650-4a13-9491-88a6fe6da860
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485254215 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.2485254215
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.2929547848
Short name T849
Test name
Test status
Simulation time 2947013171 ps
CPU time 3.41 seconds
Started Jan 21 08:28:56 PM PST 24
Finished Jan 21 08:29:01 PM PST 24
Peak memory 202708 kb
Host smart-b62c0a9e-67ac-4f3e-8104-614d825a9dd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929547848 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.2929547848
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.959495042
Short name T497
Test name
Test status
Simulation time 1559679739 ps
CPU time 6.94 seconds
Started Jan 21 08:28:52 PM PST 24
Finished Jan 21 08:29:00 PM PST 24
Peak memory 202576 kb
Host smart-de3a3bb1-a121-4118-9c86-5a48bb7faec7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959495042 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_intr_smoke.959495042
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.1110495351
Short name T481
Test name
Test status
Simulation time 6309771677 ps
CPU time 12.96 seconds
Started Jan 21 09:17:49 PM PST 24
Finished Jan 21 09:18:02 PM PST 24
Peak memory 437856 kb
Host smart-be8cdc2e-399c-4b4d-8249-523d682b28a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110495351 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.1110495351
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_perf.1981867347
Short name T1337
Test name
Test status
Simulation time 715565259 ps
CPU time 2.24 seconds
Started Jan 21 08:28:54 PM PST 24
Finished Jan 21 08:28:58 PM PST 24
Peak memory 202472 kb
Host smart-b929356e-dd53-4a7d-bca0-4a746741224b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981867347 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_perf.1981867347
Directory /workspace/22.i2c_target_perf/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.223023597
Short name T1443
Test name
Test status
Simulation time 5071346007 ps
CPU time 11.93 seconds
Started Jan 21 08:28:51 PM PST 24
Finished Jan 21 08:29:04 PM PST 24
Peak memory 202596 kb
Host smart-4a60aec7-43dd-48a4-984c-1e201610e3a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223023597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar
get_smoke.223023597
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_all.2671863902
Short name T1311
Test name
Test status
Simulation time 8882988564 ps
CPU time 73.33 seconds
Started Jan 21 08:28:54 PM PST 24
Finished Jan 21 08:30:08 PM PST 24
Peak memory 235116 kb
Host smart-621625e6-9842-49a5-8216-14bae9a7273b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671863902 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_target_stress_all.2671863902
Directory /workspace/22.i2c_target_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.2415559032
Short name T261
Test name
Test status
Simulation time 18156788166 ps
CPU time 28.14 seconds
Started Jan 21 08:28:50 PM PST 24
Finished Jan 21 08:29:19 PM PST 24
Peak memory 225860 kb
Host smart-2186b87f-5c11-48f4-a5dd-0ea1e10277ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415559032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.2415559032
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.2343757625
Short name T798
Test name
Test status
Simulation time 65475861103 ps
CPU time 878.74 seconds
Started Jan 21 08:28:48 PM PST 24
Finished Jan 21 08:43:30 PM PST 24
Peak memory 4141276 kb
Host smart-f548cd00-c5cc-4b27-a8f6-002b8c6fddba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343757625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.2343757625
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.4092685318
Short name T1498
Test name
Test status
Simulation time 13252102483 ps
CPU time 371.58 seconds
Started Jan 21 08:28:49 PM PST 24
Finished Jan 21 08:35:03 PM PST 24
Peak memory 2618996 kb
Host smart-4da2df23-f688-4c81-94f6-e1d3fc9ab9c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092685318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.4092685318
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.756727644
Short name T631
Test name
Test status
Simulation time 2865691428 ps
CPU time 7.23 seconds
Started Jan 21 08:28:53 PM PST 24
Finished Jan 21 08:29:01 PM PST 24
Peak memory 210804 kb
Host smart-f3c25080-b7a9-4db8-bfab-db91e9aa629a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756727644 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_timeout.756727644
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_ovf.1185724319
Short name T1359
Test name
Test status
Simulation time 15591977602 ps
CPU time 24.65 seconds
Started Jan 21 08:28:51 PM PST 24
Finished Jan 21 08:29:17 PM PST 24
Peak memory 207356 kb
Host smart-5c92745c-2537-4e53-8dbf-599d369ed077
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185724319 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_tx_ovf.1185724319
Directory /workspace/22.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/22.i2c_target_unexp_stop.1347100858
Short name T1472
Test name
Test status
Simulation time 3173048978 ps
CPU time 6.72 seconds
Started Jan 21 08:28:53 PM PST 24
Finished Jan 21 08:29:01 PM PST 24
Peak memory 202684 kb
Host smart-9e6f0094-7386-4282-b282-ada2e930561a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347100858 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.i2c_target_unexp_stop.1347100858
Directory /workspace/22.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/23.i2c_alert_test.738677396
Short name T1137
Test name
Test status
Simulation time 16735516 ps
CPU time 0.62 seconds
Started Jan 21 08:29:33 PM PST 24
Finished Jan 21 08:29:35 PM PST 24
Peak memory 202024 kb
Host smart-9cbf62ca-93c6-4f51-ab2a-9f438819d5bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738677396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.738677396
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.6000552
Short name T1098
Test name
Test status
Simulation time 194915130 ps
CPU time 1.15 seconds
Started Jan 21 08:29:11 PM PST 24
Finished Jan 21 08:29:13 PM PST 24
Peak memory 202548 kb
Host smart-b27e2384-022e-440f-beae-5666222b1d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6000552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.6000552
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.3751749961
Short name T438
Test name
Test status
Simulation time 865459328 ps
CPU time 4.53 seconds
Started Jan 21 08:29:06 PM PST 24
Finished Jan 21 08:29:11 PM PST 24
Peak memory 220892 kb
Host smart-a3e79842-96d4-4ade-96e0-bb7164dae6e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751749961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.3751749961
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.1466899012
Short name T267
Test name
Test status
Simulation time 6919661253 ps
CPU time 285.04 seconds
Started Jan 21 08:29:07 PM PST 24
Finished Jan 21 08:33:53 PM PST 24
Peak memory 973280 kb
Host smart-6a6bc8eb-e2ee-4327-b585-1797ac09ae4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466899012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.1466899012
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.94708112
Short name T1356
Test name
Test status
Simulation time 3820974147 ps
CPU time 196.12 seconds
Started Jan 21 09:36:59 PM PST 24
Finished Jan 21 09:40:33 PM PST 24
Peak memory 1089548 kb
Host smart-3245b376-63c3-42ac-9dbb-51d3518c5aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94708112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.94708112
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.1808374019
Short name T827
Test name
Test status
Simulation time 218184163 ps
CPU time 1.03 seconds
Started Jan 21 08:29:07 PM PST 24
Finished Jan 21 08:29:09 PM PST 24
Peak memory 202296 kb
Host smart-d97a5790-004c-47e6-bef0-5322f3671ece
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808374019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.1808374019
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.1579929996
Short name T568
Test name
Test status
Simulation time 231690541 ps
CPU time 3.22 seconds
Started Jan 21 08:29:07 PM PST 24
Finished Jan 21 08:29:11 PM PST 24
Peak memory 202560 kb
Host smart-ed0d3fb4-6fd0-4ef0-b517-547e4fd59ebb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579929996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.1579929996
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.2005764570
Short name T1151
Test name
Test status
Simulation time 21634944847 ps
CPU time 676.88 seconds
Started Jan 21 08:29:08 PM PST 24
Finished Jan 21 08:40:27 PM PST 24
Peak memory 1514984 kb
Host smart-360dbf56-6feb-459d-a24c-ff63ddaeea59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005764570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.2005764570
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.1329971458
Short name T931
Test name
Test status
Simulation time 4301454707 ps
CPU time 82.29 seconds
Started Jan 21 08:29:25 PM PST 24
Finished Jan 21 08:30:49 PM PST 24
Peak memory 345348 kb
Host smart-21178822-8677-4bb9-bba3-f68d5412faf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329971458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.1329971458
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.1552610402
Short name T1488
Test name
Test status
Simulation time 79749524 ps
CPU time 0.63 seconds
Started Jan 21 08:29:03 PM PST 24
Finished Jan 21 08:29:05 PM PST 24
Peak memory 201532 kb
Host smart-001fb9c9-002b-4ced-8692-28291e3e4ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552610402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.1552610402
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.960274333
Short name T1400
Test name
Test status
Simulation time 48718470656 ps
CPU time 649.46 seconds
Started Jan 21 09:11:33 PM PST 24
Finished Jan 21 09:22:26 PM PST 24
Peak memory 202556 kb
Host smart-57cb48c6-c0ee-4674-a6ba-b63b1f5bbaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960274333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.960274333
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.3385001751
Short name T1095
Test name
Test status
Simulation time 9343503273 ps
CPU time 48.64 seconds
Started Jan 21 08:29:05 PM PST 24
Finished Jan 21 08:29:54 PM PST 24
Peak memory 281144 kb
Host smart-f079d038-df66-44a5-bf5c-c498c9794db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385001751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.3385001751
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.3259621376
Short name T1236
Test name
Test status
Simulation time 329540519 ps
CPU time 15.22 seconds
Started Jan 21 09:06:14 PM PST 24
Finished Jan 21 09:07:01 PM PST 24
Peak memory 210648 kb
Host smart-03f31988-44fd-429c-a9d0-f52bba5e16d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259621376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.3259621376
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.478166347
Short name T639
Test name
Test status
Simulation time 1927351417 ps
CPU time 4.57 seconds
Started Jan 21 08:29:29 PM PST 24
Finished Jan 21 08:29:34 PM PST 24
Peak memory 202560 kb
Host smart-a4c1bd08-69bb-4b28-ac12-5473ed1dc99c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478166347 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.478166347
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.3275261984
Short name T1045
Test name
Test status
Simulation time 10113810278 ps
CPU time 61.43 seconds
Started Jan 21 08:29:27 PM PST 24
Finished Jan 21 08:30:29 PM PST 24
Peak memory 462424 kb
Host smart-c38de736-a9cc-45a6-bde2-6547688d2db6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275261984 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.3275261984
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.616489603
Short name T987
Test name
Test status
Simulation time 10437345559 ps
CPU time 17.07 seconds
Started Jan 21 08:29:31 PM PST 24
Finished Jan 21 08:29:49 PM PST 24
Peak memory 328800 kb
Host smart-35f3fab9-1c07-417d-8d69-3c929cdc0f89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616489603 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_fifo_reset_tx.616489603
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.2502250456
Short name T1327
Test name
Test status
Simulation time 631033103 ps
CPU time 3.07 seconds
Started Jan 21 08:29:25 PM PST 24
Finished Jan 21 08:29:30 PM PST 24
Peak memory 202656 kb
Host smart-00d06f85-d89d-4a5a-92f4-7816d26eefe1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502250456 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.2502250456
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.4094489978
Short name T62
Test name
Test status
Simulation time 6347140111 ps
CPU time 5.48 seconds
Started Jan 21 08:29:18 PM PST 24
Finished Jan 21 08:29:25 PM PST 24
Peak memory 203100 kb
Host smart-8d05410b-7483-4efb-985e-d45594cc34bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094489978 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.4094489978
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.1128121754
Short name T1525
Test name
Test status
Simulation time 7241277792 ps
CPU time 97.84 seconds
Started Jan 21 08:29:21 PM PST 24
Finished Jan 21 08:30:59 PM PST 24
Peak memory 1514060 kb
Host smart-e329d697-91b4-49ef-a289-4b180c7b8507
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128121754 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.1128121754
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_perf.3591996428
Short name T1309
Test name
Test status
Simulation time 2824895375 ps
CPU time 4.24 seconds
Started Jan 21 08:29:26 PM PST 24
Finished Jan 21 08:29:31 PM PST 24
Peak memory 202624 kb
Host smart-ede881fc-ff77-4231-b059-6f92f578c2cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591996428 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_perf.3591996428
Directory /workspace/23.i2c_target_perf/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.2448526022
Short name T533
Test name
Test status
Simulation time 1165295091 ps
CPU time 16.23 seconds
Started Jan 21 08:29:15 PM PST 24
Finished Jan 21 08:29:32 PM PST 24
Peak memory 202568 kb
Host smart-798020ae-cc6c-4e3e-a107-3afa805dee0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448526022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.2448526022
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_all.3061267976
Short name T1491
Test name
Test status
Simulation time 35965972549 ps
CPU time 25.92 seconds
Started Jan 21 08:29:26 PM PST 24
Finished Jan 21 08:29:53 PM PST 24
Peak memory 235160 kb
Host smart-7a40868e-9430-4153-a42d-0d64f4d69e28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061267976 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_stress_all.3061267976
Directory /workspace/23.i2c_target_stress_all/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.2906109709
Short name T1120
Test name
Test status
Simulation time 4827712732 ps
CPU time 29.75 seconds
Started Jan 21 08:29:23 PM PST 24
Finished Jan 21 08:29:54 PM PST 24
Peak memory 214256 kb
Host smart-8df85f56-6e68-42bb-bfde-549cadb6a993
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906109709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.2906109709
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.3165615043
Short name T529
Test name
Test status
Simulation time 23846615600 ps
CPU time 259.17 seconds
Started Jan 21 08:29:24 PM PST 24
Finished Jan 21 08:33:44 PM PST 24
Peak memory 2596320 kb
Host smart-a0e22875-3a49-4bd1-b425-52ec214a677b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165615043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.3165615043
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.1251233401
Short name T714
Test name
Test status
Simulation time 19923785289 ps
CPU time 1126.95 seconds
Started Jan 21 08:29:22 PM PST 24
Finished Jan 21 08:48:10 PM PST 24
Peak memory 4205796 kb
Host smart-a95c70df-ae63-4812-b573-543809313a27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251233401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.1251233401
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.1527424675
Short name T918
Test name
Test status
Simulation time 1855332101 ps
CPU time 8.11 seconds
Started Jan 21 08:29:23 PM PST 24
Finished Jan 21 08:29:32 PM PST 24
Peak memory 207112 kb
Host smart-c2117d29-2eff-4f45-b4f3-0583c4825648
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527424675 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.1527424675
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_ovf.2309635829
Short name T14
Test name
Test status
Simulation time 13071813542 ps
CPU time 137.4 seconds
Started Jan 21 08:29:20 PM PST 24
Finished Jan 21 08:31:38 PM PST 24
Peak memory 403096 kb
Host smart-6b09d1dc-99e7-4604-a4e2-0bafceecf6fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309635829 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_tx_ovf.2309635829
Directory /workspace/23.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/23.i2c_target_unexp_stop.901080199
Short name T1186
Test name
Test status
Simulation time 2860039375 ps
CPU time 7.08 seconds
Started Jan 21 08:29:31 PM PST 24
Finished Jan 21 08:29:39 PM PST 24
Peak memory 202620 kb
Host smart-b575bfe8-f12c-4bf5-a772-36391f7a5885
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901080199 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_unexp_stop.901080199
Directory /workspace/23.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/24.i2c_alert_test.1063102767
Short name T1179
Test name
Test status
Simulation time 16329010 ps
CPU time 0.61 seconds
Started Jan 21 08:29:53 PM PST 24
Finished Jan 21 08:29:55 PM PST 24
Peak memory 201964 kb
Host smart-a7a989ef-3413-4130-97a9-a9c0f7348df5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063102767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.1063102767
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.3850397146
Short name T502
Test name
Test status
Simulation time 123806346 ps
CPU time 1.7 seconds
Started Jan 21 08:29:44 PM PST 24
Finished Jan 21 08:29:47 PM PST 24
Peak memory 210684 kb
Host smart-776db2ba-e8d4-48b2-876b-690806de83c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850397146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.3850397146
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.3590491543
Short name T1139
Test name
Test status
Simulation time 457865550 ps
CPU time 8.38 seconds
Started Jan 21 08:29:44 PM PST 24
Finished Jan 21 08:29:53 PM PST 24
Peak memory 296884 kb
Host smart-e02be84c-3550-4e68-ba31-909c2a8de771
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590491543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.3590491543
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.2243714178
Short name T935
Test name
Test status
Simulation time 14753127740 ps
CPU time 349.05 seconds
Started Jan 21 08:29:44 PM PST 24
Finished Jan 21 08:35:33 PM PST 24
Peak memory 1121232 kb
Host smart-fffd3f26-5a52-48fa-92dc-588bc50ff976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243714178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.2243714178
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.1285200070
Short name T1377
Test name
Test status
Simulation time 15688543035 ps
CPU time 234.38 seconds
Started Jan 21 08:29:37 PM PST 24
Finished Jan 21 08:33:32 PM PST 24
Peak memory 1183372 kb
Host smart-1638ae3c-6de9-4fa8-ac42-05fd4fbc22bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285200070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.1285200070
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.3236723371
Short name T954
Test name
Test status
Simulation time 399192344 ps
CPU time 10.89 seconds
Started Jan 21 08:29:40 PM PST 24
Finished Jan 21 08:29:51 PM PST 24
Peak memory 202156 kb
Host smart-5f457038-8283-435b-b0df-a996afe1abc4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236723371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.3236723371
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.4053048904
Short name T1046
Test name
Test status
Simulation time 8388500834 ps
CPU time 398.6 seconds
Started Jan 21 08:29:34 PM PST 24
Finished Jan 21 08:36:14 PM PST 24
Peak memory 1155836 kb
Host smart-b8e3b8c5-d348-46cf-9997-00150675c168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053048904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.4053048904
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.969300816
Short name T831
Test name
Test status
Simulation time 2633897453 ps
CPU time 147.3 seconds
Started Jan 21 08:29:53 PM PST 24
Finished Jan 21 08:32:21 PM PST 24
Peak memory 410372 kb
Host smart-8e36b48f-4418-480c-a1ed-add0266215b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969300816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.969300816
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.3616306190
Short name T390
Test name
Test status
Simulation time 17336057 ps
CPU time 0.63 seconds
Started Jan 21 08:29:38 PM PST 24
Finished Jan 21 08:29:39 PM PST 24
Peak memory 201408 kb
Host smart-d3242a5a-68e3-4d00-8683-8e106b4fb994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616306190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.3616306190
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.2126168442
Short name T1426
Test name
Test status
Simulation time 31018394538 ps
CPU time 234.45 seconds
Started Jan 21 08:29:35 PM PST 24
Finished Jan 21 08:33:31 PM PST 24
Peak memory 221916 kb
Host smart-732a4a1d-7c53-4c38-91d0-0697e5cbc2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126168442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.2126168442
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_rx_oversample.3680972395
Short name T1314
Test name
Test status
Simulation time 6092465088 ps
CPU time 127.64 seconds
Started Jan 21 08:29:35 PM PST 24
Finished Jan 21 08:31:43 PM PST 24
Peak memory 278980 kb
Host smart-00f5d030-be23-4836-8e9b-033765ccab0b
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680972395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_rx_oversample
.3680972395
Directory /workspace/24.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.519252670
Short name T1149
Test name
Test status
Simulation time 4444357401 ps
CPU time 61.26 seconds
Started Jan 21 08:29:33 PM PST 24
Finished Jan 21 08:30:36 PM PST 24
Peak memory 298692 kb
Host smart-e87fc8b0-00fd-459f-8f21-77e8388cdf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519252670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.519252670
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.3951388173
Short name T184
Test name
Test status
Simulation time 83988978463 ps
CPU time 2952.32 seconds
Started Jan 21 08:29:45 PM PST 24
Finished Jan 21 09:18:58 PM PST 24
Peak memory 3979344 kb
Host smart-e5d9010a-43c7-45bb-8d14-1de6858bc1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951388173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.3951388173
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.3296465064
Short name T851
Test name
Test status
Simulation time 1142328086 ps
CPU time 22.34 seconds
Started Jan 21 08:29:44 PM PST 24
Finished Jan 21 08:30:07 PM PST 24
Peak memory 218764 kb
Host smart-e7d15c51-3cf8-4ee2-82d5-f8e2044b35a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296465064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.3296465064
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.1046492812
Short name T1494
Test name
Test status
Simulation time 670779828 ps
CPU time 3.03 seconds
Started Jan 21 08:29:45 PM PST 24
Finished Jan 21 08:29:49 PM PST 24
Peak memory 202596 kb
Host smart-a7ece92c-9385-4406-a62c-d8bf5577f2a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046492812 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.1046492812
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.423744084
Short name T1341
Test name
Test status
Simulation time 10303828386 ps
CPU time 7.47 seconds
Started Jan 21 08:29:47 PM PST 24
Finished Jan 21 08:29:55 PM PST 24
Peak memory 246676 kb
Host smart-b58d03dd-17b9-42e8-ab5d-0f605dbc9c04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423744084 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_acq.423744084
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.2468944955
Short name T1034
Test name
Test status
Simulation time 10991656355 ps
CPU time 9.34 seconds
Started Jan 21 08:29:51 PM PST 24
Finished Jan 21 08:30:01 PM PST 24
Peak memory 283084 kb
Host smart-80f611de-5202-4623-b93d-c86560155e4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468944955 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.2468944955
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.3405041685
Short name T310
Test name
Test status
Simulation time 888663081 ps
CPU time 3.99 seconds
Started Jan 21 08:29:46 PM PST 24
Finished Jan 21 08:29:51 PM PST 24
Peak memory 202612 kb
Host smart-8174ae36-6e8c-4654-bfff-7f6017ce293d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405041685 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.3405041685
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.363941376
Short name T1427
Test name
Test status
Simulation time 26431387550 ps
CPU time 651.47 seconds
Started Jan 21 08:29:48 PM PST 24
Finished Jan 21 08:40:42 PM PST 24
Peak memory 3371736 kb
Host smart-c6694b54-627c-4895-9390-929389b26c06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363941376 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.363941376
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_perf.3818303188
Short name T869
Test name
Test status
Simulation time 598239689 ps
CPU time 3.85 seconds
Started Jan 21 08:29:47 PM PST 24
Finished Jan 21 08:29:52 PM PST 24
Peak memory 202580 kb
Host smart-1e587357-ec91-43e1-a749-313643fe6d5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818303188 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_perf.3818303188
Directory /workspace/24.i2c_target_perf/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.4265113779
Short name T1262
Test name
Test status
Simulation time 3452015112 ps
CPU time 10.77 seconds
Started Jan 21 08:29:44 PM PST 24
Finished Jan 21 08:29:55 PM PST 24
Peak memory 202628 kb
Host smart-2d56c806-0553-4907-af41-8a255643ddb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265113779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.4265113779
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.2365813745
Short name T706
Test name
Test status
Simulation time 6561289221 ps
CPU time 20.66 seconds
Started Jan 21 08:29:45 PM PST 24
Finished Jan 21 08:30:07 PM PST 24
Peak memory 210960 kb
Host smart-72388570-8500-4ea2-b3dc-b64d7b8ff278
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365813745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.2365813745
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.712032796
Short name T1167
Test name
Test status
Simulation time 37402993524 ps
CPU time 2134.86 seconds
Started Jan 21 08:41:43 PM PST 24
Finished Jan 21 09:17:20 PM PST 24
Peak memory 8193168 kb
Host smart-65fd1f81-14ba-4033-b360-bb21f2910893
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712032796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_wr.712032796
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.536232603
Short name T215
Test name
Test status
Simulation time 35002019577 ps
CPU time 3215.12 seconds
Started Jan 21 08:29:39 PM PST 24
Finished Jan 21 09:23:16 PM PST 24
Peak memory 7446808 kb
Host smart-95a967bb-f2fd-490a-8fde-fd7736d29ec8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536232603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_t
arget_stretch.536232603
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.2688697577
Short name T1272
Test name
Test status
Simulation time 1785068817 ps
CPU time 7.06 seconds
Started Jan 21 08:29:46 PM PST 24
Finished Jan 21 08:29:54 PM PST 24
Peak memory 205212 kb
Host smart-3cbb4f71-8d11-423b-9cb2-68219ef70310
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688697577 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.2688697577
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_ovf.2218716324
Short name T381
Test name
Test status
Simulation time 3373160287 ps
CPU time 100.67 seconds
Started Jan 21 08:29:49 PM PST 24
Finished Jan 21 08:31:31 PM PST 24
Peak memory 310408 kb
Host smart-832899ba-d152-42ff-88ae-ff43d92bb5c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218716324 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_tx_ovf.2218716324
Directory /workspace/24.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/24.i2c_target_unexp_stop.1781119330
Short name T624
Test name
Test status
Simulation time 5953388529 ps
CPU time 8.05 seconds
Started Jan 21 08:29:49 PM PST 24
Finished Jan 21 08:29:58 PM PST 24
Peak memory 204816 kb
Host smart-c2889695-6ad6-4f30-85c7-2c5fb89477cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781119330 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.i2c_target_unexp_stop.1781119330
Directory /workspace/24.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/25.i2c_alert_test.3562410306
Short name T372
Test name
Test status
Simulation time 22664368 ps
CPU time 0.62 seconds
Started Jan 21 08:30:34 PM PST 24
Finished Jan 21 08:30:37 PM PST 24
Peak memory 201080 kb
Host smart-36369148-0359-4895-8437-2d1afcd26090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562410306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.3562410306
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.4037332767
Short name T1216
Test name
Test status
Simulation time 53740461 ps
CPU time 1.45 seconds
Started Jan 21 08:30:06 PM PST 24
Finished Jan 21 08:30:08 PM PST 24
Peak memory 210728 kb
Host smart-afc3223b-b125-4049-894a-9f2c3d327fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037332767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.4037332767
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.3129854998
Short name T1138
Test name
Test status
Simulation time 567531252 ps
CPU time 32.23 seconds
Started Jan 21 08:30:11 PM PST 24
Finished Jan 21 08:30:44 PM PST 24
Peak memory 317096 kb
Host smart-4d433fae-c063-4867-b36e-755ec194ba47
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129854998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.3129854998
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.927089291
Short name T450
Test name
Test status
Simulation time 8819455664 ps
CPU time 82.35 seconds
Started Jan 21 08:30:09 PM PST 24
Finished Jan 21 08:31:32 PM PST 24
Peak memory 715852 kb
Host smart-8f601192-f156-4cf2-b2e3-20b8bbd72a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927089291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.927089291
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.3422922801
Short name T763
Test name
Test status
Simulation time 30433745510 ps
CPU time 535.82 seconds
Started Jan 21 08:29:58 PM PST 24
Finished Jan 21 08:38:55 PM PST 24
Peak memory 1983080 kb
Host smart-3b022c06-3dcd-48a7-b2d4-0efbfba7077e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422922801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.3422922801
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.1368416786
Short name T1036
Test name
Test status
Simulation time 128040194 ps
CPU time 0.8 seconds
Started Jan 21 08:30:06 PM PST 24
Finished Jan 21 08:30:08 PM PST 24
Peak memory 201480 kb
Host smart-1146e047-8e2b-4a81-89da-d3e48ef1aaf5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368416786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.1368416786
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.1759310325
Short name T1487
Test name
Test status
Simulation time 246473519 ps
CPU time 3.51 seconds
Started Jan 21 08:30:10 PM PST 24
Finished Jan 21 08:30:15 PM PST 24
Peak memory 222120 kb
Host smart-d2e863cf-0bd4-4873-acbb-f1aef66dfdf6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759310325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.1759310325
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.3995699563
Short name T73
Test name
Test status
Simulation time 23108535386 ps
CPU time 321.42 seconds
Started Jan 21 08:29:59 PM PST 24
Finished Jan 21 08:35:21 PM PST 24
Peak memory 1580204 kb
Host smart-9b6983f4-64cf-4c66-8b90-2f297ad2de17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995699563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.3995699563
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.2910061553
Short name T275
Test name
Test status
Simulation time 16726202964 ps
CPU time 72.94 seconds
Started Jan 21 08:30:30 PM PST 24
Finished Jan 21 08:31:43 PM PST 24
Peak memory 299412 kb
Host smart-d3eaca68-6965-4d66-8b9f-9f092de0055d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910061553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.2910061553
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.1634601743
Short name T737
Test name
Test status
Simulation time 24562588 ps
CPU time 0.63 seconds
Started Jan 21 08:29:53 PM PST 24
Finished Jan 21 08:29:55 PM PST 24
Peak memory 201396 kb
Host smart-db9d9f3c-123d-4960-af00-d7f19e69a496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634601743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.1634601743
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.1882250426
Short name T711
Test name
Test status
Simulation time 25596140577 ps
CPU time 682.65 seconds
Started Jan 21 08:30:09 PM PST 24
Finished Jan 21 08:41:33 PM PST 24
Peak memory 536008 kb
Host smart-d0a52e3f-0cae-492c-b2d8-45dcdc532d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882250426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1882250426
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_rx_oversample.3660167944
Short name T257
Test name
Test status
Simulation time 3650920739 ps
CPU time 121.79 seconds
Started Jan 21 08:29:59 PM PST 24
Finished Jan 21 08:32:02 PM PST 24
Peak memory 246856 kb
Host smart-47306cff-c698-4a3a-990b-db2cc80569d9
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660167944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_rx_oversample
.3660167944
Directory /workspace/25.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.727382449
Short name T1252
Test name
Test status
Simulation time 1355559490 ps
CPU time 77.19 seconds
Started Jan 21 08:29:53 PM PST 24
Finished Jan 21 08:31:11 PM PST 24
Peak memory 243320 kb
Host smart-5d814cf2-a8ba-41dc-9dcb-8c7002af9d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727382449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.727382449
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.1112872351
Short name T140
Test name
Test status
Simulation time 65515930396 ps
CPU time 1992.73 seconds
Started Jan 21 08:30:09 PM PST 24
Finished Jan 21 09:03:23 PM PST 24
Peak memory 2345664 kb
Host smart-168d5e41-6d9c-4134-b467-73f16afa2665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112872351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.1112872351
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.1188946485
Short name T842
Test name
Test status
Simulation time 5922674202 ps
CPU time 11.27 seconds
Started Jan 21 08:30:08 PM PST 24
Finished Jan 21 08:30:20 PM PST 24
Peak memory 214432 kb
Host smart-d658d08a-200e-45a6-856b-7df77d5a0286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188946485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.1188946485
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.2481265191
Short name T986
Test name
Test status
Simulation time 915699627 ps
CPU time 2.36 seconds
Started Jan 21 08:30:31 PM PST 24
Finished Jan 21 08:30:34 PM PST 24
Peak memory 202608 kb
Host smart-13a0a435-a8ae-4370-917d-26c846112f70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481265191 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.2481265191
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.829986993
Short name T708
Test name
Test status
Simulation time 10322265902 ps
CPU time 7.39 seconds
Started Jan 21 08:30:27 PM PST 24
Finished Jan 21 08:30:35 PM PST 24
Peak memory 245152 kb
Host smart-aa7e649b-638b-458f-b72e-f1f385eb0a57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829986993 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_acq.829986993
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.3542170363
Short name T524
Test name
Test status
Simulation time 10294796229 ps
CPU time 40.93 seconds
Started Jan 21 08:30:34 PM PST 24
Finished Jan 21 08:31:16 PM PST 24
Peak memory 445836 kb
Host smart-1e695032-a2ed-4d3f-a227-eac5a6d24043
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542170363 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.3542170363
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.2218639538
Short name T432
Test name
Test status
Simulation time 1257068697 ps
CPU time 1.98 seconds
Started Jan 21 08:30:27 PM PST 24
Finished Jan 21 08:30:30 PM PST 24
Peak memory 202820 kb
Host smart-e7cb89bf-ef12-48eb-a1ee-b34aa85e1890
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218639538 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.2218639538
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.3401341306
Short name T1502
Test name
Test status
Simulation time 6062526142 ps
CPU time 6.62 seconds
Started Jan 21 08:30:19 PM PST 24
Finished Jan 21 08:30:27 PM PST 24
Peak memory 202640 kb
Host smart-3b5ed35f-8b55-4be7-9f3a-9ccec0e6f70c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401341306 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.3401341306
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.2170787906
Short name T1499
Test name
Test status
Simulation time 17763220950 ps
CPU time 753.22 seconds
Started Jan 21 08:30:20 PM PST 24
Finished Jan 21 08:42:54 PM PST 24
Peak memory 4186772 kb
Host smart-8930c8b0-8438-4fe4-845c-5782fd893326
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170787906 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.2170787906
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_perf.2881634851
Short name T1126
Test name
Test status
Simulation time 2129054662 ps
CPU time 3.36 seconds
Started Jan 21 08:30:29 PM PST 24
Finished Jan 21 08:30:33 PM PST 24
Peak memory 202568 kb
Host smart-ea03fef9-1e47-4dca-a439-ebcb6926b21e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881634851 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_perf.2881634851
Directory /workspace/25.i2c_target_perf/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.351285067
Short name T221
Test name
Test status
Simulation time 3730717477 ps
CPU time 22.76 seconds
Started Jan 21 08:30:12 PM PST 24
Finished Jan 21 08:30:35 PM PST 24
Peak memory 202684 kb
Host smart-e45edce3-a4ea-421b-b37c-e0fd343173a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351285067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_tar
get_smoke.351285067
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.1478695559
Short name T1051
Test name
Test status
Simulation time 6210580906 ps
CPU time 65.01 seconds
Started Jan 21 08:30:13 PM PST 24
Finished Jan 21 08:31:19 PM PST 24
Peak memory 202608 kb
Host smart-febff8e4-d501-4127-af54-150c410f90e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478695559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.1478695559
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.2496181597
Short name T425
Test name
Test status
Simulation time 18327753245 ps
CPU time 126.25 seconds
Started Jan 21 08:30:18 PM PST 24
Finished Jan 21 08:32:25 PM PST 24
Peak memory 1002056 kb
Host smart-3f1b53d4-4848-4880-bb8f-c2163259cb20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496181597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.2496181597
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.637491260
Short name T721
Test name
Test status
Simulation time 2104013897 ps
CPU time 7.71 seconds
Started Jan 21 08:30:15 PM PST 24
Finished Jan 21 08:30:24 PM PST 24
Peak memory 202584 kb
Host smart-07e9583a-685e-450c-af7f-2b961e382e7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637491260 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_timeout.637491260
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_ovf.432730266
Short name T973
Test name
Test status
Simulation time 8746637903 ps
CPU time 52.69 seconds
Started Jan 21 08:30:19 PM PST 24
Finished Jan 21 08:31:13 PM PST 24
Peak memory 224648 kb
Host smart-64e71389-4ec6-46ed-9e20-f72e1b9b43c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432730266 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_tx_ovf.432730266
Directory /workspace/25.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/25.i2c_target_unexp_stop.1447422567
Short name T42
Test name
Test status
Simulation time 1890996821 ps
CPU time 5.17 seconds
Started Jan 21 08:30:17 PM PST 24
Finished Jan 21 08:30:23 PM PST 24
Peak memory 202552 kb
Host smart-f83e4920-c006-4e1b-a5a9-215fdf2069e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447422567 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.i2c_target_unexp_stop.1447422567
Directory /workspace/25.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/26.i2c_alert_test.41084311
Short name T690
Test name
Test status
Simulation time 101449570 ps
CPU time 0.6 seconds
Started Jan 21 09:09:59 PM PST 24
Finished Jan 21 09:10:19 PM PST 24
Peak memory 201104 kb
Host smart-6d32876e-4a20-4f34-a7ab-6f20c20c5b51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41084311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.41084311
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.4144335339
Short name T805
Test name
Test status
Simulation time 145324342 ps
CPU time 1.2 seconds
Started Jan 21 08:30:34 PM PST 24
Finished Jan 21 08:30:36 PM PST 24
Peak memory 210684 kb
Host smart-a711f332-d169-474b-85de-16d9e6207243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144335339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.4144335339
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.463700053
Short name T695
Test name
Test status
Simulation time 494823043 ps
CPU time 12.37 seconds
Started Jan 21 08:30:32 PM PST 24
Finished Jan 21 08:30:45 PM PST 24
Peak memory 315072 kb
Host smart-97f9e71b-3475-46a3-b225-15fc49bfbb11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463700053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empt
y.463700053
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.3277776732
Short name T777
Test name
Test status
Simulation time 8494549202 ps
CPU time 94.77 seconds
Started Jan 21 08:30:33 PM PST 24
Finished Jan 21 08:32:09 PM PST 24
Peak memory 828968 kb
Host smart-4b2e5a49-0b02-4a55-9749-8d1a7cda8c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277776732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.3277776732
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.3081674677
Short name T514
Test name
Test status
Simulation time 11946188833 ps
CPU time 398.3 seconds
Started Jan 21 08:56:19 PM PST 24
Finished Jan 21 09:03:37 PM PST 24
Peak memory 1638620 kb
Host smart-e7363b92-9b7b-4668-a958-d8de3c60805e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081674677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.3081674677
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.57634933
Short name T1519
Test name
Test status
Simulation time 268554022 ps
CPU time 1.21 seconds
Started Jan 21 08:41:25 PM PST 24
Finished Jan 21 08:41:28 PM PST 24
Peak memory 202492 kb
Host smart-0b85b5bb-8064-4707-b3c0-3bfbeba97851
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57634933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fmt
.57634933
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.1347435614
Short name T1156
Test name
Test status
Simulation time 407340136 ps
CPU time 5.67 seconds
Started Jan 21 08:30:37 PM PST 24
Finished Jan 21 08:30:44 PM PST 24
Peak memory 202520 kb
Host smart-958958b7-17d8-457e-aed9-a54c5945fed7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347435614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.1347435614
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.3269720136
Short name T939
Test name
Test status
Simulation time 9159535634 ps
CPU time 833.81 seconds
Started Jan 21 08:55:09 PM PST 24
Finished Jan 21 09:09:09 PM PST 24
Peak memory 1746640 kb
Host smart-c8342668-41a1-4f08-9a86-df7d00626337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269720136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.3269720136
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.2512147439
Short name T1343
Test name
Test status
Simulation time 9587072651 ps
CPU time 142.94 seconds
Started Jan 21 09:06:10 PM PST 24
Finished Jan 21 09:09:07 PM PST 24
Peak memory 248272 kb
Host smart-a186ba80-f225-4882-9856-bd99792da555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512147439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.2512147439
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.916262022
Short name T1409
Test name
Test status
Simulation time 18635445 ps
CPU time 0.7 seconds
Started Jan 21 09:10:31 PM PST 24
Finished Jan 21 09:10:51 PM PST 24
Peak memory 201516 kb
Host smart-67aa1bfd-760b-4eae-81bb-fd13ca5985fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916262022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.916262022
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.701623276
Short name T1424
Test name
Test status
Simulation time 71928105226 ps
CPU time 1367.17 seconds
Started Jan 21 08:30:36 PM PST 24
Finished Jan 21 08:53:25 PM PST 24
Peak memory 438708 kb
Host smart-5930301f-b31d-4947-ac02-831b8f0e7dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701623276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.701623276
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_rx_oversample.3988862031
Short name T504
Test name
Test status
Simulation time 9907755989 ps
CPU time 97.36 seconds
Started Jan 21 09:02:31 PM PST 24
Finished Jan 21 09:04:18 PM PST 24
Peak memory 325000 kb
Host smart-f6fe3c20-3d77-4b26-915f-92f6c81c77a3
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988862031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_rx_oversample
.3988862031
Directory /workspace/26.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.3752365883
Short name T271
Test name
Test status
Simulation time 1817531043 ps
CPU time 97.16 seconds
Started Jan 21 08:30:30 PM PST 24
Finished Jan 21 08:32:08 PM PST 24
Peak memory 232068 kb
Host smart-374c1a6c-68a0-4e5b-b207-eeaab4a783c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752365883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.3752365883
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.1970865215
Short name T111
Test name
Test status
Simulation time 18339817586 ps
CPU time 18.09 seconds
Started Jan 21 08:30:36 PM PST 24
Finished Jan 21 08:30:56 PM PST 24
Peak memory 215128 kb
Host smart-539dafa5-b1d2-4e96-82b9-370246223160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970865215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.1970865215
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.2355358046
Short name T260
Test name
Test status
Simulation time 13151303680 ps
CPU time 3.24 seconds
Started Jan 21 08:30:48 PM PST 24
Finished Jan 21 08:30:57 PM PST 24
Peak memory 202624 kb
Host smart-ade67a68-9310-482d-ac60-316f3ec7cc32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355358046 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.2355358046
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.3745875010
Short name T904
Test name
Test status
Simulation time 10300131153 ps
CPU time 12.43 seconds
Started Jan 21 09:55:54 PM PST 24
Finished Jan 21 09:56:10 PM PST 24
Peak memory 288616 kb
Host smart-180a632a-acde-4f36-9c7d-0676e6c8a437
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745875010 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.3745875010
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.2579875216
Short name T968
Test name
Test status
Simulation time 10545301278 ps
CPU time 15.68 seconds
Started Jan 21 08:53:29 PM PST 24
Finished Jan 21 08:54:02 PM PST 24
Peak memory 290904 kb
Host smart-815111b7-9d51-4318-9d50-b1bc741c1896
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579875216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.2579875216
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.2815712209
Short name T296
Test name
Test status
Simulation time 2328546440 ps
CPU time 2.91 seconds
Started Jan 21 08:30:41 PM PST 24
Finished Jan 21 08:30:47 PM PST 24
Peak memory 202712 kb
Host smart-dfbfd981-3eb7-4007-ba2c-868b9b2377b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815712209 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.2815712209
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.3033054977
Short name T1318
Test name
Test status
Simulation time 6782453734 ps
CPU time 6.86 seconds
Started Jan 21 08:30:35 PM PST 24
Finished Jan 21 08:30:44 PM PST 24
Peak memory 207504 kb
Host smart-495de2ab-b185-4e63-ac47-201951a90e56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033054977 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.3033054977
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.3214292568
Short name T847
Test name
Test status
Simulation time 10831103972 ps
CPU time 84.43 seconds
Started Jan 21 08:30:45 PM PST 24
Finished Jan 21 08:32:11 PM PST 24
Peak memory 1285144 kb
Host smart-53c76a2d-dde7-468e-ac7d-1d05f9dfb5c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214292568 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.3214292568
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_perf.4125244304
Short name T1480
Test name
Test status
Simulation time 3075204836 ps
CPU time 4.81 seconds
Started Jan 21 08:30:42 PM PST 24
Finished Jan 21 08:30:49 PM PST 24
Peak memory 207288 kb
Host smart-f2faa07b-7fd0-4f6c-9a6a-bcbe5164e428
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125244304 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_perf.4125244304
Directory /workspace/26.i2c_target_perf/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.197797712
Short name T858
Test name
Test status
Simulation time 2922037647 ps
CPU time 14.76 seconds
Started Jan 21 08:30:36 PM PST 24
Finished Jan 21 08:30:52 PM PST 24
Peak memory 202652 kb
Host smart-85f2f535-d0f5-4644-b495-039041c66a13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197797712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_tar
get_smoke.197797712
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_all.1486729270
Short name T1118
Test name
Test status
Simulation time 13354236231 ps
CPU time 55.25 seconds
Started Jan 21 08:30:45 PM PST 24
Finished Jan 21 08:31:43 PM PST 24
Peak memory 221732 kb
Host smart-35a24f0a-dd21-4c6e-890e-59f8086ebe20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486729270 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_stress_all.1486729270
Directory /workspace/26.i2c_target_stress_all/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.3415781235
Short name T370
Test name
Test status
Simulation time 1881150099 ps
CPU time 77.25 seconds
Started Jan 21 08:30:38 PM PST 24
Finished Jan 21 08:32:00 PM PST 24
Peak memory 202928 kb
Host smart-e0d43b84-64e2-4e53-8f67-a47396974dd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415781235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.3415781235
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.1098715944
Short name T1037
Test name
Test status
Simulation time 9989160839 ps
CPU time 76.25 seconds
Started Jan 21 08:30:34 PM PST 24
Finished Jan 21 08:31:52 PM PST 24
Peak memory 1457124 kb
Host smart-81e32195-282e-42b5-9c74-ce29dfb26949
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098715944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.1098715944
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.3067637082
Short name T59
Test name
Test status
Simulation time 18836968661 ps
CPU time 130.47 seconds
Started Jan 21 08:30:35 PM PST 24
Finished Jan 21 08:32:47 PM PST 24
Peak memory 1208496 kb
Host smart-110db9bd-ed07-42a6-8b4c-652270b059f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067637082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.3067637082
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.1543371473
Short name T210
Test name
Test status
Simulation time 9508400213 ps
CPU time 7.93 seconds
Started Jan 21 08:30:47 PM PST 24
Finished Jan 21 08:31:00 PM PST 24
Peak memory 202616 kb
Host smart-e1277665-d074-4d8c-a50b-4c961135f907
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543371473 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.1543371473
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_ovf.3421804892
Short name T962
Test name
Test status
Simulation time 2604525749 ps
CPU time 115.62 seconds
Started Jan 21 08:30:47 PM PST 24
Finished Jan 21 08:32:48 PM PST 24
Peak memory 336488 kb
Host smart-8291e271-eda6-4a14-a84d-dbda600699b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421804892 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_tx_ovf.3421804892
Directory /workspace/26.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/26.i2c_target_unexp_stop.1949757475
Short name T1260
Test name
Test status
Simulation time 2164466108 ps
CPU time 5.32 seconds
Started Jan 21 08:30:43 PM PST 24
Finished Jan 21 08:30:50 PM PST 24
Peak memory 203168 kb
Host smart-487dad42-96d3-423a-a899-9687a10d273e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949757475 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.i2c_target_unexp_stop.1949757475
Directory /workspace/26.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/27.i2c_alert_test.2488758854
Short name T1357
Test name
Test status
Simulation time 16395934 ps
CPU time 0.6 seconds
Started Jan 21 09:11:06 PM PST 24
Finished Jan 21 09:11:19 PM PST 24
Peak memory 201984 kb
Host smart-6637c8bc-fa72-4b9d-8e9b-c210fea58953
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488758854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.2488758854
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.1450022230
Short name T883
Test name
Test status
Simulation time 39706939 ps
CPU time 1.2 seconds
Started Jan 21 08:31:05 PM PST 24
Finished Jan 21 08:31:08 PM PST 24
Peak memory 210752 kb
Host smart-e9ff9007-bcff-4d8c-8ea9-7f0592eadbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450022230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.1450022230
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.118324216
Short name T1315
Test name
Test status
Simulation time 233557940 ps
CPU time 4.18 seconds
Started Jan 21 08:30:55 PM PST 24
Finished Jan 21 08:31:05 PM PST 24
Peak memory 231736 kb
Host smart-cb60d139-3538-44d5-a1ff-e41fd79ccb7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118324216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_empt
y.118324216
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.20810420
Short name T1490
Test name
Test status
Simulation time 3004464913 ps
CPU time 83.75 seconds
Started Jan 21 08:30:53 PM PST 24
Finished Jan 21 08:32:24 PM PST 24
Peak memory 659916 kb
Host smart-4d5fa751-ea4b-47bc-8ed6-e8b422d7b5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20810420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.20810420
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.125109751
Short name T1144
Test name
Test status
Simulation time 13708237638 ps
CPU time 435.57 seconds
Started Jan 21 08:30:52 PM PST 24
Finished Jan 21 08:38:14 PM PST 24
Peak memory 1703724 kb
Host smart-e6c68f34-eac8-4c90-8027-7df738c61dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125109751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.125109751
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.3292888041
Short name T575
Test name
Test status
Simulation time 484004484 ps
CPU time 1.04 seconds
Started Jan 21 08:30:57 PM PST 24
Finished Jan 21 08:31:03 PM PST 24
Peak memory 202480 kb
Host smart-f2e0f61b-38ea-44c1-b979-14a356dfae88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292888041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.3292888041
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.3220051204
Short name T483
Test name
Test status
Simulation time 1136486837 ps
CPU time 6.05 seconds
Started Jan 21 08:30:51 PM PST 24
Finished Jan 21 08:31:03 PM PST 24
Peak memory 202500 kb
Host smart-6d097d2f-b5e5-4796-98c8-edb0adb024bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220051204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.3220051204
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.1784398061
Short name T1172
Test name
Test status
Simulation time 24937561310 ps
CPU time 394.23 seconds
Started Jan 21 08:30:55 PM PST 24
Finished Jan 21 08:37:36 PM PST 24
Peak memory 1650224 kb
Host smart-6d79398e-4dc9-404e-963a-f92a4266b28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784398061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.1784398061
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.1033752557
Short name T387
Test name
Test status
Simulation time 10625850009 ps
CPU time 158.06 seconds
Started Jan 21 08:31:28 PM PST 24
Finished Jan 21 08:34:09 PM PST 24
Peak memory 283760 kb
Host smart-b7c31825-4d61-4c96-8b59-72e23f4bd697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033752557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.1033752557
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.2082654000
Short name T304
Test name
Test status
Simulation time 18068678 ps
CPU time 0.72 seconds
Started Jan 21 08:30:49 PM PST 24
Finished Jan 21 08:30:54 PM PST 24
Peak memory 201556 kb
Host smart-b73b217b-a96c-484a-aa58-79c8f3b5659c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082654000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.2082654000
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.4133002341
Short name T339
Test name
Test status
Simulation time 48363493412 ps
CPU time 239.87 seconds
Started Jan 21 08:30:58 PM PST 24
Finished Jan 21 08:35:02 PM PST 24
Peak memory 263192 kb
Host smart-a626494b-feaf-4e5c-806f-0c25028f9a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133002341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.4133002341
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_rx_oversample.4247009849
Short name T535
Test name
Test status
Simulation time 5034448336 ps
CPU time 317.61 seconds
Started Jan 21 09:01:38 PM PST 24
Finished Jan 21 09:07:13 PM PST 24
Peak memory 314140 kb
Host smart-e848b6f4-9288-4004-8fb4-a551e79ceb6f
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247009849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_rx_oversample
.4247009849
Directory /workspace/27.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.3980118797
Short name T206
Test name
Test status
Simulation time 1435075555 ps
CPU time 42.29 seconds
Started Jan 21 08:30:52 PM PST 24
Finished Jan 21 08:31:40 PM PST 24
Peak memory 277100 kb
Host smart-63577ad4-e522-4f4a-b44f-78f1fc3ec358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980118797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.3980118797
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.2979746823
Short name T252
Test name
Test status
Simulation time 1000156493 ps
CPU time 18.94 seconds
Started Jan 21 08:31:02 PM PST 24
Finished Jan 21 08:31:23 PM PST 24
Peak memory 218172 kb
Host smart-652c4e25-4656-469b-a533-9696f141f091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979746823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.2979746823
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.2568261426
Short name T40
Test name
Test status
Simulation time 3269263575 ps
CPU time 4.35 seconds
Started Jan 21 08:31:24 PM PST 24
Finished Jan 21 08:31:35 PM PST 24
Peak memory 202624 kb
Host smart-e631501c-b697-48f4-bbe1-3a67dbe2a554
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568261426 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.2568261426
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.2299928284
Short name T195
Test name
Test status
Simulation time 10067208170 ps
CPU time 25.01 seconds
Started Jan 21 08:31:16 PM PST 24
Finished Jan 21 08:31:42 PM PST 24
Peak memory 352824 kb
Host smart-3ef7aa56-7ca1-4294-a886-daff21facf15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299928284 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.2299928284
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.2766543470
Short name T1475
Test name
Test status
Simulation time 10099125895 ps
CPU time 13.06 seconds
Started Jan 21 08:31:18 PM PST 24
Finished Jan 21 08:31:32 PM PST 24
Peak memory 285848 kb
Host smart-f84729d1-b6c3-4e52-8fb3-63ca76d31cb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766543470 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.2766543470
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.1171463321
Short name T1520
Test name
Test status
Simulation time 488993205 ps
CPU time 2.38 seconds
Started Jan 21 08:31:27 PM PST 24
Finished Jan 21 08:31:33 PM PST 24
Peak memory 202596 kb
Host smart-24979dcf-c35d-4172-8a46-c0004aabf12b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171463321 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.1171463321
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.2606277882
Short name T1228
Test name
Test status
Simulation time 9257298897 ps
CPU time 9.81 seconds
Started Jan 21 08:31:19 PM PST 24
Finished Jan 21 08:31:30 PM PST 24
Peak memory 208368 kb
Host smart-e10a1080-2b4e-4670-a676-b70f4d2e77ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606277882 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.2606277882
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.2524039388
Short name T945
Test name
Test status
Simulation time 25721066071 ps
CPU time 203 seconds
Started Jan 21 08:31:15 PM PST 24
Finished Jan 21 08:34:40 PM PST 24
Peak memory 1629844 kb
Host smart-855e411d-32d5-4244-b653-b217db7cb959
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524039388 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.2524039388
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_perf.1745512198
Short name T558
Test name
Test status
Simulation time 627645649 ps
CPU time 3.9 seconds
Started Jan 21 08:31:36 PM PST 24
Finished Jan 21 08:31:41 PM PST 24
Peak memory 202596 kb
Host smart-bf5b97b6-d536-41b2-9551-0d9f714f5786
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745512198 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_perf.1745512198
Directory /workspace/27.i2c_target_perf/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.4157407686
Short name T250
Test name
Test status
Simulation time 869145804 ps
CPU time 8.77 seconds
Started Jan 21 08:31:05 PM PST 24
Finished Jan 21 08:31:15 PM PST 24
Peak memory 202536 kb
Host smart-784b9587-fa43-40ad-98a8-663d0e05f742
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157407686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.4157407686
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_all.410424616
Short name T960
Test name
Test status
Simulation time 35940722552 ps
CPU time 218.43 seconds
Started Jan 21 08:31:22 PM PST 24
Finished Jan 21 08:35:02 PM PST 24
Peak memory 370364 kb
Host smart-2b1ccc4c-cfb7-4598-a33a-34ad91c285fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410424616 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.i2c_target_stress_all.410424616
Directory /workspace/27.i2c_target_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.3499365590
Short name T1293
Test name
Test status
Simulation time 1060167359 ps
CPU time 5.23 seconds
Started Jan 21 08:31:11 PM PST 24
Finished Jan 21 08:31:17 PM PST 24
Peak memory 202576 kb
Host smart-fe498a94-c6fc-4f76-9000-da491b6c8c70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499365590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.3499365590
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.3719953335
Short name T1346
Test name
Test status
Simulation time 65902719301 ps
CPU time 811.98 seconds
Started Jan 21 08:31:10 PM PST 24
Finished Jan 21 08:44:43 PM PST 24
Peak memory 3860036 kb
Host smart-746b6ee9-95c1-4845-a53b-634f2db809e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719953335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.3719953335
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.274901495
Short name T458
Test name
Test status
Simulation time 15179213314 ps
CPU time 802.66 seconds
Started Jan 21 08:31:10 PM PST 24
Finished Jan 21 08:44:33 PM PST 24
Peak memory 3381740 kb
Host smart-1e4133be-2ce3-48c3-9f4e-5411b85fc8a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274901495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_t
arget_stretch.274901495
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.1100586697
Short name T577
Test name
Test status
Simulation time 2259622058 ps
CPU time 8.82 seconds
Started Jan 21 08:31:17 PM PST 24
Finished Jan 21 08:31:27 PM PST 24
Peak memory 202652 kb
Host smart-0300b69a-8ec4-469b-be05-54ab9475e195
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100586697 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.1100586697
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_ovf.1708269115
Short name T1489
Test name
Test status
Simulation time 11034410877 ps
CPU time 78.14 seconds
Started Jan 21 08:31:16 PM PST 24
Finished Jan 21 08:32:36 PM PST 24
Peak memory 292904 kb
Host smart-0f8d582b-d9d0-49d2-ae8b-3debeee8e04c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708269115 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_tx_ovf.1708269115
Directory /workspace/27.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/27.i2c_target_unexp_stop.3380721516
Short name T1026
Test name
Test status
Simulation time 6360427052 ps
CPU time 8.02 seconds
Started Jan 21 08:31:16 PM PST 24
Finished Jan 21 08:31:26 PM PST 24
Peak memory 202648 kb
Host smart-0f949a7c-7eaf-4912-b6cf-157d35c580e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380721516 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.i2c_target_unexp_stop.3380721516
Directory /workspace/27.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/28.i2c_alert_test.3666261855
Short name T759
Test name
Test status
Simulation time 56396230 ps
CPU time 0.61 seconds
Started Jan 21 08:31:58 PM PST 24
Finished Jan 21 08:32:00 PM PST 24
Peak memory 201096 kb
Host smart-ebf5685b-4906-46f6-8cfd-b9f736efdc07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666261855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.3666261855
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.3001299486
Short name T1207
Test name
Test status
Simulation time 201645115 ps
CPU time 1.78 seconds
Started Jan 21 08:31:40 PM PST 24
Finished Jan 21 08:31:43 PM PST 24
Peak memory 210744 kb
Host smart-eb78e057-18ec-4979-9b03-4abe2430fe74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001299486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.3001299486
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.1032549754
Short name T917
Test name
Test status
Simulation time 2017361999 ps
CPU time 36.43 seconds
Started Jan 21 08:31:40 PM PST 24
Finished Jan 21 08:32:18 PM PST 24
Peak memory 353332 kb
Host smart-a18972d2-755a-4b8f-a18e-6e8df3c77d2b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032549754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.1032549754
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.2043654907
Short name T716
Test name
Test status
Simulation time 2660197359 ps
CPU time 215.43 seconds
Started Jan 21 08:31:40 PM PST 24
Finished Jan 21 08:35:17 PM PST 24
Peak memory 850300 kb
Host smart-628f9b46-ac9c-4fcc-ae40-b5832e8f4260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043654907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.2043654907
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.601938703
Short name T475
Test name
Test status
Simulation time 21044468236 ps
CPU time 314.76 seconds
Started Jan 21 08:31:36 PM PST 24
Finished Jan 21 08:36:52 PM PST 24
Peak memory 1494968 kb
Host smart-dcc2808e-3d90-4450-b11a-dbf427b30dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601938703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.601938703
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.9431506
Short name T1259
Test name
Test status
Simulation time 84465226 ps
CPU time 0.86 seconds
Started Jan 21 08:46:34 PM PST 24
Finished Jan 21 08:47:22 PM PST 24
Peak memory 202316 kb
Host smart-f64769a7-ffe4-4c61-bbae-e02033ef93aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9431506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fmt.9431506
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.4287030008
Short name T1340
Test name
Test status
Simulation time 233355791 ps
CPU time 6.93 seconds
Started Jan 21 08:31:37 PM PST 24
Finished Jan 21 08:31:45 PM PST 24
Peak memory 246636 kb
Host smart-bcf64ae5-d50c-4a68-baf3-ff1e29571af0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287030008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.4287030008
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.4036265276
Short name T691
Test name
Test status
Simulation time 12158291751 ps
CPU time 770.89 seconds
Started Jan 21 08:31:36 PM PST 24
Finished Jan 21 08:44:29 PM PST 24
Peak memory 1688648 kb
Host smart-ca67497e-3023-4954-8890-22db3eff1d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036265276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.4036265276
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.1342623981
Short name T1226
Test name
Test status
Simulation time 2698531774 ps
CPU time 34.4 seconds
Started Jan 21 09:08:55 PM PST 24
Finished Jan 21 09:09:40 PM PST 24
Peak memory 276188 kb
Host smart-72d5046e-daef-418d-8de0-5a696da039a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342623981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.1342623981
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.4230793002
Short name T630
Test name
Test status
Simulation time 15027886 ps
CPU time 0.66 seconds
Started Jan 21 08:31:38 PM PST 24
Finished Jan 21 08:31:39 PM PST 24
Peak memory 201492 kb
Host smart-d2ecfcda-4401-49c8-b4e2-8737cba6a989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230793002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.4230793002
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.4115319858
Short name T828
Test name
Test status
Simulation time 459320342 ps
CPU time 4.09 seconds
Started Jan 21 08:31:40 PM PST 24
Finished Jan 21 08:31:45 PM PST 24
Peak memory 226820 kb
Host smart-97faa8f7-0c54-43bb-8c30-89063b273d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115319858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.4115319858
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_rx_oversample.4160057393
Short name T1223
Test name
Test status
Simulation time 3250986303 ps
CPU time 173.5 seconds
Started Jan 21 08:49:06 PM PST 24
Finished Jan 21 08:52:06 PM PST 24
Peak memory 352148 kb
Host smart-febbfc61-ac80-4520-b71d-ac656850b84e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160057393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_rx_oversample
.4160057393
Directory /workspace/28.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.1899750643
Short name T1372
Test name
Test status
Simulation time 9717675118 ps
CPU time 135.75 seconds
Started Jan 21 08:31:27 PM PST 24
Finished Jan 21 08:33:46 PM PST 24
Peak memory 246780 kb
Host smart-30004d22-2dfa-4688-8ec2-30243b28eaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899750643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1899750643
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.3184778914
Short name T1431
Test name
Test status
Simulation time 86413447544 ps
CPU time 3368.53 seconds
Started Jan 21 08:31:40 PM PST 24
Finished Jan 21 09:27:51 PM PST 24
Peak memory 2977632 kb
Host smart-e7fb760a-1708-4ca9-9528-714c9af95ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184778914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.3184778914
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all_with_rand_reset.489240495
Short name T85
Test name
Test status
Simulation time 13270720221 ps
CPU time 379.51 seconds
Started Jan 21 08:56:41 PM PST 24
Finished Jan 21 09:03:38 PM PST 24
Peak memory 846068 kb
Host smart-3d836082-5820-477e-9ab6-732119f391eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489240495 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.i2c_host_stress_all_with_rand_reset.489240495
Directory /workspace/28.i2c_host_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.3102654010
Short name T589
Test name
Test status
Simulation time 585049742 ps
CPU time 27 seconds
Started Jan 21 08:31:40 PM PST 24
Finished Jan 21 08:32:09 PM PST 24
Peak memory 210880 kb
Host smart-b1285c1a-17c3-4d2f-8616-cd155624fa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102654010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.3102654010
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.1840331688
Short name T587
Test name
Test status
Simulation time 1348479725 ps
CPU time 5.53 seconds
Started Jan 21 08:31:52 PM PST 24
Finished Jan 21 08:31:58 PM PST 24
Peak memory 202560 kb
Host smart-889fd1c1-78af-49c3-a6c6-04bf6227d64c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840331688 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.1840331688
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.1751002672
Short name T897
Test name
Test status
Simulation time 10465189409 ps
CPU time 11.69 seconds
Started Jan 21 08:31:50 PM PST 24
Finished Jan 21 08:32:03 PM PST 24
Peak memory 251320 kb
Host smart-be16cd27-778c-4ae4-84ed-6c17dac2e42d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751002672 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.1751002672
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.855043225
Short name T565
Test name
Test status
Simulation time 10082868337 ps
CPU time 15.93 seconds
Started Jan 21 08:31:56 PM PST 24
Finished Jan 21 08:32:13 PM PST 24
Peak memory 320468 kb
Host smart-65b1fe14-2bda-4d03-8271-a719540b1dd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855043225 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_fifo_reset_tx.855043225
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.2265060888
Short name T859
Test name
Test status
Simulation time 377300354 ps
CPU time 2.15 seconds
Started Jan 21 08:31:56 PM PST 24
Finished Jan 21 08:31:59 PM PST 24
Peak memory 202612 kb
Host smart-764ceb39-7005-410c-adc4-f3a3f2389727
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265060888 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.2265060888
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.4038122418
Short name T720
Test name
Test status
Simulation time 5996992613 ps
CPU time 5.93 seconds
Started Jan 21 08:31:46 PM PST 24
Finished Jan 21 08:31:53 PM PST 24
Peak memory 202652 kb
Host smart-2de7cbc9-62ce-4e6d-a357-80317aa2e7b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038122418 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.4038122418
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.1416800173
Short name T999
Test name
Test status
Simulation time 5980649406 ps
CPU time 2.59 seconds
Started Jan 21 08:31:45 PM PST 24
Finished Jan 21 08:31:48 PM PST 24
Peak memory 202636 kb
Host smart-176a7b95-0357-49a3-b637-6a56cca68e73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416800173 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.1416800173
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_perf.59703769
Short name T1481
Test name
Test status
Simulation time 511689543 ps
CPU time 3.24 seconds
Started Jan 21 08:31:53 PM PST 24
Finished Jan 21 08:31:57 PM PST 24
Peak memory 202676 kb
Host smart-8b646be8-14fa-4c5c-9e36-8efba7723603
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59703769 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.i2c_target_perf.59703769
Directory /workspace/28.i2c_target_perf/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.2281384985
Short name T278
Test name
Test status
Simulation time 10284999828 ps
CPU time 15.04 seconds
Started Jan 21 08:53:26 PM PST 24
Finished Jan 21 08:53:59 PM PST 24
Peak memory 202652 kb
Host smart-123f231d-9fb4-4864-af02-cda632daa274
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281384985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.2281384985
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_all.1331923872
Short name T1460
Test name
Test status
Simulation time 36034888464 ps
CPU time 1061.57 seconds
Started Jan 21 08:31:50 PM PST 24
Finished Jan 21 08:49:33 PM PST 24
Peak memory 5352228 kb
Host smart-47362bdb-d609-4383-9e2c-75d215becbec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331923872 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.i2c_target_stress_all.1331923872
Directory /workspace/28.i2c_target_stress_all/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.2156282125
Short name T590
Test name
Test status
Simulation time 606367343 ps
CPU time 11.31 seconds
Started Jan 21 09:08:34 PM PST 24
Finished Jan 21 09:09:04 PM PST 24
Peak memory 202552 kb
Host smart-794b456e-1956-4d53-9bcd-bdb38cbe247f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156282125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.2156282125
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.1827954921
Short name T312
Test name
Test status
Simulation time 48124329326 ps
CPU time 1070.59 seconds
Started Jan 21 08:31:40 PM PST 24
Finished Jan 21 08:49:32 PM PST 24
Peak memory 5700908 kb
Host smart-38a9d90a-2fa6-441e-94cc-99cea5f3d77f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827954921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.1827954921
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.2600643907
Short name T1303
Test name
Test status
Simulation time 23761576445 ps
CPU time 6.73 seconds
Started Jan 21 08:31:43 PM PST 24
Finished Jan 21 08:31:51 PM PST 24
Peak memory 207608 kb
Host smart-8e7b3e59-9240-42f0-99ff-6ccc6362203e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600643907 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.2600643907
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_ovf.4120109739
Short name T162
Test name
Test status
Simulation time 13281822730 ps
CPU time 154.02 seconds
Started Jan 21 08:31:49 PM PST 24
Finished Jan 21 08:34:25 PM PST 24
Peak memory 386152 kb
Host smart-0b0f638e-ca22-4023-8070-452ff3f4e879
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120109739 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_tx_ovf.4120109739
Directory /workspace/28.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/28.i2c_target_unexp_stop.1041092048
Short name T364
Test name
Test status
Simulation time 3139477642 ps
CPU time 4.03 seconds
Started Jan 21 08:31:44 PM PST 24
Finished Jan 21 08:31:49 PM PST 24
Peak memory 202628 kb
Host smart-89b8d02b-8db0-40e6-8aba-25138acb8a36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041092048 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.i2c_target_unexp_stop.1041092048
Directory /workspace/28.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/29.i2c_alert_test.3496100312
Short name T888
Test name
Test status
Simulation time 72940295 ps
CPU time 0.64 seconds
Started Jan 21 09:27:26 PM PST 24
Finished Jan 21 09:27:28 PM PST 24
Peak memory 201132 kb
Host smart-37aa447a-0cf2-4d61-a8b6-88cc6ce11384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496100312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.3496100312
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.3815102869
Short name T1300
Test name
Test status
Simulation time 37431287 ps
CPU time 1.77 seconds
Started Jan 21 08:32:17 PM PST 24
Finished Jan 21 08:32:20 PM PST 24
Peak memory 210688 kb
Host smart-46a96792-ff13-4074-bf74-aa5d3ab5e43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815102869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.3815102869
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.2947286883
Short name T1017
Test name
Test status
Simulation time 2658129483 ps
CPU time 5.53 seconds
Started Jan 21 08:54:08 PM PST 24
Finished Jan 21 08:54:23 PM PST 24
Peak memory 248892 kb
Host smart-d1bd59ca-6c73-45b8-80ad-6ab5d574cbf8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947286883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.2947286883
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.2062984410
Short name T280
Test name
Test status
Simulation time 7309651726 ps
CPU time 70.29 seconds
Started Jan 21 08:32:07 PM PST 24
Finished Jan 21 08:33:18 PM PST 24
Peak memory 639828 kb
Host smart-f4ba0fa8-0e66-4a71-878f-b518167f72bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062984410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.2062984410
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.3017750433
Short name T1059
Test name
Test status
Simulation time 7290148150 ps
CPU time 473.43 seconds
Started Jan 21 09:40:09 PM PST 24
Finished Jan 21 09:48:10 PM PST 24
Peak memory 1922656 kb
Host smart-bf90387a-c05b-465a-a307-2e064414df5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017750433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.3017750433
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.3669858908
Short name T237
Test name
Test status
Simulation time 255459817 ps
CPU time 0.8 seconds
Started Jan 21 08:32:01 PM PST 24
Finished Jan 21 08:32:02 PM PST 24
Peak memory 201516 kb
Host smart-fa3ad06c-2e5b-45b8-8a2c-8c72adb3b49b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669858908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.3669858908
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.2181207705
Short name T151
Test name
Test status
Simulation time 734378438 ps
CPU time 10.79 seconds
Started Jan 21 09:15:57 PM PST 24
Finished Jan 21 09:16:09 PM PST 24
Peak memory 202536 kb
Host smart-d347fa93-46d5-426d-bf13-3e39e1416282
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181207705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.2181207705
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.2754092582
Short name T103
Test name
Test status
Simulation time 37988068112 ps
CPU time 260.05 seconds
Started Jan 21 08:32:02 PM PST 24
Finished Jan 21 08:36:23 PM PST 24
Peak memory 1399008 kb
Host smart-25629ce9-f598-43cc-a8df-466e0bd1ce48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754092582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.2754092582
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.2183729703
Short name T233
Test name
Test status
Simulation time 11072996788 ps
CPU time 40.02 seconds
Started Jan 21 11:32:15 PM PST 24
Finished Jan 21 11:32:57 PM PST 24
Peak memory 278384 kb
Host smart-d196bd07-2f53-4d43-a021-8921f442180a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183729703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.2183729703
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.1555236251
Short name T515
Test name
Test status
Simulation time 34146262 ps
CPU time 0.63 seconds
Started Jan 21 08:31:59 PM PST 24
Finished Jan 21 08:32:01 PM PST 24
Peak memory 201544 kb
Host smart-916e139e-e967-4d02-992f-3e50356da643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555236251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.1555236251
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_rx_oversample.3606305065
Short name T37
Test name
Test status
Simulation time 2427008937 ps
CPU time 129.94 seconds
Started Jan 21 08:32:06 PM PST 24
Finished Jan 21 08:34:17 PM PST 24
Peak memory 300352 kb
Host smart-fe6f4511-b5db-422b-a346-ead9f249f94e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606305065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_rx_oversample
.3606305065
Directory /workspace/29.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.3615164504
Short name T1122
Test name
Test status
Simulation time 1065775317 ps
CPU time 55.96 seconds
Started Jan 21 08:32:00 PM PST 24
Finished Jan 21 08:32:57 PM PST 24
Peak memory 219092 kb
Host smart-49a53c2d-a003-4739-abfd-7ca380afc1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615164504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.3615164504
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.132758859
Short name T576
Test name
Test status
Simulation time 3043472123 ps
CPU time 14.61 seconds
Started Jan 21 09:56:46 PM PST 24
Finished Jan 21 09:57:09 PM PST 24
Peak memory 210764 kb
Host smart-0056957c-3a74-4725-97a7-cd4881e3464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132758859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.132758859
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.1917403837
Short name T285
Test name
Test status
Simulation time 6017991265 ps
CPU time 5.3 seconds
Started Jan 21 08:32:27 PM PST 24
Finished Jan 21 08:32:34 PM PST 24
Peak memory 202664 kb
Host smart-05f0198f-34c5-4875-8ec3-07aa11dfdb96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917403837 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.1917403837
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.2517054630
Short name T1294
Test name
Test status
Simulation time 10115358401 ps
CPU time 16.43 seconds
Started Jan 21 09:32:32 PM PST 24
Finished Jan 21 09:33:08 PM PST 24
Peak memory 305836 kb
Host smart-9a28ee07-a384-47fc-b088-e9755ee4e5ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517054630 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.2517054630
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.1922213160
Short name T1192
Test name
Test status
Simulation time 10307407810 ps
CPU time 6.6 seconds
Started Jan 21 08:32:24 PM PST 24
Finished Jan 21 08:32:32 PM PST 24
Peak memory 254500 kb
Host smart-301a9856-278d-4ebc-b875-ae3534ae9deb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922213160 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.1922213160
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.3214222828
Short name T707
Test name
Test status
Simulation time 778399038 ps
CPU time 2.25 seconds
Started Jan 21 08:32:25 PM PST 24
Finished Jan 21 08:32:28 PM PST 24
Peak memory 202660 kb
Host smart-12d0cd2b-1f06-47d1-9f9a-99ca9a6efbc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214222828 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.3214222828
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.3145285208
Short name T383
Test name
Test status
Simulation time 2011096595 ps
CPU time 5.13 seconds
Started Jan 21 08:57:24 PM PST 24
Finished Jan 21 08:57:57 PM PST 24
Peak memory 202568 kb
Host smart-cea40f32-e206-463f-a89a-509ba7076465
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145285208 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.3145285208
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.1690721452
Short name T670
Test name
Test status
Simulation time 17746948163 ps
CPU time 98.61 seconds
Started Jan 21 09:19:03 PM PST 24
Finished Jan 21 09:20:43 PM PST 24
Peak memory 1150972 kb
Host smart-7149bf65-7ced-4bc5-a01d-d72c423636d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690721452 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.1690721452
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_perf.1005476952
Short name T1440
Test name
Test status
Simulation time 879732149 ps
CPU time 4.97 seconds
Started Jan 21 08:32:24 PM PST 24
Finished Jan 21 08:32:30 PM PST 24
Peak memory 202512 kb
Host smart-a8d70791-0ba2-4cb0-93f6-4dc661a7c5c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005476952 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_perf.1005476952
Directory /workspace/29.i2c_target_perf/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.2222663700
Short name T1484
Test name
Test status
Simulation time 12833915465 ps
CPU time 60.41 seconds
Started Jan 21 08:32:13 PM PST 24
Finished Jan 21 08:33:15 PM PST 24
Peak memory 202664 kb
Host smart-6b0b11a5-f6b3-4814-8121-24e9853e677c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222663700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.2222663700
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_all.3281735021
Short name T816
Test name
Test status
Simulation time 53800883609 ps
CPU time 1710.51 seconds
Started Jan 21 08:32:24 PM PST 24
Finished Jan 21 09:00:56 PM PST 24
Peak memory 4306452 kb
Host smart-bc8162b5-df73-4f0a-8cae-4c83d0eebdfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281735021 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.i2c_target_stress_all.3281735021
Directory /workspace/29.i2c_target_stress_all/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.3059085440
Short name T1058
Test name
Test status
Simulation time 2989679123 ps
CPU time 28.19 seconds
Started Jan 21 08:32:19 PM PST 24
Finished Jan 21 08:32:48 PM PST 24
Peak memory 202640 kb
Host smart-8711af76-7dc3-4194-9173-70c483620493
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059085440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.3059085440
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.247106692
Short name T1007
Test name
Test status
Simulation time 32586374688 ps
CPU time 772.3 seconds
Started Jan 21 09:08:01 PM PST 24
Finished Jan 21 09:21:17 PM PST 24
Peak memory 4711860 kb
Host smart-e6044ac8-f1ce-4d03-a67a-8b67c96ca2c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247106692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c
_target_stress_wr.247106692
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.2885387428
Short name T769
Test name
Test status
Simulation time 33327546887 ps
CPU time 336.29 seconds
Started Jan 21 08:32:25 PM PST 24
Finished Jan 21 08:38:03 PM PST 24
Peak memory 1806316 kb
Host smart-b885563a-8915-46d0-9f0c-06014ce4f902
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885387428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.2885387428
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.4092731695
Short name T1417
Test name
Test status
Simulation time 7111924644 ps
CPU time 6.84 seconds
Started Jan 21 08:32:20 PM PST 24
Finished Jan 21 08:32:28 PM PST 24
Peak memory 202596 kb
Host smart-963d88c6-3e3a-427a-8e15-ff2a10f9631d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092731695 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.4092731695
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_ovf.2017379676
Short name T384
Test name
Test status
Simulation time 3226494310 ps
CPU time 361.42 seconds
Started Jan 21 08:32:19 PM PST 24
Finished Jan 21 08:38:22 PM PST 24
Peak memory 544316 kb
Host smart-e397f5c9-3697-4c34-8008-fb3129b7e8b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017379676 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_tx_ovf.2017379676
Directory /workspace/29.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/29.i2c_target_unexp_stop.3526452154
Short name T961
Test name
Test status
Simulation time 7556938425 ps
CPU time 8.87 seconds
Started Jan 21 08:32:25 PM PST 24
Finished Jan 21 08:32:35 PM PST 24
Peak memory 206460 kb
Host smart-fab866fd-3f55-45f4-9f42-7b59fdf0e35a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526452154 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 29.i2c_target_unexp_stop.3526452154
Directory /workspace/29.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/3.i2c_alert_test.1643720511
Short name T942
Test name
Test status
Simulation time 48343630 ps
CPU time 0.61 seconds
Started Jan 21 08:19:58 PM PST 24
Finished Jan 21 08:20:00 PM PST 24
Peak memory 201956 kb
Host smart-022c3e78-d087-45f9-bdd5-1f78aff2219a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643720511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.1643720511
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.1952011272
Short name T248
Test name
Test status
Simulation time 29910655 ps
CPU time 1.33 seconds
Started Jan 21 08:19:28 PM PST 24
Finished Jan 21 08:19:31 PM PST 24
Peak memory 210736 kb
Host smart-b0efa336-6913-44b7-8f81-a55302b57090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952011272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.1952011272
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.1045574244
Short name T202
Test name
Test status
Simulation time 367928920 ps
CPU time 17.6 seconds
Started Jan 21 08:19:13 PM PST 24
Finished Jan 21 08:19:33 PM PST 24
Peak memory 251060 kb
Host smart-3df72ddb-5676-4c7b-b621-163e9d05fb3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045574244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.1045574244
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.303776554
Short name T1392
Test name
Test status
Simulation time 1977332483 ps
CPU time 64.95 seconds
Started Jan 21 08:19:29 PM PST 24
Finished Jan 21 08:20:37 PM PST 24
Peak memory 557024 kb
Host smart-ddd5fafe-446c-483d-aa08-da4fccc9dc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303776554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.303776554
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.3225681909
Short name T1405
Test name
Test status
Simulation time 7286656687 ps
CPU time 997.17 seconds
Started Jan 21 09:41:28 PM PST 24
Finished Jan 21 09:58:07 PM PST 24
Peak memory 1767480 kb
Host smart-fcb4d854-5710-4684-aea2-c0ff2772313a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225681909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.3225681909
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.1225020712
Short name T840
Test name
Test status
Simulation time 547768470 ps
CPU time 0.96 seconds
Started Jan 21 08:19:14 PM PST 24
Finished Jan 21 08:19:17 PM PST 24
Peak memory 202348 kb
Host smart-a7c0313d-82dc-4fe8-914e-c6b284de4617
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225020712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.1225020712
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.1567260047
Short name T68
Test name
Test status
Simulation time 308182509 ps
CPU time 15.57 seconds
Started Jan 21 08:19:14 PM PST 24
Finished Jan 21 08:19:32 PM PST 24
Peak memory 202508 kb
Host smart-8e95c47b-7536-4a49-a8e8-b43e2f3f53a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567260047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
1567260047
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.3025184672
Short name T1249
Test name
Test status
Simulation time 3682849551 ps
CPU time 158.01 seconds
Started Jan 21 08:19:11 PM PST 24
Finished Jan 21 08:21:51 PM PST 24
Peak memory 1112664 kb
Host smart-bea1752c-3675-4c59-9341-cc4794aee5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025184672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.3025184672
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.1569864601
Short name T34
Test name
Test status
Simulation time 3053509703 ps
CPU time 30.07 seconds
Started Jan 21 08:19:54 PM PST 24
Finished Jan 21 08:20:26 PM PST 24
Peak memory 232084 kb
Host smart-913b78a1-0e0d-42c2-b1b7-9d60fe2708f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569864601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.1569864601
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.1278183513
Short name T411
Test name
Test status
Simulation time 19448611 ps
CPU time 0.65 seconds
Started Jan 21 08:19:14 PM PST 24
Finished Jan 21 08:19:17 PM PST 24
Peak memory 201512 kb
Host smart-e112ec29-cef2-47c6-bfe6-7d440ff8ee74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278183513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.1278183513
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.106917737
Short name T32
Test name
Test status
Simulation time 13576415514 ps
CPU time 194 seconds
Started Jan 21 08:19:29 PM PST 24
Finished Jan 21 08:22:45 PM PST 24
Peak memory 249924 kb
Host smart-46517f35-9fc3-4246-ad96-e2a4ec5fee7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106917737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.106917737
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_rx_oversample.632176928
Short name T1001
Test name
Test status
Simulation time 28960923089 ps
CPU time 186.45 seconds
Started Jan 21 08:19:13 PM PST 24
Finished Jan 21 08:22:22 PM PST 24
Peak memory 332716 kb
Host smart-1120bb95-e7cd-4e5a-bf4b-dfa684a5c03e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632176928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_rx_oversample.632176928
Directory /workspace/3.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.1448858556
Short name T607
Test name
Test status
Simulation time 2545461002 ps
CPU time 130.58 seconds
Started Jan 21 08:19:12 PM PST 24
Finished Jan 21 08:21:25 PM PST 24
Peak memory 230208 kb
Host smart-1a4679ff-4984-4fad-ae6d-d3b0368a5181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448858556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.1448858556
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.1159638544
Short name T786
Test name
Test status
Simulation time 8933579161 ps
CPU time 45.42 seconds
Started Jan 21 08:19:29 PM PST 24
Finished Jan 21 08:20:17 PM PST 24
Peak memory 210704 kb
Host smart-9db3f21e-c572-495f-8fbb-6bc6a07915d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159638544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.1159638544
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.469666536
Short name T101
Test name
Test status
Simulation time 236451348 ps
CPU time 0.84 seconds
Started Jan 21 08:43:34 PM PST 24
Finished Jan 21 08:43:35 PM PST 24
Peak memory 219172 kb
Host smart-5ee54752-40d8-43de-b548-476e62a0b3d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469666536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.469666536
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.2059853557
Short name T1130
Test name
Test status
Simulation time 1239565729 ps
CPU time 4.76 seconds
Started Jan 21 08:19:51 PM PST 24
Finished Jan 21 08:19:58 PM PST 24
Peak memory 202652 kb
Host smart-6a7b6ead-e726-4a96-807b-ee15cbd7d28c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059853557 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.2059853557
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.546806888
Short name T1247
Test name
Test status
Simulation time 10262179831 ps
CPU time 32.22 seconds
Started Jan 21 08:19:38 PM PST 24
Finished Jan 21 08:20:11 PM PST 24
Peak memory 367804 kb
Host smart-73c3f8f9-31bf-4341-b322-d7769dfdb2dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546806888 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_acq.546806888
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.1203665479
Short name T445
Test name
Test status
Simulation time 10171002296 ps
CPU time 26.59 seconds
Started Jan 21 08:19:38 PM PST 24
Finished Jan 21 08:20:05 PM PST 24
Peak memory 376780 kb
Host smart-6d2181f0-bc0f-4096-bd64-54fdcfec9de0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203665479 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.1203665479
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.1333722791
Short name T2
Test name
Test status
Simulation time 457917557 ps
CPU time 2.49 seconds
Started Jan 21 08:43:49 PM PST 24
Finished Jan 21 08:43:56 PM PST 24
Peak memory 202640 kb
Host smart-e8f08493-2223-4f89-81c0-074bfbe0c7bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333722791 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.1333722791
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.2183400473
Short name T1065
Test name
Test status
Simulation time 3314099845 ps
CPU time 4.12 seconds
Started Jan 21 08:19:33 PM PST 24
Finished Jan 21 08:19:39 PM PST 24
Peak memory 207284 kb
Host smart-631a99a6-6c40-46e3-a4e7-4b7507902cb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183400473 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.2183400473
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.641785227
Short name T424
Test name
Test status
Simulation time 7806813541 ps
CPU time 19.91 seconds
Started Jan 21 08:19:36 PM PST 24
Finished Jan 21 08:19:57 PM PST 24
Peak memory 504648 kb
Host smart-3cd64d0f-0c4e-4077-babe-6d8cd8781666
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641785227 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.641785227
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_perf.4241702053
Short name T1277
Test name
Test status
Simulation time 742869806 ps
CPU time 4.29 seconds
Started Jan 21 08:19:39 PM PST 24
Finished Jan 21 08:19:45 PM PST 24
Peak memory 202604 kb
Host smart-19308379-58c6-4041-a741-cbc96db9c9ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241702053 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_perf.4241702053
Directory /workspace/3.i2c_target_perf/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.3060545424
Short name T686
Test name
Test status
Simulation time 7585358842 ps
CPU time 19.92 seconds
Started Jan 21 08:19:23 PM PST 24
Finished Jan 21 08:19:44 PM PST 24
Peak memory 202652 kb
Host smart-7c3b6087-7612-48c1-bbbd-17e8a905f833
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060545424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.3060545424
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_all.1020574137
Short name T1451
Test name
Test status
Simulation time 26599648172 ps
CPU time 513.85 seconds
Started Jan 21 08:19:52 PM PST 24
Finished Jan 21 08:28:27 PM PST 24
Peak memory 2867128 kb
Host smart-f3935989-0193-480d-ba92-8dc05e636f5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020574137 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_target_stress_all.1020574137
Directory /workspace/3.i2c_target_stress_all/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.3512166096
Short name T1401
Test name
Test status
Simulation time 1524239912 ps
CPU time 7.09 seconds
Started Jan 21 08:19:30 PM PST 24
Finished Jan 21 08:19:39 PM PST 24
Peak memory 202496 kb
Host smart-23d433b7-a061-422f-a1cf-9692b57b1530
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512166096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.3512166096
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.1300384504
Short name T744
Test name
Test status
Simulation time 18218692363 ps
CPU time 357.85 seconds
Started Jan 21 08:19:34 PM PST 24
Finished Jan 21 08:25:33 PM PST 24
Peak memory 3574964 kb
Host smart-596a988e-06e0-45dc-a5bb-14b91029784f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300384504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.1300384504
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.798333663
Short name T791
Test name
Test status
Simulation time 11614147969 ps
CPU time 179.77 seconds
Started Jan 21 08:19:25 PM PST 24
Finished Jan 21 08:22:26 PM PST 24
Peak memory 1515024 kb
Host smart-714f8a05-8a60-4ae7-8149-c19fbfb90da3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798333663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_ta
rget_stretch.798333663
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.2573754675
Short name T29
Test name
Test status
Simulation time 1718548469 ps
CPU time 7.55 seconds
Started Jan 21 08:19:38 PM PST 24
Finished Jan 21 08:19:47 PM PST 24
Peak memory 202792 kb
Host smart-c172a66a-5253-4353-9793-6759d03138ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573754675 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.2573754675
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_ovf.873559121
Short name T1004
Test name
Test status
Simulation time 8890788838 ps
CPU time 48.52 seconds
Started Jan 21 08:19:33 PM PST 24
Finished Jan 21 08:20:23 PM PST 24
Peak memory 218560 kb
Host smart-152d7bf2-c5be-4723-a19b-5b5334f47788
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873559121 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_tx_ovf.873559121
Directory /workspace/3.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/3.i2c_target_unexp_stop.613475213
Short name T172
Test name
Test status
Simulation time 2049100638 ps
CPU time 8.38 seconds
Started Jan 21 08:19:39 PM PST 24
Finished Jan 21 08:19:48 PM PST 24
Peak memory 203128 kb
Host smart-c4a85541-d83e-4b91-b647-a32db3cbf92d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613475213 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_unexp_stop.613475213
Directory /workspace/3.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/30.i2c_alert_test.3349903856
Short name T1374
Test name
Test status
Simulation time 17125301 ps
CPU time 0.63 seconds
Started Jan 21 08:33:04 PM PST 24
Finished Jan 21 08:33:05 PM PST 24
Peak memory 201152 kb
Host smart-9d75463e-6eab-4b5e-a370-a88bc4f61679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349903856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.3349903856
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.1878107225
Short name T1159
Test name
Test status
Simulation time 148592946 ps
CPU time 1.19 seconds
Started Jan 21 08:32:47 PM PST 24
Finished Jan 21 08:32:49 PM PST 24
Peak memory 210716 kb
Host smart-fe0e8737-e2d8-4620-bedb-2d9a403c385d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878107225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.1878107225
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.2200933384
Short name T635
Test name
Test status
Simulation time 620448093 ps
CPU time 12.53 seconds
Started Jan 21 08:32:38 PM PST 24
Finished Jan 21 08:32:51 PM PST 24
Peak memory 343780 kb
Host smart-40f401c8-b518-477c-bd72-64eb365d035e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200933384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.2200933384
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.94974629
Short name T245
Test name
Test status
Simulation time 5211239338 ps
CPU time 217.2 seconds
Started Jan 21 08:32:44 PM PST 24
Finished Jan 21 08:36:22 PM PST 24
Peak memory 837728 kb
Host smart-130d4d28-a9b6-4b6f-b092-b3cd82e72932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94974629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.94974629
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.1885898122
Short name T1245
Test name
Test status
Simulation time 4872979553 ps
CPU time 562.97 seconds
Started Jan 21 08:32:39 PM PST 24
Finished Jan 21 08:42:02 PM PST 24
Peak memory 1238564 kb
Host smart-513a9583-eb76-4d50-9b3b-b09ca331671e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885898122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.1885898122
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.2114327652
Short name T757
Test name
Test status
Simulation time 163152644 ps
CPU time 1.08 seconds
Started Jan 21 08:32:37 PM PST 24
Finished Jan 21 08:32:39 PM PST 24
Peak memory 202336 kb
Host smart-253b68ed-b092-445e-aff3-eb406de793f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114327652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.2114327652
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.3279499954
Short name T150
Test name
Test status
Simulation time 748777700 ps
CPU time 4.86 seconds
Started Jan 21 08:32:36 PM PST 24
Finished Jan 21 08:32:41 PM PST 24
Peak memory 237392 kb
Host smart-f138f8c5-4175-441b-b917-ca946ed10387
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279499954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.3279499954
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.2257213117
Short name T460
Test name
Test status
Simulation time 7329467067 ps
CPU time 844.36 seconds
Started Jan 21 08:32:38 PM PST 24
Finished Jan 21 08:46:43 PM PST 24
Peak memory 1859428 kb
Host smart-ea54894b-00f5-4979-a2ba-12cccbbd7c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257213117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.2257213117
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.3254231429
Short name T730
Test name
Test status
Simulation time 2647206824 ps
CPU time 60.52 seconds
Started Jan 21 08:33:09 PM PST 24
Finished Jan 21 08:34:10 PM PST 24
Peak memory 299532 kb
Host smart-bcddd8b9-d3e7-46f6-b225-8d130d5be67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254231429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.3254231429
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.1390160822
Short name T1230
Test name
Test status
Simulation time 29275343 ps
CPU time 0.65 seconds
Started Jan 21 08:32:32 PM PST 24
Finished Jan 21 08:32:34 PM PST 24
Peak memory 201484 kb
Host smart-b037f846-7342-4088-a8e2-fec299300ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390160822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.1390160822
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.1489538875
Short name T145
Test name
Test status
Simulation time 3240157638 ps
CPU time 40.87 seconds
Started Jan 21 08:32:42 PM PST 24
Finished Jan 21 08:33:24 PM PST 24
Peak memory 210752 kb
Host smart-f7871a18-1fed-4c3f-8cb1-688c12bcf8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489538875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.1489538875
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_rx_oversample.3355364011
Short name T1206
Test name
Test status
Simulation time 2861073697 ps
CPU time 141.59 seconds
Started Jan 21 08:32:30 PM PST 24
Finished Jan 21 08:34:53 PM PST 24
Peak memory 346416 kb
Host smart-178a15df-ddd8-4aa5-9709-f01fbcb2f4b5
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355364011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_rx_oversample
.3355364011
Directory /workspace/30.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.1920811985
Short name T599
Test name
Test status
Simulation time 1796600268 ps
CPU time 47.6 seconds
Started Jan 21 08:32:32 PM PST 24
Finished Jan 21 08:33:20 PM PST 24
Peak memory 257856 kb
Host smart-23bf142a-70a5-4b61-af92-1c83439374a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920811985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.1920811985
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.1066896702
Short name T1105
Test name
Test status
Simulation time 3776093547 ps
CPU time 27.23 seconds
Started Jan 21 08:32:47 PM PST 24
Finished Jan 21 08:33:17 PM PST 24
Peak memory 210748 kb
Host smart-bf4114bd-f7ae-4edf-a42f-2afaed3d48dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066896702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.1066896702
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.3300453165
Short name T625
Test name
Test status
Simulation time 9254015555 ps
CPU time 3.44 seconds
Started Jan 21 08:32:54 PM PST 24
Finished Jan 21 08:32:58 PM PST 24
Peak memory 202612 kb
Host smart-b534700b-dce7-4350-82f9-2cdccffd7bae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300453165 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.3300453165
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.2085566542
Short name T901
Test name
Test status
Simulation time 11099369458 ps
CPU time 3.77 seconds
Started Jan 21 08:32:49 PM PST 24
Finished Jan 21 08:32:55 PM PST 24
Peak memory 218908 kb
Host smart-e88bb10f-0c31-48f8-b502-045585357137
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085566542 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.2085566542
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.1856481
Short name T18
Test name
Test status
Simulation time 10271585149 ps
CPU time 37.61 seconds
Started Jan 21 08:32:56 PM PST 24
Finished Jan 21 08:33:34 PM PST 24
Peak memory 477812 kb
Host smart-5f0cf3c2-fbb1-4cee-b2d5-0005a936142a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856481 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.i2c_target_fifo_reset_tx.1856481
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.1080661
Short name T1317
Test name
Test status
Simulation time 2058309494 ps
CPU time 2.67 seconds
Started Jan 21 08:33:00 PM PST 24
Finished Jan 21 08:33:03 PM PST 24
Peak memory 202576 kb
Host smart-e0e1301f-a865-4b3e-89f7-427ede53f20d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080661 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.i2c_target_hrst.1080661
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.43504529
Short name T1333
Test name
Test status
Simulation time 859330681 ps
CPU time 4.3 seconds
Started Jan 21 08:32:48 PM PST 24
Finished Jan 21 08:32:55 PM PST 24
Peak memory 202628 kb
Host smart-15708368-157c-4199-b5f9-aebc7dfaf3e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43504529 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_intr_smoke.43504529
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.3074605014
Short name T1306
Test name
Test status
Simulation time 11873521678 ps
CPU time 307.99 seconds
Started Jan 21 08:32:50 PM PST 24
Finished Jan 21 08:37:59 PM PST 24
Peak memory 2603632 kb
Host smart-43222ef2-b7bf-4c42-8a63-fecfc43afa55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074605014 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.3074605014
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_perf.145036950
Short name T1011
Test name
Test status
Simulation time 824796568 ps
CPU time 4.94 seconds
Started Jan 21 08:32:52 PM PST 24
Finished Jan 21 08:32:58 PM PST 24
Peak memory 204164 kb
Host smart-2e9e021a-cf51-4286-b35c-678fe9d5f3f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145036950 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.i2c_target_perf.145036950
Directory /workspace/30.i2c_target_perf/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.2364868226
Short name T492
Test name
Test status
Simulation time 866923746 ps
CPU time 23.86 seconds
Started Jan 21 08:32:42 PM PST 24
Finished Jan 21 08:33:06 PM PST 24
Peak memory 202536 kb
Host smart-d824bb06-6d93-4f94-aa32-61e47367aabd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364868226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.2364868226
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_all.333517311
Short name T1449
Test name
Test status
Simulation time 79417469576 ps
CPU time 2328.67 seconds
Started Jan 21 08:32:54 PM PST 24
Finished Jan 21 09:11:44 PM PST 24
Peak memory 772256 kb
Host smart-904bfda4-b16d-44fd-9a9e-c5e86b8f7778
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333517311 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.i2c_target_stress_all.333517311
Directory /workspace/30.i2c_target_stress_all/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.3269061380
Short name T542
Test name
Test status
Simulation time 1986529850 ps
CPU time 81.5 seconds
Started Jan 21 08:32:42 PM PST 24
Finished Jan 21 08:34:04 PM PST 24
Peak memory 202860 kb
Host smart-9b3c4da8-f268-49ae-b13f-aa941b312838
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269061380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.3269061380
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.3506365491
Short name T349
Test name
Test status
Simulation time 47129006311 ps
CPU time 1131.23 seconds
Started Jan 21 08:32:47 PM PST 24
Finished Jan 21 08:51:41 PM PST 24
Peak memory 5385776 kb
Host smart-d35cb36d-26ec-47fe-bc18-ee0c3bd40274
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506365491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.3506365491
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.2769619303
Short name T543
Test name
Test status
Simulation time 1621993029 ps
CPU time 7.5 seconds
Started Jan 21 08:32:48 PM PST 24
Finished Jan 21 08:32:58 PM PST 24
Peak memory 202552 kb
Host smart-93fda5d5-59e0-4e97-979e-d4d42b15be12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769619303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.2769619303
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_ovf.87650681
Short name T1412
Test name
Test status
Simulation time 42937734725 ps
CPU time 114.51 seconds
Started Jan 21 08:32:49 PM PST 24
Finished Jan 21 08:34:45 PM PST 24
Peak memory 324960 kb
Host smart-2b01bc54-d95a-4563-b955-d78b62ad24ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87650681 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_tx_ovf.87650681
Directory /workspace/30.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/30.i2c_target_unexp_stop.106700401
Short name T168
Test name
Test status
Simulation time 16654092609 ps
CPU time 6.11 seconds
Started Jan 21 08:32:50 PM PST 24
Finished Jan 21 08:32:57 PM PST 24
Peak memory 202632 kb
Host smart-c23139c1-50e4-46f8-a531-d9e91732f4b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106700401 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_unexp_stop.106700401
Directory /workspace/30.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/31.i2c_alert_test.2033266484
Short name T442
Test name
Test status
Simulation time 109586901 ps
CPU time 0.59 seconds
Started Jan 21 08:33:39 PM PST 24
Finished Jan 21 08:33:44 PM PST 24
Peak memory 201084 kb
Host smart-a2bd4523-487c-4c2e-ba88-aa630357851b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033266484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.2033266484
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.3991864085
Short name T346
Test name
Test status
Simulation time 53282975 ps
CPU time 1.6 seconds
Started Jan 21 08:33:14 PM PST 24
Finished Jan 21 08:33:17 PM PST 24
Peak memory 210728 kb
Host smart-e5e6f5f3-8dbd-4ebe-93f6-d25bc389a213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991864085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.3991864085
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.2849115847
Short name T1433
Test name
Test status
Simulation time 1033211631 ps
CPU time 28.62 seconds
Started Jan 21 08:33:12 PM PST 24
Finished Jan 21 08:33:41 PM PST 24
Peak memory 319748 kb
Host smart-b1f879fc-db1e-41a2-bf61-e8f5693b3b91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849115847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.2849115847
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.4033157370
Short name T814
Test name
Test status
Simulation time 2181355596 ps
CPU time 76.34 seconds
Started Jan 21 08:33:15 PM PST 24
Finished Jan 21 08:34:34 PM PST 24
Peak memory 691708 kb
Host smart-78f68288-1506-4d9f-86fa-49e56c9ec5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033157370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.4033157370
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.3006387341
Short name T230
Test name
Test status
Simulation time 79659669 ps
CPU time 0.94 seconds
Started Jan 21 08:33:11 PM PST 24
Finished Jan 21 08:33:13 PM PST 24
Peak memory 202316 kb
Host smart-25c1b0bd-342d-467d-bca7-ce4c1fa64987
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006387341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.3006387341
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.2809959582
Short name T228
Test name
Test status
Simulation time 1415899151 ps
CPU time 6.51 seconds
Started Jan 21 08:33:15 PM PST 24
Finished Jan 21 08:33:24 PM PST 24
Peak memory 252100 kb
Host smart-2676db18-1e41-4823-b885-b886d302acdf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809959582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.2809959582
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.489884019
Short name T930
Test name
Test status
Simulation time 6840916619 ps
CPU time 445.01 seconds
Started Jan 21 08:33:14 PM PST 24
Finished Jan 21 08:40:40 PM PST 24
Peak memory 1865632 kb
Host smart-aaa42426-7a1d-4d84-83f4-7c4b6dab998f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489884019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.489884019
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.4003566381
Short name T482
Test name
Test status
Simulation time 32593415132 ps
CPU time 141.5 seconds
Started Jan 21 08:33:40 PM PST 24
Finished Jan 21 08:36:05 PM PST 24
Peak memory 227004 kb
Host smart-0f08fb5c-2831-4b39-82eb-72018d6e6264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003566381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.4003566381
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.3683875413
Short name T1364
Test name
Test status
Simulation time 29184598 ps
CPU time 0.64 seconds
Started Jan 21 08:33:12 PM PST 24
Finished Jan 21 08:33:13 PM PST 24
Peak memory 201512 kb
Host smart-11b64d2d-ea83-4ada-a863-fd728ae78ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683875413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.3683875413
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.2302266797
Short name T641
Test name
Test status
Simulation time 2651260414 ps
CPU time 51.98 seconds
Started Jan 21 08:33:15 PM PST 24
Finished Jan 21 08:34:08 PM PST 24
Peak memory 219960 kb
Host smart-88b737e1-c5c5-4c08-ab78-12f2cf5d283a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302266797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.2302266797
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_rx_oversample.2078441468
Short name T1019
Test name
Test status
Simulation time 9144933338 ps
CPU time 127.84 seconds
Started Jan 21 08:33:12 PM PST 24
Finished Jan 21 08:35:22 PM PST 24
Peak memory 318148 kb
Host smart-b28f2c2b-946b-4f7f-954e-58f6007570d4
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078441468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_rx_oversample
.2078441468
Directory /workspace/31.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.2659463009
Short name T1188
Test name
Test status
Simulation time 5011130361 ps
CPU time 31.74 seconds
Started Jan 21 08:33:06 PM PST 24
Finished Jan 21 08:33:38 PM PST 24
Peak memory 275640 kb
Host smart-019851e3-51aa-42d6-bf9a-16d8bd0d7d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659463009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.2659463009
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.1990942850
Short name T1298
Test name
Test status
Simulation time 3616291333 ps
CPU time 15.75 seconds
Started Jan 21 08:33:16 PM PST 24
Finished Jan 21 08:33:34 PM PST 24
Peak memory 212040 kb
Host smart-c4961af0-afac-4f20-97f7-4fea54cb7a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990942850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.1990942850
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.338961840
Short name T1436
Test name
Test status
Simulation time 8150484191 ps
CPU time 5.54 seconds
Started Jan 21 08:33:43 PM PST 24
Finished Jan 21 08:33:56 PM PST 24
Peak memory 202672 kb
Host smart-2e21335d-e355-4bf1-abb6-4222ceefedba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338961840 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.338961840
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.3680750098
Short name T1389
Test name
Test status
Simulation time 10064622061 ps
CPU time 56.26 seconds
Started Jan 21 08:33:37 PM PST 24
Finished Jan 21 08:34:40 PM PST 24
Peak memory 473956 kb
Host smart-d7e172e3-5bb1-42cc-9849-1b9177a9d17e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680750098 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.3680750098
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.1767739561
Short name T105
Test name
Test status
Simulation time 10070716343 ps
CPU time 59.78 seconds
Started Jan 21 08:33:36 PM PST 24
Finished Jan 21 08:34:43 PM PST 24
Peak memory 556148 kb
Host smart-56921796-434f-45e5-936e-ad3e72d68d4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767739561 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.1767739561
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.335014937
Short name T327
Test name
Test status
Simulation time 5378608600 ps
CPU time 3 seconds
Started Jan 21 08:33:42 PM PST 24
Finished Jan 21 08:33:53 PM PST 24
Peak memory 202688 kb
Host smart-fba6a323-4e56-4abf-99ea-06abc795596d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335014937 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.i2c_target_hrst.335014937
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.693442327
Short name T1283
Test name
Test status
Simulation time 4148721933 ps
CPU time 6.69 seconds
Started Jan 21 08:33:22 PM PST 24
Finished Jan 21 08:33:29 PM PST 24
Peak memory 213268 kb
Host smart-23dd1aa6-934a-49ea-a485-9efdaa02012f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693442327 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_intr_smoke.693442327
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.714229783
Short name T1107
Test name
Test status
Simulation time 5389921675 ps
CPU time 59.33 seconds
Started Jan 21 08:33:30 PM PST 24
Finished Jan 21 08:34:32 PM PST 24
Peak memory 1121904 kb
Host smart-e1f22a6c-1ccd-4794-a775-8888066723d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714229783 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.714229783
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_perf.3934805455
Short name T600
Test name
Test status
Simulation time 1824709360 ps
CPU time 4.29 seconds
Started Jan 21 08:33:37 PM PST 24
Finished Jan 21 08:33:48 PM PST 24
Peak memory 203996 kb
Host smart-402bd2ff-d1d1-4881-ba53-63f0d68876d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934805455 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_perf.3934805455
Directory /workspace/31.i2c_target_perf/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.993535769
Short name T1464
Test name
Test status
Simulation time 1501075222 ps
CPU time 9.65 seconds
Started Jan 21 08:33:26 PM PST 24
Finished Jan 21 08:33:36 PM PST 24
Peak memory 202516 kb
Host smart-63d15fb3-816b-42c3-aace-cc55a7397d06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993535769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_tar
get_smoke.993535769
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_all.3636549472
Short name T947
Test name
Test status
Simulation time 92812367103 ps
CPU time 1928.62 seconds
Started Jan 21 08:33:37 PM PST 24
Finished Jan 21 09:05:52 PM PST 24
Peak memory 1300868 kb
Host smart-be289340-af55-4cda-8d24-252bd9beadc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636549472 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_stress_all.3636549472
Directory /workspace/31.i2c_target_stress_all/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.1797811611
Short name T899
Test name
Test status
Simulation time 4890832386 ps
CPU time 35.68 seconds
Started Jan 21 08:33:21 PM PST 24
Finished Jan 21 08:33:58 PM PST 24
Peak memory 228624 kb
Host smart-20e4967e-b91c-44f8-a860-2edab241ed79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797811611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.1797811611
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.1142461059
Short name T1459
Test name
Test status
Simulation time 29627807006 ps
CPU time 164.11 seconds
Started Jan 21 08:33:22 PM PST 24
Finished Jan 21 08:36:07 PM PST 24
Peak memory 1755360 kb
Host smart-499bff00-00e9-43ef-9b6a-53d995a2a820
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142461059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.1142461059
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.2754564543
Short name T30
Test name
Test status
Simulation time 1761061029 ps
CPU time 7.18 seconds
Started Jan 21 08:33:31 PM PST 24
Finished Jan 21 08:33:40 PM PST 24
Peak memory 202572 kb
Host smart-80b27049-c043-428a-8b15-1b5df82a98d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754564543 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.2754564543
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_ovf.1962391960
Short name T824
Test name
Test status
Simulation time 2759442760 ps
CPU time 170.57 seconds
Started Jan 21 08:33:31 PM PST 24
Finished Jan 21 08:36:23 PM PST 24
Peak memory 395204 kb
Host smart-a85eb6ad-452c-4acc-b036-8addffbd87e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962391960 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_tx_ovf.1962391960
Directory /workspace/31.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/31.i2c_target_unexp_stop.2443858358
Short name T1163
Test name
Test status
Simulation time 1313668916 ps
CPU time 6.36 seconds
Started Jan 21 08:33:37 PM PST 24
Finished Jan 21 08:33:50 PM PST 24
Peak memory 205312 kb
Host smart-2f211119-1fa3-4a38-a69a-befa874d5e7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443858358 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 31.i2c_target_unexp_stop.2443858358
Directory /workspace/31.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/32.i2c_alert_test.1163936843
Short name T266
Test name
Test status
Simulation time 29865423 ps
CPU time 0.61 seconds
Started Jan 21 09:01:33 PM PST 24
Finished Jan 21 09:01:52 PM PST 24
Peak memory 201160 kb
Host smart-31e62128-4e6f-427b-bdf8-99f1e5eae9b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163936843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.1163936843
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.4167133421
Short name T536
Test name
Test status
Simulation time 33344406 ps
CPU time 1.57 seconds
Started Jan 21 08:33:54 PM PST 24
Finished Jan 21 08:33:56 PM PST 24
Peak memory 210736 kb
Host smart-3f7bb788-df11-44b6-a3ae-50293b687048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167133421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.4167133421
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.1191331884
Short name T1189
Test name
Test status
Simulation time 348403463 ps
CPU time 18.67 seconds
Started Jan 21 08:33:51 PM PST 24
Finished Jan 21 08:34:11 PM PST 24
Peak memory 275988 kb
Host smart-ff8bb3d8-1619-4903-bc95-635d79d59298
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191331884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.1191331884
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.594072548
Short name T1160
Test name
Test status
Simulation time 8024746004 ps
CPU time 73.98 seconds
Started Jan 21 08:33:51 PM PST 24
Finished Jan 21 08:35:06 PM PST 24
Peak memory 663024 kb
Host smart-33c5b024-2b98-4496-82fb-0384dc427be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594072548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.594072548
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.248524266
Short name T596
Test name
Test status
Simulation time 6028686005 ps
CPU time 478.95 seconds
Started Jan 21 08:33:45 PM PST 24
Finished Jan 21 08:41:50 PM PST 24
Peak memory 1738180 kb
Host smart-722b036a-2e8b-45e8-801f-8893e1d05ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248524266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.248524266
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.3634150443
Short name T311
Test name
Test status
Simulation time 121086635 ps
CPU time 1.12 seconds
Started Jan 21 08:33:51 PM PST 24
Finished Jan 21 08:33:53 PM PST 24
Peak memory 202672 kb
Host smart-8ae9626a-8283-4657-b2b9-a3d207e72b51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634150443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.3634150443
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.1913903375
Short name T493
Test name
Test status
Simulation time 1635467771 ps
CPU time 13.42 seconds
Started Jan 21 08:33:49 PM PST 24
Finished Jan 21 08:34:05 PM PST 24
Peak memory 246464 kb
Host smart-ee725b2f-ab02-45a8-ac37-bfc69c05c07b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913903375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.1913903375
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.84082134
Short name T454
Test name
Test status
Simulation time 4144242321 ps
CPU time 169.24 seconds
Started Jan 21 08:33:43 PM PST 24
Finished Jan 21 08:36:39 PM PST 24
Peak memory 1063332 kb
Host smart-c10f1ecb-90ac-4f08-9ac5-36045e6acd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84082134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.84082134
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.3573524786
Short name T735
Test name
Test status
Simulation time 2581360724 ps
CPU time 48.58 seconds
Started Jan 21 08:34:18 PM PST 24
Finished Jan 21 08:35:08 PM PST 24
Peak memory 258828 kb
Host smart-17f29d41-e4ad-4e78-a073-5acb040f0a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573524786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.3573524786
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.3629015383
Short name T732
Test name
Test status
Simulation time 28109421 ps
CPU time 0.65 seconds
Started Jan 21 08:33:45 PM PST 24
Finished Jan 21 08:33:52 PM PST 24
Peak memory 201560 kb
Host smart-fee1bcdf-1e36-4703-999d-52fe54c2b79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629015383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.3629015383
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.895555551
Short name T1178
Test name
Test status
Simulation time 1246769767 ps
CPU time 5.34 seconds
Started Jan 21 10:31:08 PM PST 24
Finished Jan 21 10:31:15 PM PST 24
Peak memory 210736 kb
Host smart-e56fcc58-c67f-4bc8-bd67-9f1c84fcb0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895555551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.895555551
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_rx_oversample.40031852
Short name T309
Test name
Test status
Simulation time 3310757431 ps
CPU time 169.52 seconds
Started Jan 21 08:33:44 PM PST 24
Finished Jan 21 08:36:40 PM PST 24
Peak memory 333460 kb
Host smart-ca7cf79b-e841-4fb6-931a-97aa6512b313
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40031852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_rx_oversample.40031852
Directory /workspace/32.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.3648834243
Short name T873
Test name
Test status
Simulation time 2506028659 ps
CPU time 141.15 seconds
Started Jan 21 08:33:47 PM PST 24
Finished Jan 21 08:36:12 PM PST 24
Peak memory 259736 kb
Host smart-d186afe6-0b38-4274-b888-3a83cdab2d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648834243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.3648834243
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.1448705340
Short name T644
Test name
Test status
Simulation time 2425964181 ps
CPU time 19.64 seconds
Started Jan 21 08:33:55 PM PST 24
Finished Jan 21 08:34:15 PM PST 24
Peak memory 216480 kb
Host smart-e8334272-3bc1-4842-b934-7778265779d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448705340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.1448705340
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.106816240
Short name T1248
Test name
Test status
Simulation time 3196637197 ps
CPU time 3.47 seconds
Started Jan 21 08:34:19 PM PST 24
Finished Jan 21 08:34:24 PM PST 24
Peak memory 202620 kb
Host smart-23ca8e28-2244-4e34-ba4b-c7bcf0e9745f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106816240 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.106816240
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.2074942764
Short name T359
Test name
Test status
Simulation time 10047293702 ps
CPU time 68.75 seconds
Started Jan 21 08:34:17 PM PST 24
Finished Jan 21 08:35:27 PM PST 24
Peak memory 512212 kb
Host smart-f3bfb79b-7325-4d29-81be-c2c0bbbb2a65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074942764 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.2074942764
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.2117919307
Short name T756
Test name
Test status
Simulation time 10100650058 ps
CPU time 84.3 seconds
Started Jan 21 08:34:19 PM PST 24
Finished Jan 21 08:35:44 PM PST 24
Peak memory 606448 kb
Host smart-f3cc202e-e7a3-42d6-8e03-22906f83b90a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117919307 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.2117919307
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.3893224139
Short name T601
Test name
Test status
Simulation time 3434382987 ps
CPU time 2.31 seconds
Started Jan 21 08:34:18 PM PST 24
Finished Jan 21 08:34:21 PM PST 24
Peak memory 202644 kb
Host smart-7e3e664c-a74b-4aad-b534-edb00518560e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893224139 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.3893224139
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.2808657563
Short name T283
Test name
Test status
Simulation time 1697080251 ps
CPU time 8.25 seconds
Started Jan 21 08:34:03 PM PST 24
Finished Jan 21 08:34:12 PM PST 24
Peak memory 214056 kb
Host smart-fc30cc14-c9f1-4434-93dc-8fc20cec0b88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808657563 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.2808657563
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.1198301906
Short name T417
Test name
Test status
Simulation time 16030674856 ps
CPU time 50.28 seconds
Started Jan 21 08:34:09 PM PST 24
Finished Jan 21 08:35:05 PM PST 24
Peak memory 736772 kb
Host smart-97411466-fd95-410c-ace0-1af103014b9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198301906 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.1198301906
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_perf.457383059
Short name T226
Test name
Test status
Simulation time 4164443099 ps
CPU time 5.23 seconds
Started Jan 21 08:34:18 PM PST 24
Finished Jan 21 08:34:24 PM PST 24
Peak memory 202572 kb
Host smart-8ed16987-4cb2-41f2-8b1b-ef94229ff5a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457383059 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.i2c_target_perf.457383059
Directory /workspace/32.i2c_target_perf/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.440649420
Short name T1169
Test name
Test status
Simulation time 3923381644 ps
CPU time 12.04 seconds
Started Jan 21 08:34:01 PM PST 24
Finished Jan 21 08:34:14 PM PST 24
Peak memory 202640 kb
Host smart-78fd7000-a709-4ef0-82db-58d926a153dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440649420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_tar
get_smoke.440649420
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_all.1555470296
Short name T268
Test name
Test status
Simulation time 39837967213 ps
CPU time 3219.51 seconds
Started Jan 21 08:34:17 PM PST 24
Finished Jan 21 09:27:58 PM PST 24
Peak memory 1140160 kb
Host smart-16b27594-7d0b-408b-9656-e41cfa53dad6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555470296 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_target_stress_all.1555470296
Directory /workspace/32.i2c_target_stress_all/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.3457105599
Short name T294
Test name
Test status
Simulation time 4807492945 ps
CPU time 26.42 seconds
Started Jan 21 08:34:01 PM PST 24
Finished Jan 21 08:34:29 PM PST 24
Peak memory 215100 kb
Host smart-bec50af3-ad56-499f-8222-47f212a4499a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457105599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.3457105599
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.2937047443
Short name T1501
Test name
Test status
Simulation time 55351266332 ps
CPU time 479.46 seconds
Started Jan 21 08:34:03 PM PST 24
Finished Jan 21 08:42:04 PM PST 24
Peak memory 3237508 kb
Host smart-ee74461e-9959-4ab6-af14-0a6265f7410b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937047443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.2937047443
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.2195894542
Short name T1217
Test name
Test status
Simulation time 37092209391 ps
CPU time 350.67 seconds
Started Jan 21 08:34:03 PM PST 24
Finished Jan 21 08:39:55 PM PST 24
Peak memory 2144460 kb
Host smart-f4799bbf-1cd9-4602-baec-dabce1a05775
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195894542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.2195894542
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.1591600948
Short name T1028
Test name
Test status
Simulation time 7105660963 ps
CPU time 7.03 seconds
Started Jan 21 08:34:09 PM PST 24
Finished Jan 21 08:34:21 PM PST 24
Peak memory 202636 kb
Host smart-bda07350-b489-4495-bde4-7314683fb7e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591600948 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.1591600948
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_ovf.612854839
Short name T845
Test name
Test status
Simulation time 5636308112 ps
CPU time 88.04 seconds
Started Jan 21 08:34:09 PM PST 24
Finished Jan 21 08:35:42 PM PST 24
Peak memory 360068 kb
Host smart-08278522-7654-4a07-b90f-f1af56ab8da7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612854839 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_tx_ovf.612854839
Directory /workspace/32.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/32.i2c_target_unexp_stop.1296817878
Short name T273
Test name
Test status
Simulation time 1467136330 ps
CPU time 9.21 seconds
Started Jan 21 08:34:17 PM PST 24
Finished Jan 21 08:34:28 PM PST 24
Peak memory 202568 kb
Host smart-214e2927-af5c-4f19-9733-6042a7e27160
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296817878 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.i2c_target_unexp_stop.1296817878
Directory /workspace/32.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/33.i2c_alert_test.600663196
Short name T545
Test name
Test status
Simulation time 21043761 ps
CPU time 0.6 seconds
Started Jan 21 08:35:05 PM PST 24
Finished Jan 21 08:35:06 PM PST 24
Peak memory 201956 kb
Host smart-5c421182-0351-46f1-9687-438d7d16e823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600663196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.600663196
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.1316970886
Short name T307
Test name
Test status
Simulation time 138240739 ps
CPU time 1.1 seconds
Started Jan 21 08:34:39 PM PST 24
Finished Jan 21 08:34:41 PM PST 24
Peak memory 202564 kb
Host smart-ffb7e1b0-b8d5-483e-b701-fcfeaf09e198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316970886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.1316970886
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.3121831193
Short name T938
Test name
Test status
Simulation time 588898027 ps
CPU time 10.68 seconds
Started Jan 21 09:01:18 PM PST 24
Finished Jan 21 09:01:52 PM PST 24
Peak memory 325060 kb
Host smart-896fab19-0784-4ed7-970c-3264153651cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121831193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.3121831193
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.2520334203
Short name T420
Test name
Test status
Simulation time 6284543177 ps
CPU time 117.78 seconds
Started Jan 21 08:34:37 PM PST 24
Finished Jan 21 08:36:36 PM PST 24
Peak memory 790940 kb
Host smart-aafd6226-2fa1-42e0-ad47-7e3113c81fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520334203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.2520334203
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.2422666990
Short name T1100
Test name
Test status
Simulation time 16199856796 ps
CPU time 213.43 seconds
Started Jan 21 08:34:32 PM PST 24
Finished Jan 21 08:38:07 PM PST 24
Peak memory 1175228 kb
Host smart-19c2e1b2-048b-4d76-abba-79c5b2cf5410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422666990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2422666990
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.1180854192
Short name T405
Test name
Test status
Simulation time 107709752 ps
CPU time 0.78 seconds
Started Jan 21 09:44:11 PM PST 24
Finished Jan 21 09:44:18 PM PST 24
Peak memory 201448 kb
Host smart-d46c24da-7898-4366-93fd-5a8947fc0f05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180854192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.1180854192
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.2285460260
Short name T1070
Test name
Test status
Simulation time 761298920 ps
CPU time 9.89 seconds
Started Jan 21 08:34:30 PM PST 24
Finished Jan 21 08:34:41 PM PST 24
Peak memory 202496 kb
Host smart-70ef1659-d631-46e0-a11d-6e8cd7e44c50
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285460260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.2285460260
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.3901187770
Short name T770
Test name
Test status
Simulation time 7287758147 ps
CPU time 158.74 seconds
Started Jan 21 08:34:33 PM PST 24
Finished Jan 21 08:37:13 PM PST 24
Peak memory 1047652 kb
Host smart-4f3f2331-42a1-4f34-a1ef-e7230ed045d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901187770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.3901187770
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.1162318630
Short name T512
Test name
Test status
Simulation time 5353960656 ps
CPU time 64.75 seconds
Started Jan 21 08:34:59 PM PST 24
Finished Jan 21 08:36:04 PM PST 24
Peak memory 259072 kb
Host smart-3f15cb8f-451f-49d1-906a-82996b849630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162318630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.1162318630
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.3452609846
Short name T1153
Test name
Test status
Simulation time 26974552 ps
CPU time 0.64 seconds
Started Jan 21 08:34:30 PM PST 24
Finished Jan 21 08:34:32 PM PST 24
Peak memory 201416 kb
Host smart-95f2b9f2-069b-4ca4-9166-edc36c17519c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452609846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3452609846
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_rx_oversample.2282000308
Short name T1127
Test name
Test status
Simulation time 8160671081 ps
CPU time 119.09 seconds
Started Jan 21 08:34:24 PM PST 24
Finished Jan 21 08:36:24 PM PST 24
Peak memory 313056 kb
Host smart-732e2e9b-09aa-49f2-ae0b-c29de5d516f5
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282000308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_rx_oversample
.2282000308
Directory /workspace/33.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.2229981885
Short name T1128
Test name
Test status
Simulation time 10375588991 ps
CPU time 87.48 seconds
Started Jan 21 08:34:28 PM PST 24
Finished Jan 21 08:35:57 PM PST 24
Peak memory 331564 kb
Host smart-38132c95-5f6f-439c-8bba-0843f81c9198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229981885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2229981885
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.2019255813
Short name T1023
Test name
Test status
Simulation time 10345195780 ps
CPU time 15.62 seconds
Started Jan 21 08:34:39 PM PST 24
Finished Jan 21 08:34:55 PM PST 24
Peak memory 218944 kb
Host smart-f1c385db-6d59-4b99-b5a2-aec8373ac61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019255813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.2019255813
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.2895456620
Short name T1184
Test name
Test status
Simulation time 11822525577 ps
CPU time 5.76 seconds
Started Jan 21 08:49:13 PM PST 24
Finished Jan 21 08:49:24 PM PST 24
Peak memory 202684 kb
Host smart-bd628ccf-9281-4fff-b0c0-a76f77601321
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895456620 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.2895456620
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.1249048700
Short name T688
Test name
Test status
Simulation time 10060095501 ps
CPU time 23.61 seconds
Started Jan 21 08:34:52 PM PST 24
Finished Jan 21 08:35:17 PM PST 24
Peak memory 323084 kb
Host smart-f5360aa7-9568-4e8a-bdc4-8851593cefad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249048700 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.1249048700
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.1744215636
Short name T682
Test name
Test status
Simulation time 10193956054 ps
CPU time 27.07 seconds
Started Jan 21 08:34:51 PM PST 24
Finished Jan 21 08:35:19 PM PST 24
Peak memory 405536 kb
Host smart-f607d68e-fff3-45b2-abb8-eb61a480bd48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744215636 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.1744215636
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.3393940853
Short name T571
Test name
Test status
Simulation time 940686900 ps
CPU time 2.53 seconds
Started Jan 21 08:34:59 PM PST 24
Finished Jan 21 08:35:02 PM PST 24
Peak memory 202620 kb
Host smart-80be75b0-7097-43c5-acc3-d3b429c57381
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393940853 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.3393940853
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.1312829545
Short name T1423
Test name
Test status
Simulation time 1744508751 ps
CPU time 7.6 seconds
Started Jan 21 08:34:39 PM PST 24
Finished Jan 21 08:34:47 PM PST 24
Peak memory 202532 kb
Host smart-10215b00-bfcb-4d8d-8120-5d2318e945d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312829545 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.1312829545
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.366969068
Short name T461
Test name
Test status
Simulation time 10019745790 ps
CPU time 216.06 seconds
Started Jan 21 08:34:41 PM PST 24
Finished Jan 21 08:38:18 PM PST 24
Peak memory 2259832 kb
Host smart-f0d79a4d-246e-4298-8fe5-0de4c48f1bf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366969068 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.366969068
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_perf.3469773639
Short name T1257
Test name
Test status
Simulation time 1073591908 ps
CPU time 3.59 seconds
Started Jan 21 08:34:57 PM PST 24
Finished Jan 21 08:35:01 PM PST 24
Peak memory 204392 kb
Host smart-98167294-5650-4d32-b20d-a5f7cbf70ad0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469773639 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_perf.3469773639
Directory /workspace/33.i2c_target_perf/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.866312452
Short name T1396
Test name
Test status
Simulation time 3990886553 ps
CPU time 11.65 seconds
Started Jan 21 08:34:43 PM PST 24
Finished Jan 21 08:34:56 PM PST 24
Peak memory 202620 kb
Host smart-50903f54-1380-4927-ad96-7f35955752b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866312452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_tar
get_smoke.866312452
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.1323710899
Short name T605
Test name
Test status
Simulation time 1241023870 ps
CPU time 23.58 seconds
Started Jan 21 08:57:53 PM PST 24
Finished Jan 21 08:58:41 PM PST 24
Peak memory 202560 kb
Host smart-ef128849-ba5d-43de-ab77-ac7385f85a04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323710899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.1323710899
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.2601471239
Short name T642
Test name
Test status
Simulation time 27628556260 ps
CPU time 124.64 seconds
Started Jan 21 08:34:37 PM PST 24
Finished Jan 21 08:36:42 PM PST 24
Peak memory 1616644 kb
Host smart-f1d0f41d-397c-4ffa-9de1-79fc5dab0186
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601471239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.2601471239
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.4028937275
Short name T407
Test name
Test status
Simulation time 17796263385 ps
CPU time 1148.12 seconds
Started Jan 21 08:34:39 PM PST 24
Finished Jan 21 08:53:48 PM PST 24
Peak memory 4194124 kb
Host smart-d1050fcf-a78d-4754-be6d-881e44580dd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028937275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.4028937275
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.1600804505
Short name T1218
Test name
Test status
Simulation time 6949895053 ps
CPU time 7.67 seconds
Started Jan 21 08:34:44 PM PST 24
Finished Jan 21 08:34:53 PM PST 24
Peak memory 202596 kb
Host smart-b4634779-4e2e-4d9e-a429-db15db22df7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600804505 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.1600804505
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_ovf.4050718466
Short name T561
Test name
Test status
Simulation time 12784120651 ps
CPU time 46.66 seconds
Started Jan 21 08:34:42 PM PST 24
Finished Jan 21 08:35:29 PM PST 24
Peak memory 230548 kb
Host smart-9b40b6af-b831-47ed-95c4-eddc128ef12e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050718466 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_tx_ovf.4050718466
Directory /workspace/33.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/33.i2c_target_unexp_stop.3421146300
Short name T534
Test name
Test status
Simulation time 1080012042 ps
CPU time 6.18 seconds
Started Jan 21 08:34:55 PM PST 24
Finished Jan 21 08:35:02 PM PST 24
Peak memory 202624 kb
Host smart-27813ed4-e668-4da4-abf2-963a07615c7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421146300 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.i2c_target_unexp_stop.3421146300
Directory /workspace/33.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/34.i2c_alert_test.1951210540
Short name T415
Test name
Test status
Simulation time 18666311 ps
CPU time 0.64 seconds
Started Jan 21 08:35:40 PM PST 24
Finished Jan 21 08:35:42 PM PST 24
Peak memory 201096 kb
Host smart-0070d8ad-64d0-47ae-a794-6c045ecefa34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951210540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.1951210540
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.3071388031
Short name T953
Test name
Test status
Simulation time 29339274 ps
CPU time 1.25 seconds
Started Jan 21 08:35:09 PM PST 24
Finished Jan 21 08:35:13 PM PST 24
Peak memory 210752 kb
Host smart-564da7ed-56e0-48f1-8131-1577b435aa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071388031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.3071388031
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.3229071122
Short name T276
Test name
Test status
Simulation time 297957124 ps
CPU time 6.38 seconds
Started Jan 21 09:12:16 PM PST 24
Finished Jan 21 09:12:28 PM PST 24
Peak memory 247416 kb
Host smart-80e91262-f380-42e8-8078-103e5fa6a91d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229071122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.3229071122
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.433524032
Short name T553
Test name
Test status
Simulation time 8024280375 ps
CPU time 97.51 seconds
Started Jan 21 08:35:06 PM PST 24
Finished Jan 21 08:36:45 PM PST 24
Peak memory 883676 kb
Host smart-051f5e23-c152-423e-ac73-1d136ed2ed82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433524032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.433524032
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.900008041
Short name T1353
Test name
Test status
Simulation time 32874891345 ps
CPU time 575.75 seconds
Started Jan 21 11:14:58 PM PST 24
Finished Jan 21 11:24:36 PM PST 24
Peak memory 1913184 kb
Host smart-b66f9541-e96e-4d12-a964-35c56f91bf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900008041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.900008041
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.6795956
Short name T286
Test name
Test status
Simulation time 279182555 ps
CPU time 0.77 seconds
Started Jan 21 08:35:08 PM PST 24
Finished Jan 21 08:35:10 PM PST 24
Peak memory 201464 kb
Host smart-e30bb404-a8c6-45eb-8193-c757f08e7306
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6795956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_fmt.6795956
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.2924329269
Short name T985
Test name
Test status
Simulation time 286413292 ps
CPU time 11.55 seconds
Started Jan 21 08:35:06 PM PST 24
Finished Jan 21 08:35:19 PM PST 24
Peak memory 237984 kb
Host smart-6286deb4-ad68-4d20-9ad1-be8a719d7056
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924329269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.2924329269
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.1312095227
Short name T916
Test name
Test status
Simulation time 16381735745 ps
CPU time 243.05 seconds
Started Jan 21 08:35:00 PM PST 24
Finished Jan 21 08:39:04 PM PST 24
Peak memory 1226896 kb
Host smart-66d9fc49-2a50-4fa2-83b7-f82c133c6466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312095227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.1312095227
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.678110103
Short name T658
Test name
Test status
Simulation time 11240247575 ps
CPU time 143.22 seconds
Started Jan 21 08:35:40 PM PST 24
Finished Jan 21 08:38:04 PM PST 24
Peak memory 245548 kb
Host smart-0e5571fc-6936-4c3c-9e51-b8bf068246b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678110103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.678110103
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.1962901455
Short name T748
Test name
Test status
Simulation time 19163477 ps
CPU time 0.64 seconds
Started Jan 21 08:35:02 PM PST 24
Finished Jan 21 08:35:03 PM PST 24
Peak memory 201432 kb
Host smart-eb145a82-3a1e-4867-811e-08799a37c2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962901455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.1962901455
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.1164626051
Short name T33
Test name
Test status
Simulation time 27291902644 ps
CPU time 691.12 seconds
Started Jan 21 08:57:12 PM PST 24
Finished Jan 21 09:09:14 PM PST 24
Peak memory 227000 kb
Host smart-ac6ed203-07c1-4281-b7b6-7c8e4d1c08e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164626051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.1164626051
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_rx_oversample.3184493873
Short name T213
Test name
Test status
Simulation time 4453746088 ps
CPU time 175.12 seconds
Started Jan 21 08:35:00 PM PST 24
Finished Jan 21 08:37:56 PM PST 24
Peak memory 264428 kb
Host smart-2799f5c0-6d7d-4449-b510-d529b8777be0
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184493873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_rx_oversample
.3184493873
Directory /workspace/34.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.93913508
Short name T867
Test name
Test status
Simulation time 1569849055 ps
CPU time 50.51 seconds
Started Jan 21 08:35:05 PM PST 24
Finished Jan 21 08:35:57 PM PST 24
Peak memory 275464 kb
Host smart-c3550b0e-ab9d-49bf-aa96-7bf8a8dc420f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93913508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.93913508
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.3579653916
Short name T1187
Test name
Test status
Simulation time 10405467526 ps
CPU time 1898.69 seconds
Started Jan 21 08:35:11 PM PST 24
Finished Jan 21 09:06:51 PM PST 24
Peak memory 1803252 kb
Host smart-3e8a73c4-c303-4a4e-b6cf-06d331a3c359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579653916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.3579653916
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.3485192235
Short name T982
Test name
Test status
Simulation time 9260915515 ps
CPU time 43.1 seconds
Started Jan 21 08:35:07 PM PST 24
Finished Jan 21 08:35:51 PM PST 24
Peak memory 210772 kb
Host smart-0d3208cb-ad22-4514-804c-f21886cdef45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485192235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.3485192235
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.89851154
Short name T1094
Test name
Test status
Simulation time 3938241648 ps
CPU time 4.07 seconds
Started Jan 21 08:35:28 PM PST 24
Finished Jan 21 08:35:33 PM PST 24
Peak memory 203384 kb
Host smart-62e0fa8e-8a72-4307-9b42-eda45ef0790b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89851154 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_bad_addr.89851154
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.2629698527
Short name T1470
Test name
Test status
Simulation time 10093702954 ps
CPU time 80.5 seconds
Started Jan 21 08:35:26 PM PST 24
Finished Jan 21 08:36:47 PM PST 24
Peak memory 502812 kb
Host smart-f23441e7-80be-495d-9e2b-50fd2a4b5fa4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629698527 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.2629698527
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.1112735796
Short name T969
Test name
Test status
Simulation time 10053739676 ps
CPU time 67.11 seconds
Started Jan 21 08:35:26 PM PST 24
Finished Jan 21 08:36:34 PM PST 24
Peak memory 553888 kb
Host smart-1599358f-99f3-4408-a5f8-9d5dcd6fe701
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112735796 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.1112735796
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.2347895767
Short name T608
Test name
Test status
Simulation time 680461230 ps
CPU time 3.25 seconds
Started Jan 21 08:35:28 PM PST 24
Finished Jan 21 08:35:32 PM PST 24
Peak memory 202600 kb
Host smart-9a56cf28-ccfe-4c47-924d-20efba4fd7b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347895767 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.2347895767
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.1647692711
Short name T837
Test name
Test status
Simulation time 1866990895 ps
CPU time 7.16 seconds
Started Jan 21 08:35:17 PM PST 24
Finished Jan 21 08:35:25 PM PST 24
Peak memory 202572 kb
Host smart-4f513c61-e1bf-47ff-8916-45867378dc2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647692711 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.1647692711
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_perf.3544691497
Short name T541
Test name
Test status
Simulation time 6988397029 ps
CPU time 4.4 seconds
Started Jan 21 08:35:25 PM PST 24
Finished Jan 21 08:35:31 PM PST 24
Peak memory 204080 kb
Host smart-b02f4575-7d0b-462c-93ab-49d475dafb92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544691497 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_perf.3544691497
Directory /workspace/34.i2c_target_perf/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.1144204622
Short name T288
Test name
Test status
Simulation time 669827542 ps
CPU time 18.66 seconds
Started Jan 21 08:35:10 PM PST 24
Finished Jan 21 08:35:30 PM PST 24
Peak memory 202580 kb
Host smart-4aa60358-799a-4284-ba54-91903cacf9e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144204622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.1144204622
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.4161215210
Short name T1425
Test name
Test status
Simulation time 1457198564 ps
CPU time 5.34 seconds
Started Jan 21 08:35:17 PM PST 24
Finished Jan 21 08:35:23 PM PST 24
Peak memory 202532 kb
Host smart-6cb7959a-9128-4d12-aa82-b4777725a2d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161215210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.4161215210
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.529450996
Short name T1251
Test name
Test status
Simulation time 17914029982 ps
CPU time 132.4 seconds
Started Jan 21 08:35:11 PM PST 24
Finished Jan 21 08:37:25 PM PST 24
Peak memory 1894888 kb
Host smart-5321080c-1aa9-40ad-8a26-68b6ebf7b03b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529450996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_wr.529450996
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.1461122960
Short name T1345
Test name
Test status
Simulation time 20904084927 ps
CPU time 574.31 seconds
Started Jan 21 11:13:07 PM PST 24
Finished Jan 21 11:22:43 PM PST 24
Peak memory 1572736 kb
Host smart-d61a99cb-2b3d-4ff6-a4b6-c0c277fc5cee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461122960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.1461122960
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.2000412816
Short name T793
Test name
Test status
Simulation time 4255338585 ps
CPU time 8.4 seconds
Started Jan 21 08:35:23 PM PST 24
Finished Jan 21 08:35:32 PM PST 24
Peak memory 204392 kb
Host smart-bb1aa695-575c-41a4-997a-6f1a0d0ded08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000412816 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.2000412816
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_ovf.2943780056
Short name T1274
Test name
Test status
Simulation time 2522543072 ps
CPU time 38.95 seconds
Started Jan 21 08:35:22 PM PST 24
Finished Jan 21 08:36:01 PM PST 24
Peak memory 252256 kb
Host smart-7a72e857-d6b7-42b0-b787-af43abb0d738
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943780056 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_tx_ovf.2943780056
Directory /workspace/34.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/34.i2c_target_unexp_stop.3475669112
Short name T465
Test name
Test status
Simulation time 1115471601 ps
CPU time 6.12 seconds
Started Jan 21 08:35:25 PM PST 24
Finished Jan 21 08:35:32 PM PST 24
Peak memory 202516 kb
Host smart-7e843ce5-8d0f-4f7d-abd6-2398a7c5662e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475669112 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.i2c_target_unexp_stop.3475669112
Directory /workspace/34.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/35.i2c_alert_test.2310714225
Short name T421
Test name
Test status
Simulation time 27437643 ps
CPU time 0.61 seconds
Started Jan 21 08:36:04 PM PST 24
Finished Jan 21 08:36:05 PM PST 24
Peak memory 201120 kb
Host smart-37a1eac6-9f8f-45dc-b175-1d1fd7b9cf45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310714225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.2310714225
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.1360623850
Short name T1483
Test name
Test status
Simulation time 31386692 ps
CPU time 1.36 seconds
Started Jan 21 09:01:32 PM PST 24
Finished Jan 21 09:01:52 PM PST 24
Peak memory 210712 kb
Host smart-24be987b-30da-4a00-8f3f-0e389cfd8eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360623850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.1360623850
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.386029580
Short name T480
Test name
Test status
Simulation time 945053429 ps
CPU time 13.08 seconds
Started Jan 21 08:35:54 PM PST 24
Finished Jan 21 08:36:09 PM PST 24
Peak memory 236784 kb
Host smart-0db79969-9934-4a44-907d-9479bf141cb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386029580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_empt
y.386029580
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.144110329
Short name T794
Test name
Test status
Simulation time 6791725189 ps
CPU time 38.87 seconds
Started Jan 21 09:10:52 PM PST 24
Finished Jan 21 09:11:47 PM PST 24
Peak memory 202552 kb
Host smart-a57088a3-5edd-4207-b28e-cb412b7a0787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144110329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.144110329
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.3358988500
Short name T10
Test name
Test status
Simulation time 7516340378 ps
CPU time 192.67 seconds
Started Jan 21 08:35:43 PM PST 24
Finished Jan 21 08:38:57 PM PST 24
Peak memory 1053336 kb
Host smart-b17f7f96-3dd0-4462-9565-fb797826c018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358988500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.3358988500
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.2694702187
Short name T1442
Test name
Test status
Simulation time 2903290217 ps
CPU time 1.04 seconds
Started Jan 21 08:35:47 PM PST 24
Finished Jan 21 08:35:48 PM PST 24
Peak memory 202484 kb
Host smart-7e3c8d90-0ff0-4323-bcbc-4c8f2ad2304b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694702187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.2694702187
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.3311764485
Short name T331
Test name
Test status
Simulation time 1632517987 ps
CPU time 9.49 seconds
Started Jan 21 08:35:52 PM PST 24
Finished Jan 21 08:36:03 PM PST 24
Peak memory 202448 kb
Host smart-31648e7c-208f-4006-8a09-9e9a1d767efc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311764485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.3311764485
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.2351326493
Short name T412
Test name
Test status
Simulation time 5402585496 ps
CPU time 593.34 seconds
Started Jan 21 08:35:49 PM PST 24
Finished Jan 21 08:45:44 PM PST 24
Peak memory 1533580 kb
Host smart-2fdde879-6cfe-42cc-ac53-f7bc230a15d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351326493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.2351326493
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.2113700719
Short name T36
Test name
Test status
Simulation time 7612896230 ps
CPU time 50.99 seconds
Started Jan 21 08:36:03 PM PST 24
Finished Jan 21 08:36:55 PM PST 24
Peak memory 292212 kb
Host smart-b9181055-74bd-4b0c-88e8-76ece3a69e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113700719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.2113700719
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.3647628453
Short name T1506
Test name
Test status
Simulation time 25832479 ps
CPU time 0.63 seconds
Started Jan 21 08:35:42 PM PST 24
Finished Jan 21 08:35:44 PM PST 24
Peak memory 201464 kb
Host smart-2eb626c0-7bda-4162-ba11-60e208f0d0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647628453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.3647628453
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.2292478752
Short name T943
Test name
Test status
Simulation time 29211130447 ps
CPU time 466.3 seconds
Started Jan 21 08:35:48 PM PST 24
Finished Jan 21 08:43:36 PM PST 24
Peak memory 218932 kb
Host smart-089bc8a2-e873-4b5e-975d-f94c4126a5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292478752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.2292478752
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_rx_oversample.1486220575
Short name T192
Test name
Test status
Simulation time 7630224975 ps
CPU time 76.64 seconds
Started Jan 21 08:35:42 PM PST 24
Finished Jan 21 08:36:59 PM PST 24
Peak memory 308400 kb
Host smart-813fc65d-75d9-4032-9c8d-6eb9827a1825
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486220575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_rx_oversample
.1486220575
Directory /workspace/35.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.382232079
Short name T1421
Test name
Test status
Simulation time 1934399568 ps
CPU time 66.12 seconds
Started Jan 21 08:35:42 PM PST 24
Finished Jan 21 08:36:49 PM PST 24
Peak memory 291724 kb
Host smart-4038d838-aba4-47a0-b3ea-74dff743c848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382232079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.382232079
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.3768186762
Short name T138
Test name
Test status
Simulation time 33839618062 ps
CPU time 1401.75 seconds
Started Jan 21 08:35:46 PM PST 24
Finished Jan 21 08:59:08 PM PST 24
Peak memory 2566352 kb
Host smart-90adcda2-8f7a-4b6f-889d-08d2cb1b7a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768186762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.3768186762
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.878114586
Short name T1035
Test name
Test status
Simulation time 3334929704 ps
CPU time 11.98 seconds
Started Jan 21 08:35:47 PM PST 24
Finished Jan 21 08:36:00 PM PST 24
Peak memory 214428 kb
Host smart-b293f43c-0c7a-4933-990f-cd37fa2c8158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878114586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.878114586
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.260986391
Short name T1071
Test name
Test status
Simulation time 3027244578 ps
CPU time 6.07 seconds
Started Jan 21 08:36:01 PM PST 24
Finished Jan 21 08:36:08 PM PST 24
Peak memory 202632 kb
Host smart-43a58795-4739-49bd-8feb-437a4310c3aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260986391 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.260986391
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.2129237597
Short name T723
Test name
Test status
Simulation time 10121777040 ps
CPU time 12.72 seconds
Started Jan 21 08:36:01 PM PST 24
Finished Jan 21 08:36:15 PM PST 24
Peak memory 269004 kb
Host smart-d831559e-2c08-4426-afe2-7ffc402a6434
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129237597 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.2129237597
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.1064664019
Short name T528
Test name
Test status
Simulation time 10277711127 ps
CPU time 12.99 seconds
Started Jan 21 08:35:59 PM PST 24
Finished Jan 21 08:36:12 PM PST 24
Peak memory 302940 kb
Host smart-95ab2409-e78d-4d6c-917c-71ca50be8e33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064664019 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.1064664019
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.234299194
Short name T992
Test name
Test status
Simulation time 1711045591 ps
CPU time 2.35 seconds
Started Jan 21 08:36:01 PM PST 24
Finished Jan 21 08:36:05 PM PST 24
Peak memory 202620 kb
Host smart-7194950e-7777-48da-90c7-7ef2906b3b24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234299194 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.i2c_target_hrst.234299194
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.3574717144
Short name T692
Test name
Test status
Simulation time 1597384470 ps
CPU time 6.87 seconds
Started Jan 21 08:35:55 PM PST 24
Finished Jan 21 08:36:03 PM PST 24
Peak memory 211888 kb
Host smart-08b2a8a4-0656-4b86-8db9-fa078ca7100a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574717144 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.3574717144
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.2785886985
Short name T1006
Test name
Test status
Simulation time 16725124847 ps
CPU time 643.3 seconds
Started Jan 21 08:35:54 PM PST 24
Finished Jan 21 08:46:38 PM PST 24
Peak memory 3771468 kb
Host smart-6a8ad932-fb8b-470f-98bf-40583da4a76c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785886985 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.2785886985
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_perf.688188542
Short name T680
Test name
Test status
Simulation time 720171637 ps
CPU time 2.5 seconds
Started Jan 21 08:59:24 PM PST 24
Finished Jan 21 08:59:49 PM PST 24
Peak memory 202440 kb
Host smart-b758b3c9-ec08-4c86-ad9b-e5b97e13f1f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688188542 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.i2c_target_perf.688188542
Directory /workspace/35.i2c_target_perf/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.1465956870
Short name T1255
Test name
Test status
Simulation time 4080911174 ps
CPU time 27.95 seconds
Started Jan 21 08:35:46 PM PST 24
Finished Jan 21 08:36:14 PM PST 24
Peak memory 202628 kb
Host smart-e5db6b4e-b632-4f1d-af50-cf2add00e6d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465956870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.1465956870
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.2778154499
Short name T995
Test name
Test status
Simulation time 2086860072 ps
CPU time 43.77 seconds
Started Jan 21 08:35:54 PM PST 24
Finished Jan 21 08:36:39 PM PST 24
Peak memory 202568 kb
Host smart-e4cf53d5-8478-4b33-8b13-0543ebaae74a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778154499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.2778154499
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.1099362988
Short name T440
Test name
Test status
Simulation time 37132048712 ps
CPU time 1939.2 seconds
Started Jan 21 08:35:46 PM PST 24
Finished Jan 21 09:08:07 PM PST 24
Peak memory 8174240 kb
Host smart-f4554f7d-8e1a-4b61-84f0-3f42c81c89d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099362988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.1099362988
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.234686109
Short name T900
Test name
Test status
Simulation time 22828022255 ps
CPU time 621.33 seconds
Started Jan 21 08:35:52 PM PST 24
Finished Jan 21 08:46:14 PM PST 24
Peak memory 2735056 kb
Host smart-c4ca2cbb-8c5f-43a5-8180-21d70dc59c3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234686109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_t
arget_stretch.234686109
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.2446028372
Short name T678
Test name
Test status
Simulation time 3915696667 ps
CPU time 7.69 seconds
Started Jan 21 08:35:56 PM PST 24
Finished Jan 21 08:36:04 PM PST 24
Peak memory 202580 kb
Host smart-a389c27e-3430-424f-8010-8938e8fcbbfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446028372 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.2446028372
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_tx_ovf.4127486385
Short name T817
Test name
Test status
Simulation time 5641600323 ps
CPU time 66.69 seconds
Started Jan 21 08:35:54 PM PST 24
Finished Jan 21 08:37:01 PM PST 24
Peak memory 283948 kb
Host smart-6894197d-7ae3-40b1-aa01-bdc9f8cf57f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127486385 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_tx_ovf.4127486385
Directory /workspace/35.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/35.i2c_target_unexp_stop.575867242
Short name T881
Test name
Test status
Simulation time 5755743732 ps
CPU time 6.33 seconds
Started Jan 21 08:35:52 PM PST 24
Finished Jan 21 08:36:00 PM PST 24
Peak memory 211024 kb
Host smart-bc20154c-6174-499f-83f5-984261f5fc1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575867242 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_unexp_stop.575867242
Directory /workspace/35.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/36.i2c_alert_test.3922592720
Short name T406
Test name
Test status
Simulation time 16837422 ps
CPU time 0.63 seconds
Started Jan 21 08:36:45 PM PST 24
Finished Jan 21 08:36:46 PM PST 24
Peak memory 202048 kb
Host smart-080e76fe-2ed2-423b-b3f2-01dfdae49149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922592720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.3922592720
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.281501723
Short name T479
Test name
Test status
Simulation time 31007393 ps
CPU time 1.13 seconds
Started Jan 21 08:36:21 PM PST 24
Finished Jan 21 08:36:26 PM PST 24
Peak memory 210692 kb
Host smart-d7ad6be3-6e2c-4ff1-8bba-ca501cb88e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281501723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.281501723
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.2312366945
Short name T392
Test name
Test status
Simulation time 654125415 ps
CPU time 7.55 seconds
Started Jan 21 08:36:19 PM PST 24
Finished Jan 21 08:36:28 PM PST 24
Peak memory 270212 kb
Host smart-33b2d84c-b678-44bc-8acc-69a34c7a06c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312366945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.2312366945
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.1722646480
Short name T110
Test name
Test status
Simulation time 8251017530 ps
CPU time 230.23 seconds
Started Jan 21 10:09:34 PM PST 24
Finished Jan 21 10:13:25 PM PST 24
Peak memory 1213088 kb
Host smart-b049894f-92cf-4363-800b-ff6c59c197f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722646480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.1722646480
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.3846128329
Short name T779
Test name
Test status
Simulation time 26992241062 ps
CPU time 1099.74 seconds
Started Jan 21 08:36:10 PM PST 24
Finished Jan 21 08:54:30 PM PST 24
Peak memory 1849088 kb
Host smart-36763f51-47de-4093-a46e-11412da25fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846128329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.3846128329
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.2539917275
Short name T408
Test name
Test status
Simulation time 1501230842 ps
CPU time 0.94 seconds
Started Jan 21 08:36:20 PM PST 24
Finished Jan 21 08:36:22 PM PST 24
Peak memory 202300 kb
Host smart-e1db0bf2-b87e-45a5-b2d7-3bed6112e7b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539917275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.2539917275
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.3176580471
Short name T952
Test name
Test status
Simulation time 810935881 ps
CPU time 4.29 seconds
Started Jan 21 08:36:19 PM PST 24
Finished Jan 21 08:36:25 PM PST 24
Peak memory 202540 kb
Host smart-7705dcc2-771e-4012-8a60-3d55bd23ead8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176580471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.3176580471
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.3495929722
Short name T1496
Test name
Test status
Simulation time 4928417383 ps
CPU time 270.14 seconds
Started Jan 21 08:36:10 PM PST 24
Finished Jan 21 08:40:41 PM PST 24
Peak memory 1327720 kb
Host smart-518098e4-0196-4e57-9a47-398b444d1bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495929722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.3495929722
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.1087285125
Short name T1280
Test name
Test status
Simulation time 14516558406 ps
CPU time 46.41 seconds
Started Jan 21 08:36:45 PM PST 24
Finished Jan 21 08:37:33 PM PST 24
Peak memory 311944 kb
Host smart-9a01829b-7ff2-4435-9400-e2100fcd8515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087285125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.1087285125
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.2325289904
Short name T338
Test name
Test status
Simulation time 19063408 ps
CPU time 0.65 seconds
Started Jan 21 08:36:04 PM PST 24
Finished Jan 21 08:36:05 PM PST 24
Peak memory 201484 kb
Host smart-6e57a328-5c67-492c-93df-a9008c96eead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325289904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.2325289904
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.857261246
Short name T1380
Test name
Test status
Simulation time 29598250491 ps
CPU time 192.4 seconds
Started Jan 21 08:36:19 PM PST 24
Finished Jan 21 08:39:33 PM PST 24
Peak memory 326156 kb
Host smart-413ce3f0-1df2-4588-bf3a-9c157075b3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857261246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.857261246
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_rx_oversample.210798650
Short name T879
Test name
Test status
Simulation time 2234197774 ps
CPU time 102.8 seconds
Started Jan 21 08:36:05 PM PST 24
Finished Jan 21 08:37:49 PM PST 24
Peak memory 310660 kb
Host smart-e2a6ae58-9975-4ebb-ac49-8803ddcdd211
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210798650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_rx_oversample.
210798650
Directory /workspace/36.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.44969559
Short name T970
Test name
Test status
Simulation time 2099155492 ps
CPU time 122.8 seconds
Started Jan 21 09:08:27 PM PST 24
Finished Jan 21 09:10:51 PM PST 24
Peak memory 243360 kb
Host smart-fb1ecbb5-1a7e-4cec-9dfd-3bf23ccf07e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44969559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.44969559
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.3476230834
Short name T1336
Test name
Test status
Simulation time 649944912 ps
CPU time 29.19 seconds
Started Jan 21 08:36:22 PM PST 24
Finished Jan 21 08:36:55 PM PST 24
Peak memory 210708 kb
Host smart-48ce08f3-4f77-4f2e-ab5f-7c9f06accae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476230834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.3476230834
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.1284919486
Short name T1414
Test name
Test status
Simulation time 911043887 ps
CPU time 3.55 seconds
Started Jan 21 08:36:45 PM PST 24
Finished Jan 21 08:36:50 PM PST 24
Peak memory 202592 kb
Host smart-734af6d7-818d-4a8b-9f3e-0c7ab8a3a33c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284919486 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.1284919486
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.709405490
Short name T324
Test name
Test status
Simulation time 10959431843 ps
CPU time 3.26 seconds
Started Jan 21 08:36:42 PM PST 24
Finished Jan 21 08:36:46 PM PST 24
Peak memory 211036 kb
Host smart-aed06aab-63e2-4a63-a45b-d719582a1777
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709405490 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_acq.709405490
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.170430933
Short name T321
Test name
Test status
Simulation time 10076545575 ps
CPU time 76.65 seconds
Started Jan 21 09:02:40 PM PST 24
Finished Jan 21 09:04:03 PM PST 24
Peak memory 607412 kb
Host smart-efb333bd-a7cd-4324-bec6-e1e16cd2936e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170430933 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_fifo_reset_tx.170430933
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.3008356283
Short name T1408
Test name
Test status
Simulation time 976537882 ps
CPU time 2.64 seconds
Started Jan 21 08:36:45 PM PST 24
Finished Jan 21 08:36:49 PM PST 24
Peak memory 202600 kb
Host smart-21758bf5-ad6b-4e80-acdf-64234bd0e312
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008356283 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.3008356283
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.307901474
Short name T523
Test name
Test status
Simulation time 1578478863 ps
CPU time 6.81 seconds
Started Jan 21 09:47:37 PM PST 24
Finished Jan 21 09:47:44 PM PST 24
Peak memory 211180 kb
Host smart-a8908045-97f0-4046-929d-58dcd47d9768
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307901474 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_intr_smoke.307901474
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.1931468227
Short name T208
Test name
Test status
Simulation time 16150980487 ps
CPU time 10.74 seconds
Started Jan 21 08:36:29 PM PST 24
Finished Jan 21 08:36:42 PM PST 24
Peak memory 316680 kb
Host smart-edeaf164-71b3-45e4-8691-94d2a134aaff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931468227 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.1931468227
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_perf.1476594168
Short name T865
Test name
Test status
Simulation time 3159975813 ps
CPU time 4.85 seconds
Started Jan 21 08:36:44 PM PST 24
Finished Jan 21 08:36:49 PM PST 24
Peak memory 205120 kb
Host smart-82afef97-b26d-4002-b27c-05188bbd4529
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476594168 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_perf.1476594168
Directory /workspace/36.i2c_target_perf/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.2057658684
Short name T1383
Test name
Test status
Simulation time 5500396986 ps
CPU time 34.49 seconds
Started Jan 21 08:36:22 PM PST 24
Finished Jan 21 08:37:00 PM PST 24
Peak memory 202596 kb
Host smart-f49c4dbf-13dd-4f13-bc6a-96b3659316f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057658684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.2057658684
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_all.2191765171
Short name T1331
Test name
Test status
Simulation time 25391027882 ps
CPU time 1123.33 seconds
Started Jan 21 08:36:44 PM PST 24
Finished Jan 21 08:55:29 PM PST 24
Peak memory 1620160 kb
Host smart-2c72d1ba-48ae-4857-9288-5cec92e76cbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191765171 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_stress_all.2191765171
Directory /workspace/36.i2c_target_stress_all/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.2366461063
Short name T1509
Test name
Test status
Simulation time 4618110723 ps
CPU time 15.83 seconds
Started Jan 21 08:36:33 PM PST 24
Finished Jan 21 08:36:52 PM PST 24
Peak memory 209624 kb
Host smart-3700eaea-ad19-4989-93de-5381b598919b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366461063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.2366461063
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.854173357
Short name T317
Test name
Test status
Simulation time 15095871167 ps
CPU time 70.55 seconds
Started Jan 21 09:10:00 PM PST 24
Finished Jan 21 09:11:31 PM PST 24
Peak memory 1219472 kb
Host smart-bc329624-6446-4a27-a77b-c905d04fdc7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854173357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_wr.854173357
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.757804323
Short name T222
Test name
Test status
Simulation time 35297224245 ps
CPU time 1507.23 seconds
Started Jan 21 08:36:31 PM PST 24
Finished Jan 21 09:01:40 PM PST 24
Peak memory 4429976 kb
Host smart-3baf9a04-117b-4d5a-a1ec-873fac873f68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757804323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_t
arget_stretch.757804323
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.2996701923
Short name T337
Test name
Test status
Simulation time 3582397084 ps
CPU time 7.35 seconds
Started Jan 21 08:36:32 PM PST 24
Finished Jan 21 08:36:42 PM PST 24
Peak memory 211104 kb
Host smart-b4a3c76a-a132-4eb7-8bd9-7ceeca907916
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996701923 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.2996701923
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_ovf.1615608685
Short name T868
Test name
Test status
Simulation time 9272122750 ps
CPU time 37.66 seconds
Started Jan 21 08:36:29 PM PST 24
Finished Jan 21 08:37:09 PM PST 24
Peak memory 217796 kb
Host smart-a0fe8d4b-ddc9-4eb2-9043-b1bb0727fd3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615608685 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_tx_ovf.1615608685
Directory /workspace/36.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/36.i2c_target_unexp_stop.758653421
Short name T964
Test name
Test status
Simulation time 2046048129 ps
CPU time 5.28 seconds
Started Jan 21 10:07:13 PM PST 24
Finished Jan 21 10:07:24 PM PST 24
Peak memory 202576 kb
Host smart-9618d20d-0734-4701-902f-e339ade4536d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758653421 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_unexp_stop.758653421
Directory /workspace/36.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/37.i2c_alert_test.2106020286
Short name T1066
Test name
Test status
Simulation time 16708644 ps
CPU time 0.62 seconds
Started Jan 21 08:37:17 PM PST 24
Finished Jan 21 08:37:18 PM PST 24
Peak memory 201088 kb
Host smart-071ce228-7aef-4fd8-8dfc-efa554727121
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106020286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2106020286
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.462754014
Short name T765
Test name
Test status
Simulation time 152573784 ps
CPU time 1.91 seconds
Started Jan 21 08:36:57 PM PST 24
Finished Jan 21 08:37:05 PM PST 24
Peak memory 210728 kb
Host smart-3c262a6b-d84b-41ce-a2d4-ef4c45aeda88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462754014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.462754014
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.3097383770
Short name T799
Test name
Test status
Simulation time 5013909659 ps
CPU time 10.91 seconds
Started Jan 21 08:37:03 PM PST 24
Finished Jan 21 08:37:17 PM PST 24
Peak memory 306604 kb
Host smart-fe26ddf3-cc7f-4101-be19-83e2694235cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097383770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.3097383770
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.4136355247
Short name T1013
Test name
Test status
Simulation time 3510943240 ps
CPU time 131.61 seconds
Started Jan 21 08:36:55 PM PST 24
Finished Jan 21 08:39:08 PM PST 24
Peak memory 639296 kb
Host smart-6219d83b-7ed0-448f-976a-d1fcb4e66f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136355247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.4136355247
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.294236696
Short name T178
Test name
Test status
Simulation time 5873853403 ps
CPU time 821.75 seconds
Started Jan 21 08:36:59 PM PST 24
Finished Jan 21 08:50:45 PM PST 24
Peak memory 1636944 kb
Host smart-feee45aa-32af-447b-98dc-68d49d20680d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294236696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.294236696
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.2405024321
Short name T368
Test name
Test status
Simulation time 75667465 ps
CPU time 0.85 seconds
Started Jan 21 08:36:59 PM PST 24
Finished Jan 21 08:37:04 PM PST 24
Peak memory 202324 kb
Host smart-004610c5-1608-478c-a9cf-f878e8aae304
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405024321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.2405024321
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.1022977249
Short name T1170
Test name
Test status
Simulation time 915461052 ps
CPU time 12.36 seconds
Started Jan 21 08:37:03 PM PST 24
Finished Jan 21 08:37:18 PM PST 24
Peak memory 202504 kb
Host smart-69a5a854-9bdf-403a-b8d3-70d9e25ce396
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022977249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.1022977249
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.1416349235
Short name T940
Test name
Test status
Simulation time 26073091893 ps
CPU time 460.68 seconds
Started Jan 21 08:36:55 PM PST 24
Finished Jan 21 08:44:38 PM PST 24
Peak memory 1796820 kb
Host smart-4a604ee0-397f-4646-844f-a57c27cc6e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416349235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1416349235
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.909986246
Short name T743
Test name
Test status
Simulation time 10089792415 ps
CPU time 128.94 seconds
Started Jan 21 08:37:07 PM PST 24
Finished Jan 21 08:39:17 PM PST 24
Peak memory 248928 kb
Host smart-c29641a3-5ffb-4b16-b07e-14d8e08b805a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909986246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.909986246
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.3773010308
Short name T1224
Test name
Test status
Simulation time 57569968 ps
CPU time 0.63 seconds
Started Jan 21 08:36:45 PM PST 24
Finished Jan 21 08:36:47 PM PST 24
Peak memory 201432 kb
Host smart-44f529e7-2fb2-4c1b-a839-96c66e184208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773010308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.3773010308
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.1079033489
Short name T726
Test name
Test status
Simulation time 58858387597 ps
CPU time 127.22 seconds
Started Jan 21 08:36:59 PM PST 24
Finished Jan 21 08:39:10 PM PST 24
Peak memory 364868 kb
Host smart-eddf8bd7-075c-4635-83b3-63a964699ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079033489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.1079033489
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_rx_oversample.1110187285
Short name T1101
Test name
Test status
Simulation time 2747516325 ps
CPU time 58.01 seconds
Started Jan 21 08:36:56 PM PST 24
Finished Jan 21 08:38:00 PM PST 24
Peak memory 277380 kb
Host smart-a203ac97-0a93-442e-bdfe-c4455349d20e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110187285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_rx_oversample
.1110187285
Directory /workspace/37.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.1083897998
Short name T1397
Test name
Test status
Simulation time 2366792492 ps
CPU time 59.44 seconds
Started Jan 21 08:36:44 PM PST 24
Finished Jan 21 08:37:44 PM PST 24
Peak memory 261716 kb
Host smart-c0dda16a-98a7-40ec-8f31-7ab79d79260b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083897998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.1083897998
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.3074548753
Short name T705
Test name
Test status
Simulation time 1350028272 ps
CPU time 12.47 seconds
Started Jan 21 08:37:02 PM PST 24
Finished Jan 21 08:37:16 PM PST 24
Peak memory 218924 kb
Host smart-ece97334-883a-44d8-a63c-72d11931a532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074548753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.3074548753
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.2275129433
Short name T41
Test name
Test status
Simulation time 1862335534 ps
CPU time 3.81 seconds
Started Jan 21 08:37:08 PM PST 24
Finished Jan 21 08:37:12 PM PST 24
Peak memory 202576 kb
Host smart-4135450b-da3a-4680-a277-d1fc32b99a02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275129433 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.2275129433
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.1224681228
Short name T319
Test name
Test status
Simulation time 10028625558 ps
CPU time 67.21 seconds
Started Jan 21 08:37:10 PM PST 24
Finished Jan 21 08:38:18 PM PST 24
Peak memory 492628 kb
Host smart-34e3cd67-1b9c-4967-a73a-f9fb68b9b3c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224681228 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.1224681228
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.720765187
Short name T909
Test name
Test status
Simulation time 10035272223 ps
CPU time 75.04 seconds
Started Jan 21 08:37:10 PM PST 24
Finished Jan 21 08:38:26 PM PST 24
Peak memory 499328 kb
Host smart-3f4213db-4839-4b91-b184-e208e2c06d0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720765187 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_fifo_reset_tx.720765187
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.520920713
Short name T444
Test name
Test status
Simulation time 566578142 ps
CPU time 2.56 seconds
Started Jan 21 09:07:33 PM PST 24
Finished Jan 21 09:07:46 PM PST 24
Peak memory 202644 kb
Host smart-7ade8a38-ae5b-49df-b502-731a9bd2f19d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520920713 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.i2c_target_hrst.520920713
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.4228876969
Short name T335
Test name
Test status
Simulation time 1794362946 ps
CPU time 7.97 seconds
Started Jan 21 09:06:55 PM PST 24
Finished Jan 21 09:07:19 PM PST 24
Peak memory 205336 kb
Host smart-057cf751-98d6-4724-916c-d46bd5abdac7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228876969 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.4228876969
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.14117258
Short name T500
Test name
Test status
Simulation time 27537747332 ps
CPU time 887.83 seconds
Started Jan 21 09:16:57 PM PST 24
Finished Jan 21 09:31:46 PM PST 24
Peak memory 5807304 kb
Host smart-14419711-6e64-4c1a-bdd4-825d15491481
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14117258 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.14117258
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_perf.1443066745
Short name T355
Test name
Test status
Simulation time 1090368488 ps
CPU time 3.38 seconds
Started Jan 21 08:37:08 PM PST 24
Finished Jan 21 08:37:12 PM PST 24
Peak memory 202532 kb
Host smart-821ad697-5531-48d3-875d-c791397a798a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443066745 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_perf.1443066745
Directory /workspace/37.i2c_target_perf/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.3024663234
Short name T583
Test name
Test status
Simulation time 15507751785 ps
CPU time 39.46 seconds
Started Jan 21 08:37:02 PM PST 24
Finished Jan 21 08:37:43 PM PST 24
Peak memory 202656 kb
Host smart-45ddcf5b-4e83-4422-878e-f5ca058f475e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024663234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.3024663234
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_all.2656099138
Short name T1182
Test name
Test status
Simulation time 20759977878 ps
CPU time 1585.31 seconds
Started Jan 21 08:37:09 PM PST 24
Finished Jan 21 09:03:36 PM PST 24
Peak memory 2672628 kb
Host smart-ac23427b-26d5-4b74-822c-37b1a9c5d4f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656099138 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.i2c_target_stress_all.2656099138
Directory /workspace/37.i2c_target_stress_all/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.78963298
Short name T984
Test name
Test status
Simulation time 2814471985 ps
CPU time 28.44 seconds
Started Jan 21 08:37:00 PM PST 24
Finished Jan 21 08:37:32 PM PST 24
Peak memory 202640 kb
Host smart-926f2a3e-8104-4c0e-820f-2c71081597a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78963298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stress_rd.78963298
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.3272493324
Short name T1242
Test name
Test status
Simulation time 31247343793 ps
CPU time 1101.16 seconds
Started Jan 21 08:36:55 PM PST 24
Finished Jan 21 08:55:18 PM PST 24
Peak memory 6701808 kb
Host smart-1ff323eb-594d-4899-a3f2-3a265bf133fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272493324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.3272493324
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.1403329538
Short name T399
Test name
Test status
Simulation time 40698785590 ps
CPU time 841.74 seconds
Started Jan 21 08:37:01 PM PST 24
Finished Jan 21 08:51:05 PM PST 24
Peak memory 2991604 kb
Host smart-ab64725b-70b7-460b-9d51-c88074215533
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403329538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.1403329538
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.2225405726
Short name T555
Test name
Test status
Simulation time 3290094431 ps
CPU time 7.61 seconds
Started Jan 21 10:14:11 PM PST 24
Finished Jan 21 10:14:23 PM PST 24
Peak memory 207476 kb
Host smart-243a667b-7d51-45dd-9a1c-7f9a516c68a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225405726 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.2225405726
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_tx_ovf.1368515747
Short name T1407
Test name
Test status
Simulation time 2738235126 ps
CPU time 142.7 seconds
Started Jan 21 08:37:04 PM PST 24
Finished Jan 21 08:39:29 PM PST 24
Peak memory 430440 kb
Host smart-13b6ad11-b1cd-4f38-827d-8dca6ad850b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368515747 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_tx_ovf.1368515747
Directory /workspace/37.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/37.i2c_target_unexp_stop.1645756882
Short name T1448
Test name
Test status
Simulation time 2893723473 ps
CPU time 6.91 seconds
Started Jan 21 08:37:08 PM PST 24
Finished Jan 21 08:37:16 PM PST 24
Peak memory 206692 kb
Host smart-1b030acf-887a-45b5-9ab7-37c18a8328b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645756882 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.i2c_target_unexp_stop.1645756882
Directory /workspace/37.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/38.i2c_alert_test.4142056850
Short name T531
Test name
Test status
Simulation time 53169250 ps
CPU time 0.61 seconds
Started Jan 21 08:37:48 PM PST 24
Finished Jan 21 08:37:51 PM PST 24
Peak memory 201140 kb
Host smart-6b5a59ef-b8b2-41cf-90d5-d3caba598251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142056850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.4142056850
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.3708121757
Short name T385
Test name
Test status
Simulation time 43995656 ps
CPU time 1.25 seconds
Started Jan 21 08:37:35 PM PST 24
Finished Jan 21 08:37:37 PM PST 24
Peak memory 210716 kb
Host smart-53fe1636-9d77-43cf-a449-0d7705c2c313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708121757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.3708121757
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.4276560748
Short name T1240
Test name
Test status
Simulation time 470204677 ps
CPU time 8.31 seconds
Started Jan 21 08:37:24 PM PST 24
Finished Jan 21 08:37:33 PM PST 24
Peak memory 291512 kb
Host smart-002ca38f-3ef7-45f7-bd55-1c24e5cbe39b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276560748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.4276560748
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.3078700647
Short name T878
Test name
Test status
Simulation time 3874464220 ps
CPU time 67.85 seconds
Started Jan 21 08:37:26 PM PST 24
Finished Jan 21 08:38:35 PM PST 24
Peak memory 685700 kb
Host smart-53e6550e-aa91-4d8e-8c42-f96a6e6a42ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078700647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.3078700647
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.777222477
Short name T1239
Test name
Test status
Simulation time 11129426374 ps
CPU time 830.27 seconds
Started Jan 21 08:37:26 PM PST 24
Finished Jan 21 08:51:16 PM PST 24
Peak memory 1554940 kb
Host smart-2537b9e8-ddd6-45cb-a1d2-371e3431c407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777222477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.777222477
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.1337050140
Short name T1323
Test name
Test status
Simulation time 120137068 ps
CPU time 0.92 seconds
Started Jan 21 08:37:25 PM PST 24
Finished Jan 21 08:37:27 PM PST 24
Peak memory 202300 kb
Host smart-82e1fe38-214a-4c8d-a6ce-02e6b4c0a705
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337050140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.1337050140
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.3582722481
Short name T1214
Test name
Test status
Simulation time 334594058 ps
CPU time 4.55 seconds
Started Jan 21 08:37:25 PM PST 24
Finished Jan 21 08:37:30 PM PST 24
Peak memory 232936 kb
Host smart-0e9cf38d-be99-4ae6-b29f-6e54046e3dd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582722481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.3582722481
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.4071122347
Short name T1175
Test name
Test status
Simulation time 6630235102 ps
CPU time 434.24 seconds
Started Jan 21 08:37:24 PM PST 24
Finished Jan 21 08:44:39 PM PST 24
Peak memory 1259740 kb
Host smart-a72cbe7b-f62c-4022-9d84-08004e04bd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071122347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.4071122347
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.422065961
Short name T834
Test name
Test status
Simulation time 1949629976 ps
CPU time 58.9 seconds
Started Jan 21 08:37:50 PM PST 24
Finished Jan 21 08:38:50 PM PST 24
Peak memory 288272 kb
Host smart-64282897-b33c-4670-a53d-be3c2a67bda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422065961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.422065961
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.2227792482
Short name T830
Test name
Test status
Simulation time 16034125 ps
CPU time 0.65 seconds
Started Jan 21 08:37:18 PM PST 24
Finished Jan 21 08:37:20 PM PST 24
Peak memory 201516 kb
Host smart-a78590c0-eb41-4a59-ad70-afc72f72f55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227792482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.2227792482
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.1350670672
Short name T447
Test name
Test status
Simulation time 1867765430 ps
CPU time 3.7 seconds
Started Jan 21 08:37:26 PM PST 24
Finished Jan 21 08:37:30 PM PST 24
Peak memory 215580 kb
Host smart-1d10c6cd-d533-4ea4-abd2-d0f088fe9383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350670672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.1350670672
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_rx_oversample.1675279
Short name T1133
Test name
Test status
Simulation time 15767780335 ps
CPU time 164.23 seconds
Started Jan 21 08:37:27 PM PST 24
Finished Jan 21 08:40:12 PM PST 24
Peak memory 327556 kb
Host smart-20e9c88a-2cbb-4b97-8f01-d7aaa4ea4166
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_rx_oversample.1675279
Directory /workspace/38.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.1345666390
Short name T305
Test name
Test status
Simulation time 2858908559 ps
CPU time 99.38 seconds
Started Jan 21 08:37:21 PM PST 24
Finished Jan 21 08:39:01 PM PST 24
Peak memory 345004 kb
Host smart-82689860-376c-402f-b5b7-c8ce10154286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345666390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.1345666390
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.1923091348
Short name T636
Test name
Test status
Simulation time 44624496934 ps
CPU time 165.33 seconds
Started Jan 21 08:37:35 PM PST 24
Finished Jan 21 08:40:20 PM PST 24
Peak memory 242724 kb
Host smart-3ca9c84f-72ce-4f80-8d38-48a2b3e08b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923091348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.1923091348
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.3477171380
Short name T1090
Test name
Test status
Simulation time 910527333 ps
CPU time 7.45 seconds
Started Jan 21 08:37:38 PM PST 24
Finished Jan 21 08:37:46 PM PST 24
Peak memory 218692 kb
Host smart-9b8463de-a6ba-40f2-87c8-a8ee06a66daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477171380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.3477171380
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.1570710541
Short name T559
Test name
Test status
Simulation time 802814034 ps
CPU time 3.69 seconds
Started Jan 21 08:58:46 PM PST 24
Finished Jan 21 08:59:17 PM PST 24
Peak memory 202576 kb
Host smart-57e2e1e2-0aea-41b0-a9a9-6b2f7a3e76c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570710541 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.1570710541
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.4034039710
Short name T1220
Test name
Test status
Simulation time 10132525460 ps
CPU time 8.38 seconds
Started Jan 21 09:12:13 PM PST 24
Finished Jan 21 09:12:24 PM PST 24
Peak memory 247092 kb
Host smart-a7ddeffd-56da-4dbd-a8ce-4dea62967f8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034039710 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.4034039710
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.2490845495
Short name T1205
Test name
Test status
Simulation time 10415190376 ps
CPU time 12.48 seconds
Started Jan 21 08:37:44 PM PST 24
Finished Jan 21 08:37:57 PM PST 24
Peak memory 307412 kb
Host smart-447a3b71-fa9e-4e86-9de2-f42f5f8119b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490845495 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.2490845495
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.1514940907
Short name T152
Test name
Test status
Simulation time 2103111124 ps
CPU time 2.64 seconds
Started Jan 21 08:37:50 PM PST 24
Finished Jan 21 08:37:54 PM PST 24
Peak memory 202600 kb
Host smart-79f18063-c33e-485c-b455-eb4c39738089
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514940907 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.1514940907
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.2785866889
Short name T1114
Test name
Test status
Simulation time 5584400952 ps
CPU time 4.62 seconds
Started Jan 21 08:37:45 PM PST 24
Finished Jan 21 08:37:50 PM PST 24
Peak memory 202688 kb
Host smart-976cc7c8-d027-4958-ae9f-cf1ab8aab3ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785866889 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.2785866889
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.1126360425
Short name T322
Test name
Test status
Simulation time 4123814296 ps
CPU time 2.36 seconds
Started Jan 21 08:37:36 PM PST 24
Finished Jan 21 08:37:40 PM PST 24
Peak memory 202620 kb
Host smart-ea3b0bfb-1101-4dc3-833c-79f2f96b788d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126360425 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.1126360425
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_perf.2299948985
Short name T1324
Test name
Test status
Simulation time 899411966 ps
CPU time 5.64 seconds
Started Jan 21 08:51:39 PM PST 24
Finished Jan 21 08:52:25 PM PST 24
Peak memory 206812 kb
Host smart-0de78dc5-a9f0-499b-8a98-6915ce83fda7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299948985 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_perf.2299948985
Directory /workspace/38.i2c_target_perf/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.4051538715
Short name T1477
Test name
Test status
Simulation time 3880286024 ps
CPU time 12.24 seconds
Started Jan 21 08:37:36 PM PST 24
Finished Jan 21 08:37:49 PM PST 24
Peak memory 202576 kb
Host smart-6acd1ebe-aeac-4050-9542-3f8e6d480e10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051538715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.4051538715
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_all.141250656
Short name T16
Test name
Test status
Simulation time 78992342696 ps
CPU time 742.35 seconds
Started Jan 21 08:37:42 PM PST 24
Finished Jan 21 08:50:05 PM PST 24
Peak memory 1696336 kb
Host smart-53fa86a1-3315-49ff-9bb8-a3a0a8946a40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141250656 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.i2c_target_stress_all.141250656
Directory /workspace/38.i2c_target_stress_all/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.1852146953
Short name T1
Test name
Test status
Simulation time 6920385508 ps
CPU time 30.93 seconds
Started Jan 21 08:37:37 PM PST 24
Finished Jan 21 08:38:08 PM PST 24
Peak memory 220448 kb
Host smart-6d66d397-235f-4983-9fa1-c99a4ae3d347
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852146953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.1852146953
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.3366303217
Short name T622
Test name
Test status
Simulation time 39090460360 ps
CPU time 2216.62 seconds
Started Jan 21 08:37:35 PM PST 24
Finished Jan 21 09:14:33 PM PST 24
Peak memory 8777860 kb
Host smart-9b884584-8a5c-40b1-893e-94a31cf9ea27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366303217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.3366303217
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.1232403311
Short name T648
Test name
Test status
Simulation time 22925249545 ps
CPU time 463.3 seconds
Started Jan 21 08:37:34 PM PST 24
Finished Jan 21 08:45:18 PM PST 24
Peak memory 1481964 kb
Host smart-73f7fa29-ee57-498d-987a-771f0443acf7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232403311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.1232403311
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.3700505744
Short name T902
Test name
Test status
Simulation time 4427381095 ps
CPU time 8.63 seconds
Started Jan 21 08:37:37 PM PST 24
Finished Jan 21 08:37:46 PM PST 24
Peak memory 202624 kb
Host smart-9f21f3d5-4ea0-42d0-8f35-2d05560b813e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700505744 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.3700505744
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_tx_ovf.1506545293
Short name T929
Test name
Test status
Simulation time 22362666943 ps
CPU time 160.06 seconds
Started Jan 21 08:37:35 PM PST 24
Finished Jan 21 08:40:16 PM PST 24
Peak memory 405744 kb
Host smart-e309ceda-9752-4cac-89ad-2a1c6d3732e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506545293 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_tx_ovf.1506545293
Directory /workspace/38.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/38.i2c_target_unexp_stop.2800112833
Short name T1375
Test name
Test status
Simulation time 1209162955 ps
CPU time 5.4 seconds
Started Jan 21 08:37:46 PM PST 24
Finished Jan 21 08:37:52 PM PST 24
Peak memory 202596 kb
Host smart-0a5be92d-306c-41ce-bc92-0714194e6c48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800112833 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.i2c_target_unexp_stop.2800112833
Directory /workspace/38.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/39.i2c_alert_test.1655088915
Short name T227
Test name
Test status
Simulation time 21254579 ps
CPU time 0.62 seconds
Started Jan 21 08:38:28 PM PST 24
Finished Jan 21 08:38:29 PM PST 24
Peak memory 201132 kb
Host smart-c6242989-907c-4c10-97ea-8b685adf784b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655088915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1655088915
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.4280951127
Short name T896
Test name
Test status
Simulation time 138259389 ps
CPU time 1.25 seconds
Started Jan 21 08:38:11 PM PST 24
Finished Jan 21 08:38:13 PM PST 24
Peak memory 210728 kb
Host smart-7bb09e41-cb5c-4658-8e1a-1dfc9a168bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280951127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.4280951127
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.2888658032
Short name T1321
Test name
Test status
Simulation time 1089767647 ps
CPU time 27.92 seconds
Started Jan 21 08:37:57 PM PST 24
Finished Jan 21 08:38:26 PM PST 24
Peak memory 319736 kb
Host smart-15a55526-0595-4083-9fde-1966e1e98223
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888658032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.2888658032
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.3261923142
Short name T446
Test name
Test status
Simulation time 6274290829 ps
CPU time 148.36 seconds
Started Jan 21 09:06:01 PM PST 24
Finished Jan 21 09:09:04 PM PST 24
Peak memory 970412 kb
Host smart-14c89870-a2d5-43bd-af9b-85f2d8cdffe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261923142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.3261923142
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.1232151343
Short name T789
Test name
Test status
Simulation time 18680899912 ps
CPU time 191.92 seconds
Started Jan 21 09:16:33 PM PST 24
Finished Jan 21 09:19:47 PM PST 24
Peak memory 1192616 kb
Host smart-521e07b1-d5ff-4f19-a5a7-5f3278d84c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232151343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.1232151343
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.3369834959
Short name T652
Test name
Test status
Simulation time 431491181 ps
CPU time 1.01 seconds
Started Jan 21 08:37:57 PM PST 24
Finished Jan 21 08:37:58 PM PST 24
Peak memory 202340 kb
Host smart-32530bb6-0a24-4fbf-a714-641a611e961e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369834959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.3369834959
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.1919843248
Short name T1155
Test name
Test status
Simulation time 470700006 ps
CPU time 12.06 seconds
Started Jan 21 08:37:56 PM PST 24
Finished Jan 21 08:38:08 PM PST 24
Peak memory 202500 kb
Host smart-cfd73f6c-0e7c-4e03-953f-6c9e978c0528
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919843248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.1919843248
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.3179214160
Short name T72
Test name
Test status
Simulation time 3586969865 ps
CPU time 145.8 seconds
Started Jan 21 08:54:26 PM PST 24
Finished Jan 21 08:56:59 PM PST 24
Peak memory 1050856 kb
Host smart-4cac9e17-a18a-4e7f-99e4-45d193398a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179214160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.3179214160
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.3811631700
Short name T1366
Test name
Test status
Simulation time 2655179016 ps
CPU time 136.05 seconds
Started Jan 21 08:38:29 PM PST 24
Finished Jan 21 08:40:46 PM PST 24
Peak memory 232196 kb
Host smart-81050f02-ccb3-4e0a-95f4-5ce03726e52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811631700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.3811631700
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.1092519702
Short name T651
Test name
Test status
Simulation time 38734361 ps
CPU time 0.63 seconds
Started Jan 21 08:37:49 PM PST 24
Finished Jan 21 08:37:51 PM PST 24
Peak memory 201516 kb
Host smart-197b3e78-6b89-43c4-a131-bf7536c891c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092519702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.1092519702
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.2229248965
Short name T1102
Test name
Test status
Simulation time 52191705460 ps
CPU time 833.58 seconds
Started Jan 21 08:37:56 PM PST 24
Finished Jan 21 08:51:50 PM PST 24
Peak memory 226976 kb
Host smart-9a489388-60c8-4717-8472-afd4201e0979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229248965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.2229248965
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_rx_oversample.3894775980
Short name T767
Test name
Test status
Simulation time 11267662061 ps
CPU time 319.67 seconds
Started Jan 21 08:37:56 PM PST 24
Finished Jan 21 08:43:17 PM PST 24
Peak memory 431956 kb
Host smart-0c13aba6-2143-4bb9-ab95-42726402c90e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894775980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_rx_oversample
.3894775980
Directory /workspace/39.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.504440372
Short name T1526
Test name
Test status
Simulation time 7906110348 ps
CPU time 45.46 seconds
Started Jan 21 08:37:49 PM PST 24
Finished Jan 21 08:38:36 PM PST 24
Peak memory 277064 kb
Host smart-0d9ccd34-86e7-40c3-919f-324a88b51093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504440372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.504440372
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.1014700097
Short name T1235
Test name
Test status
Simulation time 50428593493 ps
CPU time 2180.33 seconds
Started Jan 21 08:38:10 PM PST 24
Finished Jan 21 09:14:31 PM PST 24
Peak memory 2482556 kb
Host smart-12dcaf0a-f6dc-48be-b46b-1f5cf75e4fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014700097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.1014700097
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.2908896400
Short name T526
Test name
Test status
Simulation time 8748456549 ps
CPU time 15.29 seconds
Started Jan 21 08:37:57 PM PST 24
Finished Jan 21 08:38:13 PM PST 24
Peak memory 218920 kb
Host smart-b6844e8b-dc2a-4e82-856a-08c479bb382a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908896400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.2908896400
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.746550883
Short name T1465
Test name
Test status
Simulation time 2589332031 ps
CPU time 2.92 seconds
Started Jan 21 08:38:21 PM PST 24
Finished Jan 21 08:38:25 PM PST 24
Peak memory 202616 kb
Host smart-ccd13770-2a11-45ee-9be6-17c32b933879
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746550883 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.746550883
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.50647459
Short name T270
Test name
Test status
Simulation time 10107168478 ps
CPU time 57.44 seconds
Started Jan 21 08:38:16 PM PST 24
Finished Jan 21 08:39:14 PM PST 24
Peak memory 541096 kb
Host smart-99c3a3b1-e7db-41dc-9c06-77d4ed16f037
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50647459 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_fifo_reset_acq.50647459
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.2700165001
Short name T745
Test name
Test status
Simulation time 10030736198 ps
CPU time 65.29 seconds
Started Jan 21 08:38:26 PM PST 24
Finished Jan 21 08:39:32 PM PST 24
Peak memory 588796 kb
Host smart-e4686a2f-49cf-4d95-809a-3c603f15e917
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700165001 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.2700165001
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.1626692446
Short name T220
Test name
Test status
Simulation time 539183213 ps
CPU time 2.67 seconds
Started Jan 21 08:38:20 PM PST 24
Finished Jan 21 08:38:24 PM PST 24
Peak memory 202644 kb
Host smart-e2f49929-5004-405d-8b2c-6929492d2382
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626692446 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.1626692446
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.964324281
Short name T1503
Test name
Test status
Simulation time 11840124100 ps
CPU time 5.53 seconds
Started Jan 21 08:38:09 PM PST 24
Finished Jan 21 08:38:15 PM PST 24
Peak memory 206840 kb
Host smart-d29278e0-4b7e-4ac5-b6a5-9b37995558c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964324281 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_intr_smoke.964324281
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.1611411619
Short name T890
Test name
Test status
Simulation time 20657150972 ps
CPU time 111.17 seconds
Started Jan 21 08:38:19 PM PST 24
Finished Jan 21 08:40:11 PM PST 24
Peak memory 1120776 kb
Host smart-949f79bd-1188-419d-99ef-e4f1ceeda134
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611411619 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.1611411619
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_perf.1081392650
Short name T967
Test name
Test status
Simulation time 3707775514 ps
CPU time 4.05 seconds
Started Jan 21 08:38:26 PM PST 24
Finished Jan 21 08:38:30 PM PST 24
Peak memory 202532 kb
Host smart-201dd895-bf1b-427e-9a21-530e4319e5df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081392650 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_perf.1081392650
Directory /workspace/39.i2c_target_perf/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.296318819
Short name T963
Test name
Test status
Simulation time 1346650852 ps
CPU time 16.69 seconds
Started Jan 21 09:21:46 PM PST 24
Finished Jan 21 09:22:08 PM PST 24
Peak memory 202624 kb
Host smart-bb527306-fb3d-474a-ae04-f98dfea5b531
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296318819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_tar
get_smoke.296318819
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_all.3787154917
Short name T171
Test name
Test status
Simulation time 25615917897 ps
CPU time 124.63 seconds
Started Jan 21 08:38:20 PM PST 24
Finished Jan 21 08:40:26 PM PST 24
Peak memory 248080 kb
Host smart-4c8eed2a-dfed-415d-8c4f-139fe95a4e6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787154917 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_target_stress_all.3787154917
Directory /workspace/39.i2c_target_stress_all/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.2374250201
Short name T540
Test name
Test status
Simulation time 1419896642 ps
CPU time 11.15 seconds
Started Jan 21 10:34:56 PM PST 24
Finished Jan 21 10:35:09 PM PST 24
Peak memory 209144 kb
Host smart-ff8e547b-d432-49dd-a6b9-5c1aba06c14a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374250201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.2374250201
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.2952694195
Short name T386
Test name
Test status
Simulation time 16248764200 ps
CPU time 95.83 seconds
Started Jan 21 08:38:08 PM PST 24
Finished Jan 21 08:39:44 PM PST 24
Peak memory 1597432 kb
Host smart-9d1df84f-6b72-4954-b453-7d765b5ccdca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952694195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.2952694195
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.3212245050
Short name T474
Test name
Test status
Simulation time 40255965443 ps
CPU time 359.7 seconds
Started Jan 21 08:38:09 PM PST 24
Finished Jan 21 08:44:10 PM PST 24
Peak memory 2237876 kb
Host smart-a5414a7a-b7b1-49ad-ae52-f885840966b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212245050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.3212245050
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.2875984316
Short name T293
Test name
Test status
Simulation time 1929346481 ps
CPU time 7.76 seconds
Started Jan 21 08:38:17 PM PST 24
Finished Jan 21 08:38:25 PM PST 24
Peak memory 212568 kb
Host smart-a3323fa9-1647-49f9-974f-c6ea700457cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875984316 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.2875984316
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_ovf.3573362913
Short name T806
Test name
Test status
Simulation time 16823163387 ps
CPU time 383 seconds
Started Jan 21 08:38:16 PM PST 24
Finished Jan 21 08:44:40 PM PST 24
Peak memory 578704 kb
Host smart-b8388697-0543-45ff-9a31-5df52e5e60b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573362913 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_tx_ovf.3573362913
Directory /workspace/39.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/39.i2c_target_unexp_stop.1226639384
Short name T1500
Test name
Test status
Simulation time 19952607804 ps
CPU time 6.03 seconds
Started Jan 21 08:38:16 PM PST 24
Finished Jan 21 08:38:23 PM PST 24
Peak memory 209716 kb
Host smart-521a7d55-2868-41fd-ae0f-2d02581ff866
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226639384 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.i2c_target_unexp_stop.1226639384
Directory /workspace/39.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/4.i2c_alert_test.811312465
Short name T693
Test name
Test status
Simulation time 20157342 ps
CPU time 0.62 seconds
Started Jan 21 08:20:23 PM PST 24
Finished Jan 21 08:20:26 PM PST 24
Peak memory 201104 kb
Host smart-5f15be20-1c8f-4848-b66a-98151e6b7b97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811312465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.811312465
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.2534616968
Short name T1388
Test name
Test status
Simulation time 76793029 ps
CPU time 1.27 seconds
Started Jan 21 08:19:52 PM PST 24
Finished Jan 21 08:19:54 PM PST 24
Peak memory 210720 kb
Host smart-5875ed07-2553-429c-ac2f-71ca7f6980c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534616968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.2534616968
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.307690436
Short name T1399
Test name
Test status
Simulation time 1680729392 ps
CPU time 6.92 seconds
Started Jan 21 08:38:27 PM PST 24
Finished Jan 21 08:38:35 PM PST 24
Peak memory 283052 kb
Host smart-b844e750-4064-4fcf-b7b6-2356619c7703
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307690436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty
.307690436
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.2912349031
Short name T263
Test name
Test status
Simulation time 10966451797 ps
CPU time 107.75 seconds
Started Jan 21 08:19:52 PM PST 24
Finished Jan 21 08:21:41 PM PST 24
Peak memory 635580 kb
Host smart-ab85bdad-a7e9-4f4f-a98a-57c77b81b7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912349031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.2912349031
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.3181529983
Short name T856
Test name
Test status
Simulation time 5940343489 ps
CPU time 411.7 seconds
Started Jan 21 08:58:34 PM PST 24
Finished Jan 21 09:05:56 PM PST 24
Peak memory 1686156 kb
Host smart-0a8c3aa4-07f7-413a-87af-ebfda4f9a349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181529983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.3181529983
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.1292590002
Short name T637
Test name
Test status
Simulation time 241301956 ps
CPU time 1.1 seconds
Started Jan 21 08:19:51 PM PST 24
Finished Jan 21 08:19:54 PM PST 24
Peak memory 202276 kb
Host smart-9bbd42a2-8bcd-4245-8da8-395e27a4727a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292590002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.1292590002
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.2652225994
Short name T853
Test name
Test status
Simulation time 147086385 ps
CPU time 8.62 seconds
Started Jan 21 08:19:53 PM PST 24
Finished Jan 21 08:20:04 PM PST 24
Peak memory 227236 kb
Host smart-bfc981a9-4f1a-4f00-9ef0-92a1d09ff3b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652225994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
2652225994
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.1965372486
Short name T457
Test name
Test status
Simulation time 6822224062 ps
CPU time 473.72 seconds
Started Jan 21 08:19:56 PM PST 24
Finished Jan 21 08:27:51 PM PST 24
Peak memory 1852116 kb
Host smart-e450c80d-4878-4122-9592-f4befd7085fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965372486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.1965372486
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.3257592305
Short name T1393
Test name
Test status
Simulation time 3306948861 ps
CPU time 48.41 seconds
Started Jan 21 08:20:11 PM PST 24
Finished Jan 21 08:21:02 PM PST 24
Peak memory 292132 kb
Host smart-131ff347-7658-4254-9e83-2425a629f716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257592305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.3257592305
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.1634538269
Short name T452
Test name
Test status
Simulation time 123297099 ps
CPU time 0.63 seconds
Started Jan 21 09:09:13 PM PST 24
Finished Jan 21 09:09:21 PM PST 24
Peak memory 201504 kb
Host smart-c491fbce-d593-4ff3-9751-0eade0885b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634538269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.1634538269
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.2633786944
Short name T148
Test name
Test status
Simulation time 2120345119 ps
CPU time 5.5 seconds
Started Jan 21 08:19:53 PM PST 24
Finished Jan 21 08:20:00 PM PST 24
Peak memory 232444 kb
Host smart-cbf64cda-d5f3-4988-8648-c64ac2704634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633786944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.2633786944
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_rx_oversample.2954911927
Short name T925
Test name
Test status
Simulation time 8583715668 ps
CPU time 94.37 seconds
Started Jan 21 08:19:58 PM PST 24
Finished Jan 21 08:21:34 PM PST 24
Peak memory 325148 kb
Host smart-cf1684ee-7bba-4062-b16b-9cd2555f8e42
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954911927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_rx_oversample.
2954911927
Directory /workspace/4.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.664170036
Short name T704
Test name
Test status
Simulation time 3121435754 ps
CPU time 47.94 seconds
Started Jan 21 08:39:47 PM PST 24
Finished Jan 21 08:40:36 PM PST 24
Peak memory 293204 kb
Host smart-583bacfb-51cd-4ff1-85f0-47c47ab20116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664170036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.664170036
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.3557209776
Short name T933
Test name
Test status
Simulation time 35676821459 ps
CPU time 3184.02 seconds
Started Jan 21 08:19:55 PM PST 24
Finished Jan 21 09:13:01 PM PST 24
Peak memory 2435740 kb
Host smart-411ad387-dae0-4f46-9cb9-3c404bb5ccd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557209776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.3557209776
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.320033854
Short name T584
Test name
Test status
Simulation time 1975909893 ps
CPU time 47.52 seconds
Started Jan 21 08:19:53 PM PST 24
Finished Jan 21 08:20:43 PM PST 24
Peak memory 210656 kb
Host smart-935180b6-7751-42ef-846a-c1da4de4455a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320033854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.320033854
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.741680876
Short name T82
Test name
Test status
Simulation time 244350171 ps
CPU time 1 seconds
Started Jan 21 08:20:11 PM PST 24
Finished Jan 21 08:20:15 PM PST 24
Peak memory 219444 kb
Host smart-584ab0bb-8ff4-4a32-a85a-600b005c11bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741680876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.741680876
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.1747181377
Short name T218
Test name
Test status
Simulation time 606269314 ps
CPU time 2.13 seconds
Started Jan 21 09:17:42 PM PST 24
Finished Jan 21 09:17:48 PM PST 24
Peak memory 202544 kb
Host smart-6a8e85e0-b306-49c8-9bc2-10cfca7052b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747181377 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.1747181377
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.839978851
Short name T602
Test name
Test status
Simulation time 10046141147 ps
CPU time 52.93 seconds
Started Jan 21 08:51:00 PM PST 24
Finished Jan 21 08:52:30 PM PST 24
Peak memory 463308 kb
Host smart-1f3fb493-4875-4fd3-b48e-bff63171b1d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839978851 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_acq.839978851
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.2148585468
Short name T659
Test name
Test status
Simulation time 10037487961 ps
CPU time 28.7 seconds
Started Jan 21 08:20:03 PM PST 24
Finished Jan 21 08:20:35 PM PST 24
Peak memory 404108 kb
Host smart-06310e8c-b56b-486e-aba5-e24c208ae8c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148585468 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.2148585468
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.727857442
Short name T1173
Test name
Test status
Simulation time 4499019430 ps
CPU time 2.22 seconds
Started Jan 21 08:20:11 PM PST 24
Finished Jan 21 08:20:16 PM PST 24
Peak memory 202692 kb
Host smart-9b21139f-54e5-4fbf-8b0e-9002e6b80965
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727857442 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.i2c_target_hrst.727857442
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.661675081
Short name T753
Test name
Test status
Simulation time 2485052657 ps
CPU time 4.17 seconds
Started Jan 21 08:20:03 PM PST 24
Finished Jan 21 08:20:11 PM PST 24
Peak memory 202628 kb
Host smart-6bb50640-fddd-457e-b6fb-3826fb19a6df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661675081 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_intr_smoke.661675081
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.693176695
Short name T1210
Test name
Test status
Simulation time 5921863986 ps
CPU time 64.95 seconds
Started Jan 21 08:20:03 PM PST 24
Finished Jan 21 08:21:12 PM PST 24
Peak memory 1208844 kb
Host smart-8178a4d2-9100-4b20-8b85-c86c01ea039d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693176695 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.693176695
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_perf.2863348289
Short name T615
Test name
Test status
Simulation time 690674950 ps
CPU time 3.99 seconds
Started Jan 21 08:20:09 PM PST 24
Finished Jan 21 08:20:17 PM PST 24
Peak memory 202588 kb
Host smart-7b3d975f-4679-4fe8-b817-eebb64e4c9ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863348289 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_perf.2863348289
Directory /workspace/4.i2c_target_perf/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.1073169283
Short name T516
Test name
Test status
Simulation time 997784455 ps
CPU time 10.41 seconds
Started Jan 21 08:20:03 PM PST 24
Finished Jan 21 08:20:18 PM PST 24
Peak memory 201960 kb
Host smart-73558bca-8ea6-4753-b0ed-d70f4fdbfb4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073169283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.1073169283
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_all.2635723247
Short name T1077
Test name
Test status
Simulation time 169252861045 ps
CPU time 589.89 seconds
Started Jan 21 08:47:39 PM PST 24
Finished Jan 21 08:57:55 PM PST 24
Peak memory 1825160 kb
Host smart-5421ac60-68d7-411b-bd86-486e3a564074
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635723247 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_target_stress_all.2635723247
Directory /workspace/4.i2c_target_stress_all/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.3900762292
Short name T1222
Test name
Test status
Simulation time 2772261190 ps
CPU time 8.42 seconds
Started Jan 21 08:20:02 PM PST 24
Finished Jan 21 08:20:14 PM PST 24
Peak memory 202744 kb
Host smart-b028fbd3-37c6-4a12-b75b-185c42bce470
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900762292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.3900762292
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.2941179492
Short name T997
Test name
Test status
Simulation time 37256463114 ps
CPU time 212.16 seconds
Started Jan 21 08:20:02 PM PST 24
Finished Jan 21 08:23:36 PM PST 24
Peak memory 1385320 kb
Host smart-a6c8214f-c02f-4b50-97b3-3aeebf2472ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941179492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.2941179492
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.608197059
Short name T532
Test name
Test status
Simulation time 6351037220 ps
CPU time 6.87 seconds
Started Jan 21 08:20:02 PM PST 24
Finished Jan 21 08:20:11 PM PST 24
Peak memory 202604 kb
Host smart-64f3b87b-e301-4e2d-9737-d68ab340ae84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608197059 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_timeout.608197059
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_ovf.1041061329
Short name T725
Test name
Test status
Simulation time 3854439624 ps
CPU time 156.55 seconds
Started Jan 21 08:20:03 PM PST 24
Finished Jan 21 08:22:43 PM PST 24
Peak memory 408020 kb
Host smart-be41c20c-064e-42f6-8df7-abae6491d64d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041061329 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_tx_ovf.1041061329
Directory /workspace/4.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/4.i2c_target_unexp_stop.529197563
Short name T1201
Test name
Test status
Simulation time 3446256724 ps
CPU time 8.81 seconds
Started Jan 21 08:20:03 PM PST 24
Finished Jan 21 08:20:16 PM PST 24
Peak memory 202648 kb
Host smart-f9091733-13e5-457e-9278-d01455492e5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529197563 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_unexp_stop.529197563
Directory /workspace/4.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/40.i2c_alert_test.3584138926
Short name T906
Test name
Test status
Simulation time 34638306 ps
CPU time 0.63 seconds
Started Jan 21 08:39:11 PM PST 24
Finished Jan 21 08:39:14 PM PST 24
Peak memory 201128 kb
Host smart-5c8a1f2a-40a0-4fb2-a535-bbc92da80ee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584138926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.3584138926
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.2182602070
Short name T609
Test name
Test status
Simulation time 33126522 ps
CPU time 1.57 seconds
Started Jan 21 08:38:37 PM PST 24
Finished Jan 21 08:38:39 PM PST 24
Peak memory 212340 kb
Host smart-ea3b4c0b-0291-43ba-adae-293b6ccff1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182602070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.2182602070
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.275891242
Short name T369
Test name
Test status
Simulation time 213797206 ps
CPU time 4.88 seconds
Started Jan 21 08:51:28 PM PST 24
Finished Jan 21 08:52:17 PM PST 24
Peak memory 242684 kb
Host smart-f0b151b1-d96c-4c06-b0d2-512e521bf06a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275891242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empt
y.275891242
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.2023967077
Short name T801
Test name
Test status
Simulation time 4037031680 ps
CPU time 111.98 seconds
Started Jan 21 08:38:40 PM PST 24
Finished Jan 21 08:40:32 PM PST 24
Peak memory 407656 kb
Host smart-6675a6c4-efc5-4393-8a31-f8b7f96eb59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023967077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.2023967077
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.539057819
Short name T188
Test name
Test status
Simulation time 5873320523 ps
CPU time 410.54 seconds
Started Jan 21 08:38:38 PM PST 24
Finished Jan 21 08:45:29 PM PST 24
Peak memory 1699228 kb
Host smart-bae47a6e-ce53-4901-b381-3ac52f202138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539057819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.539057819
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.486314687
Short name T389
Test name
Test status
Simulation time 133919261 ps
CPU time 0.87 seconds
Started Jan 21 08:38:38 PM PST 24
Finished Jan 21 08:38:39 PM PST 24
Peak memory 202392 kb
Host smart-a2378680-a2b5-40ff-8e00-afcb236000ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486314687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fm
t.486314687
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.2062674301
Short name T1273
Test name
Test status
Simulation time 378832471 ps
CPU time 6.11 seconds
Started Jan 21 08:38:37 PM PST 24
Finished Jan 21 08:38:43 PM PST 24
Peak memory 237508 kb
Host smart-f8472cf2-a831-4053-8a50-e651f344d609
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062674301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.2062674301
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.602186378
Short name T505
Test name
Test status
Simulation time 6938239571 ps
CPU time 475.19 seconds
Started Jan 21 08:54:24 PM PST 24
Finished Jan 21 09:02:27 PM PST 24
Peak memory 1810200 kb
Host smart-51cd1a7f-0e0f-49cc-949e-9a04a2a06c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602186378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.602186378
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.3040522286
Short name T780
Test name
Test status
Simulation time 2616240025 ps
CPU time 72.46 seconds
Started Jan 21 08:39:08 PM PST 24
Finished Jan 21 08:40:22 PM PST 24
Peak memory 302712 kb
Host smart-fc10a553-3c2f-442e-9d95-9a8f0d3bd2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040522286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.3040522286
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.1110091414
Short name T603
Test name
Test status
Simulation time 21994929 ps
CPU time 0.64 seconds
Started Jan 21 08:38:33 PM PST 24
Finished Jan 21 08:38:35 PM PST 24
Peak memory 201444 kb
Host smart-9cb2f679-8e33-474e-b07d-d5cd45c06191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110091414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.1110091414
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.3999147263
Short name T1110
Test name
Test status
Simulation time 54117383927 ps
CPU time 198.63 seconds
Started Jan 21 08:38:36 PM PST 24
Finished Jan 21 08:41:55 PM PST 24
Peak memory 212244 kb
Host smart-708fcb21-e4a1-4882-b835-21ab5f2ac2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999147263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.3999147263
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_rx_oversample.1154740857
Short name T1195
Test name
Test status
Simulation time 1755745309 ps
CPU time 175.05 seconds
Started Jan 21 08:38:36 PM PST 24
Finished Jan 21 08:41:32 PM PST 24
Peak memory 297304 kb
Host smart-27cca463-69f9-4f02-b4eb-e92ff6cadc22
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154740857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_rx_oversample
.1154740857
Directory /workspace/40.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.2371645781
Short name T1304
Test name
Test status
Simulation time 2003506023 ps
CPU time 64.16 seconds
Started Jan 21 08:38:29 PM PST 24
Finished Jan 21 08:39:33 PM PST 24
Peak memory 311480 kb
Host smart-2c9cc217-9dd7-40d5-82c3-f9be57df20e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371645781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.2371645781
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.2690950892
Short name T894
Test name
Test status
Simulation time 671728288 ps
CPU time 12.14 seconds
Started Jan 21 08:38:38 PM PST 24
Finished Jan 21 08:38:50 PM PST 24
Peak memory 210700 kb
Host smart-3a7bc285-57ec-44d1-ae2e-e591cbbf1ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690950892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.2690950892
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.3698526914
Short name T1269
Test name
Test status
Simulation time 809349397 ps
CPU time 3.74 seconds
Started Jan 21 08:39:03 PM PST 24
Finished Jan 21 08:39:08 PM PST 24
Peak memory 202520 kb
Host smart-3d150f2b-ed02-44be-bf7c-8f09c5504db4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698526914 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.3698526914
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.347325734
Short name T922
Test name
Test status
Simulation time 10040252756 ps
CPU time 54.03 seconds
Started Jan 21 08:38:56 PM PST 24
Finished Jan 21 08:39:51 PM PST 24
Peak memory 475828 kb
Host smart-9b0a99bb-9dd9-4506-b49e-f573a8a391a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347325734 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_acq.347325734
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.4212986112
Short name T662
Test name
Test status
Simulation time 10083648804 ps
CPU time 68.05 seconds
Started Jan 21 08:38:56 PM PST 24
Finished Jan 21 08:40:05 PM PST 24
Peak memory 559136 kb
Host smart-825c2168-7a23-4929-82ed-459d890fc96f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212986112 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.4212986112
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.2963539810
Short name T1410
Test name
Test status
Simulation time 699429365 ps
CPU time 2.83 seconds
Started Jan 21 08:39:03 PM PST 24
Finished Jan 21 08:39:07 PM PST 24
Peak memory 202580 kb
Host smart-5ada484f-6e0f-4444-8c2d-2b1353104608
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963539810 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.2963539810
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.3760782309
Short name T951
Test name
Test status
Simulation time 753409898 ps
CPU time 3.71 seconds
Started Jan 21 08:38:46 PM PST 24
Finished Jan 21 08:38:55 PM PST 24
Peak memory 202612 kb
Host smart-5c304b7a-5756-49dc-aac8-95abecf699a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760782309 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.3760782309
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.282487014
Short name T818
Test name
Test status
Simulation time 19762941588 ps
CPU time 517.26 seconds
Started Jan 21 08:38:47 PM PST 24
Finished Jan 21 08:47:30 PM PST 24
Peak memory 3025884 kb
Host smart-471453e4-36fc-45ef-876d-2c8e831c0ec2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282487014 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.282487014
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_perf.17515700
Short name T106
Test name
Test status
Simulation time 400589604 ps
CPU time 2.6 seconds
Started Jan 21 08:38:56 PM PST 24
Finished Jan 21 08:39:00 PM PST 24
Peak memory 202548 kb
Host smart-6871fcfd-2e0c-49d8-91f9-8d585afd0714
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17515700 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.i2c_target_perf.17515700
Directory /workspace/40.i2c_target_perf/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.24193042
Short name T496
Test name
Test status
Simulation time 1310609420 ps
CPU time 16.69 seconds
Started Jan 21 08:38:44 PM PST 24
Finished Jan 21 08:39:02 PM PST 24
Peak memory 202540 kb
Host smart-cabdeb14-7d1a-4010-a34b-4fe0215a317c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24193042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_targ
et_smoke.24193042
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_all.1242614110
Short name T864
Test name
Test status
Simulation time 27227551469 ps
CPU time 205.88 seconds
Started Jan 21 08:38:56 PM PST 24
Finished Jan 21 08:42:23 PM PST 24
Peak memory 1128356 kb
Host smart-a6a47630-a8c1-4684-8c38-2942d362a593
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242614110 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.i2c_target_stress_all.1242614110
Directory /workspace/40.i2c_target_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.1221714091
Short name T1190
Test name
Test status
Simulation time 4235954081 ps
CPU time 44.12 seconds
Started Jan 21 08:38:47 PM PST 24
Finished Jan 21 08:39:37 PM PST 24
Peak memory 202608 kb
Host smart-59081da1-6bc8-4fae-92b9-8a452e480be6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221714091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.1221714091
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.3371630551
Short name T58
Test name
Test status
Simulation time 64658046649 ps
CPU time 286.15 seconds
Started Jan 21 08:38:45 PM PST 24
Finished Jan 21 08:43:32 PM PST 24
Peak memory 2444716 kb
Host smart-ec5870fa-23cf-4f7b-a587-cdb44f30413e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371630551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.3371630551
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.3263625480
Short name T1430
Test name
Test status
Simulation time 23273256639 ps
CPU time 531.99 seconds
Started Jan 21 08:38:46 PM PST 24
Finished Jan 21 08:47:38 PM PST 24
Peak memory 2417164 kb
Host smart-d3621605-ad9c-4384-8c84-6046aa66861e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263625480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.3263625480
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.3170600867
Short name T604
Test name
Test status
Simulation time 8196306915 ps
CPU time 6.48 seconds
Started Jan 21 08:38:57 PM PST 24
Finished Jan 21 08:39:04 PM PST 24
Peak memory 208012 kb
Host smart-fca5e834-fe96-42fe-8d49-80cdb6b2950f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170600867 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.3170600867
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_ovf.1760212247
Short name T1504
Test name
Test status
Simulation time 14469933307 ps
CPU time 154.94 seconds
Started Jan 21 08:38:57 PM PST 24
Finished Jan 21 08:41:33 PM PST 24
Peak memory 423356 kb
Host smart-a2e9c09c-de11-4c15-a7da-9edf929f0df0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760212247 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_tx_ovf.1760212247
Directory /workspace/40.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/40.i2c_target_unexp_stop.1143430567
Short name T1085
Test name
Test status
Simulation time 924427296 ps
CPU time 6.74 seconds
Started Jan 21 08:38:59 PM PST 24
Finished Jan 21 08:39:07 PM PST 24
Peak memory 202552 kb
Host smart-4a5e321b-1ef0-49cf-b334-8374c56f036a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143430567 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.i2c_target_unexp_stop.1143430567
Directory /workspace/40.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/41.i2c_alert_test.3262930049
Short name T552
Test name
Test status
Simulation time 38387948 ps
CPU time 0.62 seconds
Started Jan 21 08:39:56 PM PST 24
Finished Jan 21 08:39:58 PM PST 24
Peak memory 201132 kb
Host smart-e51578ed-4f33-4d93-af9d-6bb3d1f40a82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262930049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.3262930049
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.2343272540
Short name T1117
Test name
Test status
Simulation time 164349604 ps
CPU time 2.05 seconds
Started Jan 21 08:39:26 PM PST 24
Finished Jan 21 08:39:31 PM PST 24
Peak memory 212492 kb
Host smart-90ae7ae5-6ed7-4d36-8356-2dcbda408c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343272540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.2343272540
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.483783481
Short name T815
Test name
Test status
Simulation time 1187941864 ps
CPU time 10.36 seconds
Started Jan 21 08:39:17 PM PST 24
Finished Jan 21 08:39:28 PM PST 24
Peak memory 298544 kb
Host smart-afc5328e-657a-4264-be6e-f816979ddc66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483783481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empt
y.483783481
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.952718030
Short name T796
Test name
Test status
Simulation time 8123421802 ps
CPU time 153.54 seconds
Started Jan 21 08:39:18 PM PST 24
Finished Jan 21 08:41:54 PM PST 24
Peak memory 1066924 kb
Host smart-ebd3eb4a-986e-4408-9716-0a9f21e1ccdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952718030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.952718030
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.3285923004
Short name T1479
Test name
Test status
Simulation time 4714469519 ps
CPU time 591.55 seconds
Started Jan 21 08:39:09 PM PST 24
Finished Jan 21 08:49:02 PM PST 24
Peak memory 1339944 kb
Host smart-855fcdf3-72d6-4735-8888-fd8555969132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285923004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.3285923004
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.3450762848
Short name T1348
Test name
Test status
Simulation time 301190808 ps
CPU time 1.05 seconds
Started Jan 21 08:39:23 PM PST 24
Finished Jan 21 08:39:27 PM PST 24
Peak memory 202276 kb
Host smart-d3be6767-1172-49a2-923e-d6761735a98e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450762848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.3450762848
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.621605451
Short name T247
Test name
Test status
Simulation time 271832592 ps
CPU time 15.84 seconds
Started Jan 21 08:39:19 PM PST 24
Finished Jan 21 08:39:36 PM PST 24
Peak memory 257944 kb
Host smart-1868d026-410f-457c-8940-e73420d92808
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621605451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.
621605451
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.2327036480
Short name T1012
Test name
Test status
Simulation time 4874773458 ps
CPU time 233.93 seconds
Started Jan 21 08:39:08 PM PST 24
Finished Jan 21 08:43:04 PM PST 24
Peak memory 1448732 kb
Host smart-5670c7e4-b5dd-4a50-9b9c-985281916ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327036480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.2327036480
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.1575403286
Short name T1142
Test name
Test status
Simulation time 8975126490 ps
CPU time 125.8 seconds
Started Jan 21 08:39:59 PM PST 24
Finished Jan 21 08:42:06 PM PST 24
Peak memory 260708 kb
Host smart-90f44703-e472-46d7-895f-6025ea639183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575403286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.1575403286
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.3362299846
Short name T330
Test name
Test status
Simulation time 38860685 ps
CPU time 0.7 seconds
Started Jan 21 08:39:07 PM PST 24
Finished Jan 21 08:39:11 PM PST 24
Peak memory 201508 kb
Host smart-0378bcb3-836a-45fc-8daf-dc1135422bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362299846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.3362299846
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.781375432
Short name T395
Test name
Test status
Simulation time 5038703411 ps
CPU time 320.42 seconds
Started Jan 21 08:39:18 PM PST 24
Finished Jan 21 08:44:41 PM PST 24
Peak memory 290292 kb
Host smart-34de34e7-9e4c-4a99-bb2d-9cf174332b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781375432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.781375432
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_rx_oversample.3804987764
Short name T313
Test name
Test status
Simulation time 1321131509 ps
CPU time 120.71 seconds
Started Jan 21 08:39:08 PM PST 24
Finished Jan 21 08:41:11 PM PST 24
Peak memory 261548 kb
Host smart-fb811341-2f54-4dc3-9e3a-56c0d43ed9bd
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804987764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_rx_oversample
.3804987764
Directory /workspace/41.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.2112549557
Short name T191
Test name
Test status
Simulation time 9615227867 ps
CPU time 130.98 seconds
Started Jan 21 08:39:08 PM PST 24
Finished Jan 21 08:41:21 PM PST 24
Peak memory 243332 kb
Host smart-e9c698f9-ab95-4288-a68a-b9e05275e650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112549557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.2112549557
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.1034721145
Short name T530
Test name
Test status
Simulation time 4776223304 ps
CPU time 28.18 seconds
Started Jan 21 08:39:23 PM PST 24
Finished Jan 21 08:39:54 PM PST 24
Peak memory 210780 kb
Host smart-ad24feb9-2e11-433f-8aee-941813683d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034721145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.1034721145
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.776586788
Short name T1320
Test name
Test status
Simulation time 439373650 ps
CPU time 2.21 seconds
Started Jan 21 08:39:46 PM PST 24
Finished Jan 21 08:39:49 PM PST 24
Peak memory 202548 kb
Host smart-b5b9ca2e-5f8f-4a33-9f28-362a68782d47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776586788 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.776586788
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.1269722980
Short name T517
Test name
Test status
Simulation time 10077966439 ps
CPU time 60.13 seconds
Started Jan 21 08:39:39 PM PST 24
Finished Jan 21 08:40:40 PM PST 24
Peak memory 485924 kb
Host smart-6a91caea-a452-4e68-a7ba-ad764e5fcc16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269722980 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.1269722980
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.2400092485
Short name T1146
Test name
Test status
Simulation time 10187807864 ps
CPU time 6.22 seconds
Started Jan 21 08:39:47 PM PST 24
Finished Jan 21 08:39:54 PM PST 24
Peak memory 259876 kb
Host smart-d8be2a7e-d219-4177-b5a9-bfd8b9bb3b6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400092485 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.2400092485
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.2913442396
Short name T170
Test name
Test status
Simulation time 2057745973 ps
CPU time 2.78 seconds
Started Jan 21 08:39:46 PM PST 24
Finished Jan 21 08:39:50 PM PST 24
Peak memory 202604 kb
Host smart-53b82698-ad87-402d-a0e2-63bcac0210a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913442396 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.2913442396
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.2421086589
Short name T634
Test name
Test status
Simulation time 1533280218 ps
CPU time 6.49 seconds
Started Jan 21 08:39:33 PM PST 24
Finished Jan 21 08:39:41 PM PST 24
Peak memory 205768 kb
Host smart-29de8318-ab93-4290-ab55-a4ac97704277
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421086589 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.2421086589
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.767323366
Short name T290
Test name
Test status
Simulation time 36667387255 ps
CPU time 784.94 seconds
Started Jan 21 08:39:39 PM PST 24
Finished Jan 21 08:52:45 PM PST 24
Peak memory 5308656 kb
Host smart-f0f89f6b-80f9-4502-8676-035895d995f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767323366 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.767323366
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_perf.396966828
Short name T1492
Test name
Test status
Simulation time 566482882 ps
CPU time 3.49 seconds
Started Jan 21 08:39:49 PM PST 24
Finished Jan 21 08:39:54 PM PST 24
Peak memory 202548 kb
Host smart-4570e95f-5930-42cc-8974-604d0c5bc44f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396966828 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.i2c_target_perf.396966828
Directory /workspace/41.i2c_target_perf/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.2836629884
Short name T990
Test name
Test status
Simulation time 1523992982 ps
CPU time 16.05 seconds
Started Jan 21 08:50:59 PM PST 24
Finished Jan 21 08:51:52 PM PST 24
Peak memory 202576 kb
Host smart-fcf2f8ed-a30d-4151-abf4-c49c37015b99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836629884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.2836629884
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_all.3554060535
Short name T1517
Test name
Test status
Simulation time 170395882689 ps
CPU time 715.39 seconds
Started Jan 21 10:00:44 PM PST 24
Finished Jan 21 10:12:46 PM PST 24
Peak memory 275836 kb
Host smart-a6643660-df53-4afe-9ad8-90085f8cc675
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554060535 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.i2c_target_stress_all.3554060535
Directory /workspace/41.i2c_target_stress_all/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.379282840
Short name T1043
Test name
Test status
Simulation time 1816894985 ps
CPU time 33.61 seconds
Started Jan 21 10:05:45 PM PST 24
Finished Jan 21 10:06:27 PM PST 24
Peak memory 219224 kb
Host smart-8c52f077-ff0b-4886-80d7-569733f24556
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379282840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_rd.379282840
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.2835254943
Short name T1416
Test name
Test status
Simulation time 32124712363 ps
CPU time 1273.59 seconds
Started Jan 21 08:39:27 PM PST 24
Finished Jan 21 09:00:43 PM PST 24
Peak memory 6421548 kb
Host smart-da87a05b-744d-4bd6-8499-ea96fba65fe7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835254943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.2835254943
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.3879753423
Short name T486
Test name
Test status
Simulation time 32079420524 ps
CPU time 512.68 seconds
Started Jan 21 08:39:27 PM PST 24
Finished Jan 21 08:48:02 PM PST 24
Peak memory 2338260 kb
Host smart-7d0ab68a-177d-46c1-9f62-b9af3bd20981
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879753423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.3879753423
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.2761252852
Short name T823
Test name
Test status
Simulation time 6013104306 ps
CPU time 6.89 seconds
Started Jan 21 08:39:38 PM PST 24
Finished Jan 21 08:39:46 PM PST 24
Peak memory 206508 kb
Host smart-478a2d03-83b8-469f-a66c-7612fa8c268c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761252852 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.2761252852
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_ovf.916129889
Short name T376
Test name
Test status
Simulation time 12143561413 ps
CPU time 97.45 seconds
Started Jan 21 10:09:47 PM PST 24
Finished Jan 21 10:11:30 PM PST 24
Peak memory 304980 kb
Host smart-f8e9a9ad-7f62-4738-a02d-7b94d2bc839d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916129889 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_tx_ovf.916129889
Directory /workspace/41.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/41.i2c_target_unexp_stop.64832314
Short name T567
Test name
Test status
Simulation time 1915489179 ps
CPU time 8.89 seconds
Started Jan 21 08:39:39 PM PST 24
Finished Jan 21 08:39:49 PM PST 24
Peak memory 210820 kb
Host smart-a017c325-cdf0-41df-a0cf-3031a56a1066
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64832314 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_unexp_stop.64832314
Directory /workspace/41.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/42.i2c_alert_test.710215590
Short name T99
Test name
Test status
Simulation time 40156448 ps
CPU time 0.61 seconds
Started Jan 21 08:40:38 PM PST 24
Finished Jan 21 08:40:39 PM PST 24
Peak memory 201140 kb
Host smart-83e24650-0970-4349-b666-6f5d92afffc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710215590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.710215590
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.1198974704
Short name T1511
Test name
Test status
Simulation time 51724711 ps
CPU time 1.3 seconds
Started Jan 21 08:40:12 PM PST 24
Finished Jan 21 08:40:15 PM PST 24
Peak memory 202592 kb
Host smart-cdf75e5d-2026-471d-9305-55813cddaf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198974704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.1198974704
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.4255672061
Short name T885
Test name
Test status
Simulation time 628492450 ps
CPU time 13.99 seconds
Started Jan 21 08:40:04 PM PST 24
Finished Jan 21 08:40:18 PM PST 24
Peak memory 328896 kb
Host smart-a14b2766-7c7f-47b6-92b0-75026bbe19f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255672061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.4255672061
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.1452197721
Short name T360
Test name
Test status
Simulation time 5527673226 ps
CPU time 106.48 seconds
Started Jan 21 08:40:03 PM PST 24
Finished Jan 21 08:41:51 PM PST 24
Peak memory 837360 kb
Host smart-8ac31ac9-e7b4-4dcf-b64d-0408159b4451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452197721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.1452197721
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.1315427871
Short name T872
Test name
Test status
Simulation time 11273950305 ps
CPU time 806.01 seconds
Started Jan 21 08:39:56 PM PST 24
Finished Jan 21 08:53:23 PM PST 24
Peak memory 1541764 kb
Host smart-84abb604-20ca-4617-ab58-61e2e3b0e431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315427871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.1315427871
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.3417205016
Short name T1254
Test name
Test status
Simulation time 66433702 ps
CPU time 0.85 seconds
Started Jan 21 08:40:01 PM PST 24
Finished Jan 21 08:40:02 PM PST 24
Peak memory 202288 kb
Host smart-ac0ebf5b-9f90-4e8e-bee3-26e92d7c8e5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417205016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.3417205016
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.1123936191
Short name T74
Test name
Test status
Simulation time 303018257 ps
CPU time 3.79 seconds
Started Jan 21 08:40:03 PM PST 24
Finished Jan 21 08:40:08 PM PST 24
Peak memory 202552 kb
Host smart-2b7aa3a4-ddb0-4755-a8b2-4e63de5afb94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123936191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.1123936191
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.884614203
Short name T655
Test name
Test status
Simulation time 67371150393 ps
CPU time 392.35 seconds
Started Jan 21 08:39:58 PM PST 24
Finished Jan 21 08:46:31 PM PST 24
Peak memory 1710908 kb
Host smart-9dc6788b-e6ac-4635-a700-4745ebf390d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884614203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.884614203
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.25964806
Short name T871
Test name
Test status
Simulation time 2974467145 ps
CPU time 355.61 seconds
Started Jan 21 08:40:38 PM PST 24
Finished Jan 21 08:46:34 PM PST 24
Peak memory 439372 kb
Host smart-bbb7b860-54cd-4088-971e-49d9e2e5a0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25964806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.25964806
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.1206111838
Short name T156
Test name
Test status
Simulation time 40553333 ps
CPU time 0.64 seconds
Started Jan 21 08:39:58 PM PST 24
Finished Jan 21 08:39:59 PM PST 24
Peak memory 201504 kb
Host smart-1e188e23-843a-4868-9ee8-d796242c3485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206111838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.1206111838
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.929314421
Short name T38
Test name
Test status
Simulation time 27253660288 ps
CPU time 2148.98 seconds
Started Jan 21 08:40:05 PM PST 24
Finished Jan 21 09:15:55 PM PST 24
Peak memory 498324 kb
Host smart-30f884bd-5319-4b01-8a8b-6a7910acba3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929314421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.929314421
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_rx_oversample.3343853818
Short name T594
Test name
Test status
Simulation time 20888862634 ps
CPU time 133.74 seconds
Started Jan 21 08:40:01 PM PST 24
Finished Jan 21 08:42:16 PM PST 24
Peak memory 294904 kb
Host smart-7c0bceb7-4099-4c68-a90c-ead4913bbb72
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343853818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_rx_oversample
.3343853818
Directory /workspace/42.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.551171916
Short name T400
Test name
Test status
Simulation time 2751587898 ps
CPU time 77.94 seconds
Started Jan 21 08:39:58 PM PST 24
Finished Jan 21 08:41:17 PM PST 24
Peak memory 296264 kb
Host smart-06f79ba6-7fdc-4556-9728-ba838fbc5054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551171916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.551171916
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.2908709422
Short name T810
Test name
Test status
Simulation time 61865047704 ps
CPU time 697.39 seconds
Started Jan 21 08:40:22 PM PST 24
Finished Jan 21 08:52:00 PM PST 24
Peak memory 1810816 kb
Host smart-d051e244-6b8e-43c5-90e0-2af81a59c8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908709422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.2908709422
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.4048444870
Short name T255
Test name
Test status
Simulation time 1147231971 ps
CPU time 19.83 seconds
Started Jan 21 08:40:17 PM PST 24
Finished Jan 21 08:40:38 PM PST 24
Peak memory 216360 kb
Host smart-6c02b30a-7fb0-436e-b497-ba52bfa95102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048444870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.4048444870
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.1816447463
Short name T581
Test name
Test status
Simulation time 949203511 ps
CPU time 4.61 seconds
Started Jan 21 08:40:37 PM PST 24
Finished Jan 21 08:40:42 PM PST 24
Peak memory 202572 kb
Host smart-b852d0e3-cb11-479f-8a2b-eefcc9f206bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816447463 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.1816447463
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.1875799525
Short name T1344
Test name
Test status
Simulation time 10294769207 ps
CPU time 14.3 seconds
Started Jan 21 08:40:26 PM PST 24
Finished Jan 21 08:40:41 PM PST 24
Peak memory 296872 kb
Host smart-ec457900-d40c-4ccf-908e-0365509ef575
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875799525 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.1875799525
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.1289168922
Short name T289
Test name
Test status
Simulation time 10094568659 ps
CPU time 43.01 seconds
Started Jan 21 08:40:28 PM PST 24
Finished Jan 21 08:41:12 PM PST 24
Peak memory 456696 kb
Host smart-26ab5984-b04c-4271-acf3-93533ce92ea9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289168922 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.1289168922
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.1601379983
Short name T160
Test name
Test status
Simulation time 2283725977 ps
CPU time 2.6 seconds
Started Jan 21 08:40:37 PM PST 24
Finished Jan 21 08:40:41 PM PST 24
Peak memory 202744 kb
Host smart-85eaa130-af96-4ada-9052-909b72004b75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601379983 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.1601379983
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.2093717255
Short name T1368
Test name
Test status
Simulation time 1614566364 ps
CPU time 6.33 seconds
Started Jan 21 08:40:21 PM PST 24
Finished Jan 21 08:40:28 PM PST 24
Peak memory 202616 kb
Host smart-e04e2624-2134-4076-8e64-5ea8c39bfe22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093717255 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.2093717255
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.1800043446
Short name T698
Test name
Test status
Simulation time 8955575883 ps
CPU time 10.46 seconds
Started Jan 21 08:40:20 PM PST 24
Finished Jan 21 08:40:31 PM PST 24
Peak memory 372216 kb
Host smart-dfc6ec8f-4dd7-40d5-b96f-faa107fa957c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800043446 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.1800043446
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_perf.3776860218
Short name T668
Test name
Test status
Simulation time 1173544559 ps
CPU time 3.7 seconds
Started Jan 21 08:40:29 PM PST 24
Finished Jan 21 08:40:33 PM PST 24
Peak memory 206836 kb
Host smart-bcd95ecc-1322-4244-be85-47b2bbcdc7f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776860218 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_perf.3776860218
Directory /workspace/42.i2c_target_perf/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.1259488306
Short name T1322
Test name
Test status
Simulation time 2654573270 ps
CPU time 34.17 seconds
Started Jan 21 08:40:20 PM PST 24
Finished Jan 21 08:40:55 PM PST 24
Peak memory 202664 kb
Host smart-18a6d1bb-e6ec-4cd4-ae89-cbff2b40b758
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259488306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.1259488306
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_all.1861655049
Short name T855
Test name
Test status
Simulation time 25443667813 ps
CPU time 754.59 seconds
Started Jan 21 08:40:35 PM PST 24
Finished Jan 21 08:53:10 PM PST 24
Peak memory 3651132 kb
Host smart-d4b39a35-b945-438b-aad8-79c887119ea0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861655049 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_stress_all.1861655049
Directory /workspace/42.i2c_target_stress_all/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.4238807895
Short name T61
Test name
Test status
Simulation time 3708695971 ps
CPU time 12.92 seconds
Started Jan 21 08:40:21 PM PST 24
Finished Jan 21 08:40:35 PM PST 24
Peak memory 206488 kb
Host smart-25ce41fd-2106-4fc7-89b2-b5e27add9909
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238807895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.4238807895
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.697325360
Short name T1238
Test name
Test status
Simulation time 43196275437 ps
CPU time 953.17 seconds
Started Jan 21 08:40:25 PM PST 24
Finished Jan 21 08:56:19 PM PST 24
Peak memory 4917788 kb
Host smart-c9863c21-44ac-4540-833f-56724697749d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697325360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_wr.697325360
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.1212649318
Short name T738
Test name
Test status
Simulation time 31220016377 ps
CPU time 2566.67 seconds
Started Jan 21 08:40:22 PM PST 24
Finished Jan 21 09:23:10 PM PST 24
Peak memory 6162716 kb
Host smart-4f0eb7b8-3fc7-499d-85ea-98e1d036f02b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212649318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.1212649318
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.1175126615
Short name T287
Test name
Test status
Simulation time 3405533626 ps
CPU time 8.23 seconds
Started Jan 21 08:40:27 PM PST 24
Finished Jan 21 08:40:36 PM PST 24
Peak memory 207832 kb
Host smart-34f8068c-23ea-41b6-822f-988354dbe6a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175126615 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.1175126615
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_ovf.3690705578
Short name T754
Test name
Test status
Simulation time 12889245104 ps
CPU time 133.95 seconds
Started Jan 21 08:40:20 PM PST 24
Finished Jan 21 08:42:35 PM PST 24
Peak memory 345372 kb
Host smart-383f26a1-57f8-48c3-bec2-d086d28a3a68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690705578 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_tx_ovf.3690705578
Directory /workspace/42.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/42.i2c_target_unexp_stop.2436884864
Short name T978
Test name
Test status
Simulation time 1575664818 ps
CPU time 6.81 seconds
Started Jan 21 08:40:25 PM PST 24
Finished Jan 21 08:40:32 PM PST 24
Peak memory 202552 kb
Host smart-249095a7-9402-4857-ad44-e2b385d3e1fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436884864 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.i2c_target_unexp_stop.2436884864
Directory /workspace/42.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/43.i2c_alert_test.508217979
Short name T254
Test name
Test status
Simulation time 15230608 ps
CPU time 0.61 seconds
Started Jan 21 08:41:22 PM PST 24
Finished Jan 21 08:41:25 PM PST 24
Peak memory 201072 kb
Host smart-2728cad3-b60e-4acf-91ec-58758bfb83d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508217979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.508217979
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.1049458478
Short name T1081
Test name
Test status
Simulation time 29103615 ps
CPU time 1.37 seconds
Started Jan 21 08:41:01 PM PST 24
Finished Jan 21 08:41:03 PM PST 24
Peak memory 212460 kb
Host smart-0e175618-5ee5-442f-81ff-03b131739e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049458478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.1049458478
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.4122035883
Short name T207
Test name
Test status
Simulation time 268120856 ps
CPU time 13.14 seconds
Started Jan 21 08:40:42 PM PST 24
Finished Jan 21 08:40:56 PM PST 24
Peak memory 249948 kb
Host smart-d32e99dc-f39b-414a-9755-bf7d8980821c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122035883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.4122035883
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.2842399635
Short name T1524
Test name
Test status
Simulation time 2259334709 ps
CPU time 185.51 seconds
Started Jan 21 08:40:50 PM PST 24
Finished Jan 21 08:43:56 PM PST 24
Peak memory 763024 kb
Host smart-6effdef7-33be-49a5-a98f-6d340068f1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842399635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.2842399635
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.1753644915
Short name T1508
Test name
Test status
Simulation time 24941855893 ps
CPU time 381.04 seconds
Started Jan 21 08:40:43 PM PST 24
Finished Jan 21 08:47:05 PM PST 24
Peak memory 1693852 kb
Host smart-27070fa0-66a7-41ae-ba3a-5591191f30f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753644915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.1753644915
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.607628774
Short name T456
Test name
Test status
Simulation time 401154533 ps
CPU time 0.98 seconds
Started Jan 21 08:40:41 PM PST 24
Finished Jan 21 08:40:43 PM PST 24
Peak memory 202384 kb
Host smart-396bc4f7-0348-4762-89f0-306f807d9432
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607628774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fm
t.607628774
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.905434920
Short name T1258
Test name
Test status
Simulation time 618119187 ps
CPU time 8.02 seconds
Started Jan 21 08:40:48 PM PST 24
Finished Jan 21 08:40:57 PM PST 24
Peak memory 265312 kb
Host smart-e258481a-d2b4-4a32-9421-b9bb87b8c631
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905434920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.
905434920
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.738627541
Short name T380
Test name
Test status
Simulation time 4302163920 ps
CPU time 467.69 seconds
Started Jan 21 08:40:44 PM PST 24
Finished Jan 21 08:48:33 PM PST 24
Peak memory 1232004 kb
Host smart-2c414a70-3c36-428d-a96c-99b828f7dc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738627541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.738627541
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.1906242384
Short name T1276
Test name
Test status
Simulation time 3193050994 ps
CPU time 99.87 seconds
Started Jan 21 09:14:58 PM PST 24
Finished Jan 21 09:16:41 PM PST 24
Peak memory 260680 kb
Host smart-833c9b2f-4191-4ceb-ac24-60d07e009096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906242384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.1906242384
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.3407014544
Short name T776
Test name
Test status
Simulation time 137964412 ps
CPU time 0.61 seconds
Started Jan 21 08:40:44 PM PST 24
Finished Jan 21 08:40:46 PM PST 24
Peak memory 201504 kb
Host smart-ddae1622-5ff7-48d4-8a63-e8b10152f332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407014544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.3407014544
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.1863991273
Short name T473
Test name
Test status
Simulation time 7092173578 ps
CPU time 104.79 seconds
Started Jan 21 08:40:50 PM PST 24
Finished Jan 21 08:42:35 PM PST 24
Peak memory 218444 kb
Host smart-c6810276-1507-420e-8c49-b94133a1e2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863991273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.1863991273
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_rx_oversample.2901125159
Short name T839
Test name
Test status
Simulation time 5643211903 ps
CPU time 103.44 seconds
Started Jan 21 08:40:44 PM PST 24
Finished Jan 21 08:42:28 PM PST 24
Peak memory 259444 kb
Host smart-8ae7f1d8-776b-4871-ab9e-6b739f88a369
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901125159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_rx_oversample
.2901125159
Directory /workspace/43.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.2835842858
Short name T539
Test name
Test status
Simulation time 19036684842 ps
CPU time 45.1 seconds
Started Jan 21 08:40:41 PM PST 24
Finished Jan 21 08:41:27 PM PST 24
Peak memory 298544 kb
Host smart-d057b414-f763-4070-8299-45b8253a0f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835842858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.2835842858
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.1185069982
Short name T235
Test name
Test status
Simulation time 688837488 ps
CPU time 31 seconds
Started Jan 21 08:40:52 PM PST 24
Finished Jan 21 08:41:23 PM PST 24
Peak memory 210652 kb
Host smart-af9ac771-c16c-4579-a196-ce3a5434f64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185069982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.1185069982
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.328907528
Short name T431
Test name
Test status
Simulation time 3741253989 ps
CPU time 4.04 seconds
Started Jan 21 08:41:20 PM PST 24
Finished Jan 21 08:41:28 PM PST 24
Peak memory 202676 kb
Host smart-1e6b3921-d4df-415d-b324-e55c26bc12d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328907528 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.328907528
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.2669297756
Short name T795
Test name
Test status
Simulation time 10158766956 ps
CPU time 25.7 seconds
Started Jan 21 08:41:12 PM PST 24
Finished Jan 21 08:41:38 PM PST 24
Peak memory 333784 kb
Host smart-0e5ceb15-b6b5-4a0a-ba22-09cb1f4219cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669297756 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.2669297756
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.4242300066
Short name T357
Test name
Test status
Simulation time 10060679787 ps
CPU time 87.25 seconds
Started Jan 21 08:41:20 PM PST 24
Finished Jan 21 08:42:51 PM PST 24
Peak memory 623660 kb
Host smart-fa2b7d28-e06e-4229-87ea-6a5ff12d5789
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242300066 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.4242300066
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.3299126479
Short name T525
Test name
Test status
Simulation time 1730961770 ps
CPU time 2.33 seconds
Started Jan 21 08:41:23 PM PST 24
Finished Jan 21 08:41:27 PM PST 24
Peak memory 202648 kb
Host smart-19cb48c1-01c2-4550-8263-a190a9afa842
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299126479 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.3299126479
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.2853051384
Short name T1161
Test name
Test status
Simulation time 1011242098 ps
CPU time 4.58 seconds
Started Jan 21 08:41:07 PM PST 24
Finished Jan 21 08:41:12 PM PST 24
Peak memory 202588 kb
Host smart-3d70d473-7888-4975-8bdb-5ae236c8f9de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853051384 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.2853051384
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.3970387369
Short name T1527
Test name
Test status
Simulation time 20698758189 ps
CPU time 956.47 seconds
Started Jan 21 08:41:05 PM PST 24
Finished Jan 21 08:57:02 PM PST 24
Peak memory 4862204 kb
Host smart-4fdcfba0-0445-41ac-b7f3-f0b946787094
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970387369 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.3970387369
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_perf.2408701017
Short name T775
Test name
Test status
Simulation time 718228431 ps
CPU time 4.11 seconds
Started Jan 21 08:41:14 PM PST 24
Finished Jan 21 08:41:19 PM PST 24
Peak memory 202768 kb
Host smart-7e8d1f02-821f-4344-92f5-e4722dc568bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408701017 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_perf.2408701017
Directory /workspace/43.i2c_target_perf/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.3166079845
Short name T345
Test name
Test status
Simulation time 4282134896 ps
CPU time 12.7 seconds
Started Jan 21 08:41:00 PM PST 24
Finished Jan 21 08:41:13 PM PST 24
Peak memory 202584 kb
Host smart-25a98dd9-9451-4997-b4fc-4a0741ec2367
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166079845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.3166079845
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_all.3276232410
Short name T1471
Test name
Test status
Simulation time 21116745793 ps
CPU time 229.01 seconds
Started Jan 21 08:41:11 PM PST 24
Finished Jan 21 08:45:01 PM PST 24
Peak memory 1704992 kb
Host smart-4223d553-15e6-4e6c-93f8-ea797afa88e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276232410 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.i2c_target_stress_all.3276232410
Directory /workspace/43.i2c_target_stress_all/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.3462624184
Short name T1125
Test name
Test status
Simulation time 1666189881 ps
CPU time 6.58 seconds
Started Jan 21 08:41:05 PM PST 24
Finished Jan 21 08:41:12 PM PST 24
Peak memory 202508 kb
Host smart-2a9b98fa-5b5f-47d7-b082-ca4cac166f66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462624184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.3462624184
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.1210902671
Short name T1124
Test name
Test status
Simulation time 31259867363 ps
CPU time 1585.6 seconds
Started Jan 21 08:40:57 PM PST 24
Finished Jan 21 09:07:23 PM PST 24
Peak memory 6941168 kb
Host smart-664ade3c-b1e1-474a-9a4f-3e5e4b55244f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210902671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.1210902671
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.1154243218
Short name T1406
Test name
Test status
Simulation time 11601721332 ps
CPU time 148.03 seconds
Started Jan 21 08:41:03 PM PST 24
Finished Jan 21 08:43:32 PM PST 24
Peak memory 709276 kb
Host smart-01a79f73-f4d0-40c8-88d8-b79cfe7b018c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154243218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.1154243218
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.804359391
Short name T950
Test name
Test status
Simulation time 7068286066 ps
CPU time 6.89 seconds
Started Jan 21 08:41:12 PM PST 24
Finished Jan 21 08:41:20 PM PST 24
Peak memory 204956 kb
Host smart-dd8f891c-d76a-4ed0-9d0b-c09dcf038b96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804359391 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_timeout.804359391
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_ovf.2062706464
Short name T537
Test name
Test status
Simulation time 10755583229 ps
CPU time 143.97 seconds
Started Jan 21 08:41:15 PM PST 24
Finished Jan 21 08:43:39 PM PST 24
Peak memory 361172 kb
Host smart-bba5a573-aa0e-40ee-aab3-8ff838625072
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062706464 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_tx_ovf.2062706464
Directory /workspace/43.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/43.i2c_target_unexp_stop.1888923069
Short name T300
Test name
Test status
Simulation time 5590306890 ps
CPU time 7.11 seconds
Started Jan 21 08:41:13 PM PST 24
Finished Jan 21 08:41:20 PM PST 24
Peak memory 202664 kb
Host smart-90918571-60e6-46b3-b65c-23496886f4bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888923069 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.i2c_target_unexp_stop.1888923069
Directory /workspace/43.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/44.i2c_alert_test.3467655752
Short name T269
Test name
Test status
Simulation time 51203477 ps
CPU time 0.62 seconds
Started Jan 21 08:42:00 PM PST 24
Finished Jan 21 08:42:02 PM PST 24
Peak memory 201980 kb
Host smart-beff9ca1-9ff2-42fd-ab72-a3502a5e614b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467655752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.3467655752
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.3161844619
Short name T1103
Test name
Test status
Simulation time 167168510 ps
CPU time 2.19 seconds
Started Jan 21 08:41:30 PM PST 24
Finished Jan 21 08:41:33 PM PST 24
Peak memory 210736 kb
Host smart-47ca9b33-6791-4976-b339-79deeba089f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161844619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.3161844619
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.3135227047
Short name T569
Test name
Test status
Simulation time 2484319101 ps
CPU time 11.03 seconds
Started Jan 21 08:41:30 PM PST 24
Finished Jan 21 08:41:42 PM PST 24
Peak memory 329092 kb
Host smart-77f52360-dfc2-48ac-ac5f-2598c079b9c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135227047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.3135227047
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.1382540075
Short name T669
Test name
Test status
Simulation time 32920454303 ps
CPU time 171.9 seconds
Started Jan 21 08:41:32 PM PST 24
Finished Jan 21 08:44:25 PM PST 24
Peak memory 1108168 kb
Host smart-2e9f8577-1738-4ce5-8360-153bff2b296f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382540075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.1382540075
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.2463201555
Short name T1008
Test name
Test status
Simulation time 4054713102 ps
CPU time 239.4 seconds
Started Jan 21 08:41:30 PM PST 24
Finished Jan 21 08:45:31 PM PST 24
Peak memory 1214640 kb
Host smart-be5c0dd2-c6f6-4960-8b7d-9ee1412005ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463201555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.2463201555
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.2902674092
Short name T511
Test name
Test status
Simulation time 123280411 ps
CPU time 1.12 seconds
Started Jan 21 08:41:33 PM PST 24
Finished Jan 21 08:41:35 PM PST 24
Peak memory 202312 kb
Host smart-258b3dfa-efde-489c-a328-7b9a4c8cb0b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902674092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.2902674092
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.3239524460
Short name T1199
Test name
Test status
Simulation time 408727482 ps
CPU time 5.69 seconds
Started Jan 21 08:41:32 PM PST 24
Finished Jan 21 08:41:38 PM PST 24
Peak memory 242328 kb
Host smart-8a6d00c6-b57d-4709-af60-6e1af0cfe36d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239524460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.3239524460
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.3262135219
Short name T1221
Test name
Test status
Simulation time 6010577385 ps
CPU time 357.01 seconds
Started Jan 21 08:41:31 PM PST 24
Finished Jan 21 08:47:29 PM PST 24
Peak memory 1718252 kb
Host smart-d2d269b2-8b89-4b03-9fe5-7a5b33b88357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262135219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.3262135219
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.2374921012
Short name T1145
Test name
Test status
Simulation time 2418477214 ps
CPU time 119.56 seconds
Started Jan 21 08:59:55 PM PST 24
Finished Jan 21 09:02:20 PM PST 24
Peak memory 230244 kb
Host smart-576deee2-cf39-4c05-8b8c-55fcf5534817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374921012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.2374921012
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.4037463056
Short name T898
Test name
Test status
Simulation time 24787374 ps
CPU time 0.61 seconds
Started Jan 21 08:41:20 PM PST 24
Finished Jan 21 08:41:24 PM PST 24
Peak memory 201448 kb
Host smart-176e690e-3608-4b66-ae07-31c1f0cf1ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037463056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.4037463056
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.1636686756
Short name T147
Test name
Test status
Simulation time 1875593453 ps
CPU time 8.08 seconds
Started Jan 21 08:41:33 PM PST 24
Finished Jan 21 08:41:42 PM PST 24
Peak memory 218316 kb
Host smart-ae3b8873-53a5-47cb-8458-843182b0ce89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636686756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.1636686756
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_rx_oversample.1083561207
Short name T1067
Test name
Test status
Simulation time 2584641178 ps
CPU time 239.09 seconds
Started Jan 21 08:41:32 PM PST 24
Finished Jan 21 08:45:32 PM PST 24
Peak memory 299768 kb
Host smart-c2b1a0ea-e197-4757-8e3c-1d1c28b65a64
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083561207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_rx_oversample
.1083561207
Directory /workspace/44.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.1997623869
Short name T308
Test name
Test status
Simulation time 10043721469 ps
CPU time 203.31 seconds
Started Jan 21 08:41:19 PM PST 24
Finished Jan 21 08:44:47 PM PST 24
Peak memory 289728 kb
Host smart-97d6ca46-0dd2-4d2b-a5d6-db536e1e9727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997623869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.1997623869
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.1396559817
Short name T1087
Test name
Test status
Simulation time 27856924396 ps
CPU time 3291.84 seconds
Started Jan 21 08:41:31 PM PST 24
Finished Jan 21 09:36:24 PM PST 24
Peak memory 3562360 kb
Host smart-87738760-0de4-4aee-b174-27ba19b9b8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396559817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.1396559817
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.1813670809
Short name T187
Test name
Test status
Simulation time 982257147 ps
CPU time 8.65 seconds
Started Jan 21 08:41:33 PM PST 24
Finished Jan 21 08:41:43 PM PST 24
Peak memory 210664 kb
Host smart-4ac7c923-5e93-486a-99f9-91340f8d6ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813670809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.1813670809
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.4133160019
Short name T495
Test name
Test status
Simulation time 1209855032 ps
CPU time 4.65 seconds
Started Jan 21 08:41:53 PM PST 24
Finished Jan 21 08:41:59 PM PST 24
Peak memory 202576 kb
Host smart-dd2931b8-19f6-468a-a088-cd90691c3482
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133160019 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.4133160019
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.3549779392
Short name T1288
Test name
Test status
Simulation time 10386187202 ps
CPU time 11.45 seconds
Started Jan 21 08:41:51 PM PST 24
Finished Jan 21 08:42:06 PM PST 24
Peak memory 251092 kb
Host smart-5184f02d-42f6-4147-96f4-0642f23b5097
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549779392 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.3549779392
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.1397511883
Short name T343
Test name
Test status
Simulation time 10046337426 ps
CPU time 80.15 seconds
Started Jan 21 09:34:29 PM PST 24
Finished Jan 21 09:36:07 PM PST 24
Peak memory 585876 kb
Host smart-13ed464a-adc3-4040-839f-29cd0363c0c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397511883 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.1397511883
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.979630927
Short name T1275
Test name
Test status
Simulation time 1881567169 ps
CPU time 2.62 seconds
Started Jan 21 08:42:01 PM PST 24
Finished Jan 21 08:42:04 PM PST 24
Peak memory 202600 kb
Host smart-190133b4-f173-419c-913d-cdb48506cfad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979630927 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.i2c_target_hrst.979630927
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.3082795235
Short name T802
Test name
Test status
Simulation time 1770943355 ps
CPU time 5.09 seconds
Started Jan 21 08:41:44 PM PST 24
Finished Jan 21 08:41:50 PM PST 24
Peak memory 202532 kb
Host smart-04cf622e-8a8b-4e50-844f-0d8d348e3254
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082795235 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.3082795235
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.4200931228
Short name T1355
Test name
Test status
Simulation time 16231086449 ps
CPU time 75.37 seconds
Started Jan 21 08:41:49 PM PST 24
Finished Jan 21 08:43:10 PM PST 24
Peak memory 970768 kb
Host smart-84815bc0-23f2-42b6-b165-7e8258b28ac4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200931228 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.4200931228
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_perf.835091809
Short name T650
Test name
Test status
Simulation time 718562450 ps
CPU time 4.57 seconds
Started Jan 21 09:03:31 PM PST 24
Finished Jan 21 09:03:52 PM PST 24
Peak memory 202508 kb
Host smart-3124fc88-392a-4906-aed3-be789039da06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835091809 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.i2c_target_perf.835091809
Directory /workspace/44.i2c_target_perf/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.2323342250
Short name T1203
Test name
Test status
Simulation time 1637526384 ps
CPU time 16.27 seconds
Started Jan 21 08:41:38 PM PST 24
Finished Jan 21 08:41:58 PM PST 24
Peak memory 202484 kb
Host smart-78037643-9023-4f20-b58d-0d0ee0a8c6a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323342250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.2323342250
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_all.2230558269
Short name T169
Test name
Test status
Simulation time 56300573669 ps
CPU time 115.32 seconds
Started Jan 21 08:41:55 PM PST 24
Finished Jan 21 08:43:53 PM PST 24
Peak memory 215484 kb
Host smart-5a966725-7791-45d8-9d2e-532ec5b48622
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230558269 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.i2c_target_stress_all.2230558269
Directory /workspace/44.i2c_target_stress_all/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.3129904807
Short name T1096
Test name
Test status
Simulation time 1607916406 ps
CPU time 22.52 seconds
Started Jan 21 08:41:38 PM PST 24
Finished Jan 21 08:42:04 PM PST 24
Peak memory 213364 kb
Host smart-eaec16b3-2c80-44cc-b708-2c6a201d88b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129904807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.3129904807
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.426618487
Short name T55
Test name
Test status
Simulation time 7869779310 ps
CPU time 19.3 seconds
Started Jan 21 08:41:39 PM PST 24
Finished Jan 21 08:42:01 PM PST 24
Peak memory 553216 kb
Host smart-5144cc96-30b7-413d-bfd7-dad15b693b54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426618487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_wr.426618487
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.3151923250
Short name T1244
Test name
Test status
Simulation time 34949109756 ps
CPU time 3549.87 seconds
Started Jan 21 08:41:39 PM PST 24
Finished Jan 21 09:40:52 PM PST 24
Peak memory 8102556 kb
Host smart-c4a7eaa9-84b0-4420-8564-ac59c764b568
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151923250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.3151923250
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.3651496879
Short name T891
Test name
Test status
Simulation time 1837846943 ps
CPU time 7.24 seconds
Started Jan 21 08:41:44 PM PST 24
Finished Jan 21 08:41:52 PM PST 24
Peak memory 210772 kb
Host smart-c234ceb3-5cfd-435f-b86f-3c7d1ce9a6e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651496879 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.3651496879
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_ovf.143330978
Short name T361
Test name
Test status
Simulation time 5081343641 ps
CPU time 97.56 seconds
Started Jan 21 08:41:47 PM PST 24
Finished Jan 21 08:43:26 PM PST 24
Peak memory 310004 kb
Host smart-8767441f-4ad1-4478-9c4e-294fdc6009fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143330978 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_tx_ovf.143330978
Directory /workspace/44.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/44.i2c_target_unexp_stop.1435655228
Short name T578
Test name
Test status
Simulation time 1241405533 ps
CPU time 5.8 seconds
Started Jan 21 08:41:44 PM PST 24
Finished Jan 21 08:41:51 PM PST 24
Peak memory 202560 kb
Host smart-d4b145fc-a2c4-40fa-b705-dad594769a3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435655228 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.i2c_target_unexp_stop.1435655228
Directory /workspace/44.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/45.i2c_alert_test.3483075023
Short name T989
Test name
Test status
Simulation time 38860896 ps
CPU time 0.6 seconds
Started Jan 21 08:42:47 PM PST 24
Finished Jan 21 08:42:49 PM PST 24
Peak memory 201084 kb
Host smart-96dbbbc8-008a-41ea-b803-90ce79b11549
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483075023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.3483075023
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.2150474113
Short name T1132
Test name
Test status
Simulation time 53327440 ps
CPU time 1.59 seconds
Started Jan 21 08:42:16 PM PST 24
Finished Jan 21 08:42:19 PM PST 24
Peak memory 210728 kb
Host smart-cdfc7f1f-cd80-43f5-9ada-f6b5271ad6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150474113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.2150474113
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.1986799518
Short name T1447
Test name
Test status
Simulation time 2445419252 ps
CPU time 9.83 seconds
Started Jan 21 08:42:07 PM PST 24
Finished Jan 21 08:42:18 PM PST 24
Peak memory 297132 kb
Host smart-ff998845-bc04-4476-9360-2ed8fa327795
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986799518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.1986799518
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.1684595934
Short name T1354
Test name
Test status
Simulation time 3005797290 ps
CPU time 104.29 seconds
Started Jan 21 08:42:21 PM PST 24
Finished Jan 21 08:44:06 PM PST 24
Peak memory 701672 kb
Host smart-e4b4f190-e82f-462c-99a2-a3e61b892d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684595934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.1684595934
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.308037611
Short name T792
Test name
Test status
Simulation time 21526496774 ps
CPU time 424.94 seconds
Started Jan 21 08:42:08 PM PST 24
Finished Jan 21 08:49:13 PM PST 24
Peak memory 1738276 kb
Host smart-7b443d30-f198-4f2c-afea-ae28c3b7659e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308037611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.308037611
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.2638098593
Short name T1027
Test name
Test status
Simulation time 409803307 ps
CPU time 1.05 seconds
Started Jan 21 08:42:10 PM PST 24
Finished Jan 21 08:42:11 PM PST 24
Peak memory 202328 kb
Host smart-3c65fed0-49b6-4b75-a86b-0f7d1d8269af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638098593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.2638098593
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.679515040
Short name T699
Test name
Test status
Simulation time 164924056 ps
CPU time 8.8 seconds
Started Jan 21 08:42:16 PM PST 24
Finished Jan 21 08:42:26 PM PST 24
Peak memory 202764 kb
Host smart-cc05e8c3-d77f-4d43-803a-02e50f77d566
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679515040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.
679515040
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.1012848716
Short name T470
Test name
Test status
Simulation time 17143774445 ps
CPU time 443.45 seconds
Started Jan 21 08:42:08 PM PST 24
Finished Jan 21 08:49:32 PM PST 24
Peak memory 1862436 kb
Host smart-ee5dc6a7-9f01-40d0-b03c-4c267cbae1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012848716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.1012848716
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.3706841091
Short name T665
Test name
Test status
Simulation time 1451703608 ps
CPU time 45.15 seconds
Started Jan 21 08:42:42 PM PST 24
Finished Jan 21 08:43:28 PM PST 24
Peak memory 296516 kb
Host smart-54f21786-84d5-4105-9a22-c573e602a1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706841091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.3706841091
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.610538657
Short name T1000
Test name
Test status
Simulation time 31511723 ps
CPU time 0.62 seconds
Started Jan 21 08:42:06 PM PST 24
Finished Jan 21 08:42:08 PM PST 24
Peak memory 201444 kb
Host smart-147976f8-b261-417a-92cb-20c7f1c25450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610538657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.610538657
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.806666929
Short name T1233
Test name
Test status
Simulation time 29567721453 ps
CPU time 46.3 seconds
Started Jan 21 08:42:15 PM PST 24
Finished Jan 21 08:43:02 PM PST 24
Peak memory 218284 kb
Host smart-943c4e85-1d89-4794-a016-c3ccfac09735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806666929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.806666929
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_rx_oversample.1547856802
Short name T1486
Test name
Test status
Simulation time 8426760079 ps
CPU time 75.47 seconds
Started Jan 21 08:42:08 PM PST 24
Finished Jan 21 08:43:24 PM PST 24
Peak memory 275268 kb
Host smart-962a2222-d8bc-436f-8fd6-e895056a3f43
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547856802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_rx_oversample
.1547856802
Directory /workspace/45.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.781485148
Short name T1030
Test name
Test status
Simulation time 2231933555 ps
CPU time 70.22 seconds
Started Jan 21 09:13:43 PM PST 24
Finished Jan 21 09:14:54 PM PST 24
Peak memory 340736 kb
Host smart-14561313-1747-42bb-be60-657ee17ecae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781485148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.781485148
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.3108328513
Short name T728
Test name
Test status
Simulation time 1633283047 ps
CPU time 34.13 seconds
Started Jan 21 08:42:16 PM PST 24
Finished Jan 21 08:42:52 PM PST 24
Peak memory 210652 kb
Host smart-0edc57e7-5dad-42e7-bcf0-0d7cb215c497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108328513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.3108328513
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.2755862436
Short name T216
Test name
Test status
Simulation time 449469283 ps
CPU time 2.15 seconds
Started Jan 21 09:12:16 PM PST 24
Finished Jan 21 09:12:23 PM PST 24
Peak memory 202580 kb
Host smart-b09e3b17-489c-4ade-a2af-1d534f9f93d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755862436 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.2755862436
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.3105376616
Short name T554
Test name
Test status
Simulation time 10346977207 ps
CPU time 21.13 seconds
Started Jan 21 08:42:29 PM PST 24
Finished Jan 21 08:42:51 PM PST 24
Peak memory 345044 kb
Host smart-ae48ac5c-74c1-4b55-88ed-415ab4fc4539
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105376616 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.3105376616
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.2984214950
Short name T977
Test name
Test status
Simulation time 10146353607 ps
CPU time 12.69 seconds
Started Jan 21 08:42:24 PM PST 24
Finished Jan 21 08:42:37 PM PST 24
Peak memory 286924 kb
Host smart-4845595a-3ebb-42c8-a86b-2bb00820e29e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984214950 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.2984214950
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.2854200542
Short name T928
Test name
Test status
Simulation time 967814793 ps
CPU time 3.95 seconds
Started Jan 21 10:26:22 PM PST 24
Finished Jan 21 10:26:45 PM PST 24
Peak memory 202676 kb
Host smart-646f87d1-942a-42e8-a1ff-c43a061c4148
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854200542 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.2854200542
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.1710582647
Short name T1168
Test name
Test status
Simulation time 5995522263 ps
CPU time 7.1 seconds
Started Jan 21 08:42:29 PM PST 24
Finished Jan 21 08:42:37 PM PST 24
Peak memory 209960 kb
Host smart-effe0889-509d-42ec-bc06-03633151d00c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710582647 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.1710582647
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.1367784832
Short name T427
Test name
Test status
Simulation time 4922560542 ps
CPU time 45.47 seconds
Started Jan 21 08:42:24 PM PST 24
Finished Jan 21 08:43:11 PM PST 24
Peak memory 993140 kb
Host smart-f2321924-0e49-451b-b2c2-b826d76fbb63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367784832 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.1367784832
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_perf.314989406
Short name T1157
Test name
Test status
Simulation time 641803197 ps
CPU time 3.61 seconds
Started Jan 21 10:09:45 PM PST 24
Finished Jan 21 10:09:53 PM PST 24
Peak memory 202588 kb
Host smart-2d01ca72-21cd-4de2-9142-c08f927f44b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314989406 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.i2c_target_perf.314989406
Directory /workspace/45.i2c_target_perf/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.1210647404
Short name T377
Test name
Test status
Simulation time 1276306090 ps
CPU time 15.41 seconds
Started Jan 21 08:42:21 PM PST 24
Finished Jan 21 08:42:37 PM PST 24
Peak memory 202548 kb
Host smart-651c3619-330a-4053-a3fb-52cfb8c82396
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210647404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.1210647404
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_all.1256178883
Short name T1413
Test name
Test status
Simulation time 33324086450 ps
CPU time 1171.86 seconds
Started Jan 21 08:42:33 PM PST 24
Finished Jan 21 09:02:06 PM PST 24
Peak memory 5240220 kb
Host smart-4a702ddc-2f48-46e6-a396-615c9aa4e719
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256178883 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_target_stress_all.1256178883
Directory /workspace/45.i2c_target_stress_all/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.2281178048
Short name T1461
Test name
Test status
Simulation time 6762708853 ps
CPU time 16.5 seconds
Started Jan 21 08:42:28 PM PST 24
Finished Jan 21 08:42:45 PM PST 24
Peak memory 207496 kb
Host smart-9ea4aad7-7225-4299-b2e6-a22ba4b5c37e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281178048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.2281178048
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.2157589807
Short name T1062
Test name
Test status
Simulation time 23622894441 ps
CPU time 89.08 seconds
Started Jan 21 08:42:16 PM PST 24
Finished Jan 21 08:43:46 PM PST 24
Peak memory 1266648 kb
Host smart-ed7239bd-ee1d-4580-a1d3-3d976aaf5d27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157589807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.2157589807
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.1239947753
Short name T1474
Test name
Test status
Simulation time 24203904147 ps
CPU time 1382.05 seconds
Started Jan 21 08:42:27 PM PST 24
Finished Jan 21 09:05:30 PM PST 24
Peak memory 2747288 kb
Host smart-e0f5a519-ec99-4fe6-87ed-1caf763f3fb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239947753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.1239947753
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.2048536338
Short name T1061
Test name
Test status
Simulation time 1366654709 ps
CPU time 6.24 seconds
Started Jan 21 08:42:26 PM PST 24
Finished Jan 21 08:42:33 PM PST 24
Peak memory 205576 kb
Host smart-3ec35888-a43b-46cf-9eb5-6d58fb932b76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048536338 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.2048536338
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_ovf.1885154001
Short name T876
Test name
Test status
Simulation time 4794479181 ps
CPU time 51.93 seconds
Started Jan 21 08:42:29 PM PST 24
Finished Jan 21 08:43:22 PM PST 24
Peak memory 258060 kb
Host smart-d97c6511-f531-4959-889c-8e6137fd4b62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885154001 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_tx_ovf.1885154001
Directory /workspace/45.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/45.i2c_target_unexp_stop.191766725
Short name T654
Test name
Test status
Simulation time 2411660713 ps
CPU time 5.22 seconds
Started Jan 21 08:42:28 PM PST 24
Finished Jan 21 08:42:34 PM PST 24
Peak memory 202980 kb
Host smart-249b73f0-fba3-445d-9be7-808f88ba7436
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191766725 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_unexp_stop.191766725
Directory /workspace/45.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/46.i2c_alert_test.2048349565
Short name T800
Test name
Test status
Simulation time 15124263 ps
CPU time 0.67 seconds
Started Jan 21 08:43:20 PM PST 24
Finished Jan 21 08:43:22 PM PST 24
Peak memory 202044 kb
Host smart-897610cf-05df-412f-badb-1c755886de30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048349565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.2048349565
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.2520360418
Short name T586
Test name
Test status
Simulation time 59695755 ps
CPU time 1.13 seconds
Started Jan 21 08:42:54 PM PST 24
Finished Jan 21 08:42:55 PM PST 24
Peak memory 210756 kb
Host smart-c813a90e-2601-4e6a-a38b-9b9440cc5105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520360418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.2520360418
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.436818026
Short name T1369
Test name
Test status
Simulation time 688369754 ps
CPU time 17.66 seconds
Started Jan 21 08:42:49 PM PST 24
Finished Jan 21 08:43:08 PM PST 24
Peak memory 261196 kb
Host smart-bf120ac1-a9c5-4af2-9dd4-0d8e2bf84fa5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436818026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empt
y.436818026
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.520429934
Short name T1381
Test name
Test status
Simulation time 12449895155 ps
CPU time 260.55 seconds
Started Jan 21 08:42:50 PM PST 24
Finished Jan 21 08:47:12 PM PST 24
Peak memory 898892 kb
Host smart-73ed1738-43a8-46fa-b523-c3f76fa8a8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520429934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.520429934
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.2239598366
Short name T183
Test name
Test status
Simulation time 23932527658 ps
CPU time 479.37 seconds
Started Jan 21 08:42:47 PM PST 24
Finished Jan 21 08:50:48 PM PST 24
Peak memory 1787932 kb
Host smart-9367926c-4ea4-4468-b28a-c0227db4ccae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239598366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.2239598366
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.1918554760
Short name T1016
Test name
Test status
Simulation time 164059064 ps
CPU time 0.88 seconds
Started Jan 21 08:42:49 PM PST 24
Finished Jan 21 08:42:51 PM PST 24
Peak memory 202352 kb
Host smart-7d457b40-6f40-4401-a778-2c849398ec65
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918554760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.1918554760
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.2630460633
Short name T1302
Test name
Test status
Simulation time 3207621888 ps
CPU time 5.31 seconds
Started Jan 21 08:42:55 PM PST 24
Finished Jan 21 08:43:01 PM PST 24
Peak memory 202508 kb
Host smart-563c5669-62be-4328-94a7-65fc5ae25d14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630460633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.2630460633
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.3129672525
Short name T672
Test name
Test status
Simulation time 6426696644 ps
CPU time 649.22 seconds
Started Jan 21 08:42:46 PM PST 24
Finished Jan 21 08:53:36 PM PST 24
Peak memory 1577716 kb
Host smart-33a824eb-8e9d-4715-9ffb-df4221218da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129672525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.3129672525
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.20186037
Short name T1229
Test name
Test status
Simulation time 3862405853 ps
CPU time 107.83 seconds
Started Jan 21 08:43:21 PM PST 24
Finished Jan 21 08:45:09 PM PST 24
Peak memory 299472 kb
Host smart-64396337-13d9-46f0-ad57-2e13ad1e188e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20186037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.20186037
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.2190904268
Short name T143
Test name
Test status
Simulation time 216433470 ps
CPU time 0.61 seconds
Started Jan 21 08:42:46 PM PST 24
Finished Jan 21 08:42:48 PM PST 24
Peak memory 201556 kb
Host smart-afafa1e4-9622-412d-858d-b7e5b89a9fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190904268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.2190904268
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.952937875
Short name T1154
Test name
Test status
Simulation time 4785144557 ps
CPU time 5.87 seconds
Started Jan 21 08:42:49 PM PST 24
Finished Jan 21 08:42:56 PM PST 24
Peak memory 210820 kb
Host smart-900ba580-f831-4deb-96ee-903e0ff565d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952937875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.952937875
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_rx_oversample.2267430758
Short name T1290
Test name
Test status
Simulation time 3448883901 ps
CPU time 486.24 seconds
Started Jan 21 08:42:47 PM PST 24
Finished Jan 21 08:50:55 PM PST 24
Peak memory 380452 kb
Host smart-73a910de-09e7-4c0e-a5f6-9547b1a199c2
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267430758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_rx_oversample
.2267430758
Directory /workspace/46.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.957125054
Short name T297
Test name
Test status
Simulation time 8081147612 ps
CPU time 57.34 seconds
Started Jan 21 08:42:43 PM PST 24
Finished Jan 21 08:43:41 PM PST 24
Peak memory 279912 kb
Host smart-570e9d09-ca78-46fd-b388-0eba276dd4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957125054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.957125054
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.2063242665
Short name T924
Test name
Test status
Simulation time 29034468433 ps
CPU time 2640.24 seconds
Started Jan 21 08:42:49 PM PST 24
Finished Jan 21 09:26:50 PM PST 24
Peak memory 2101516 kb
Host smart-f07c886b-e9ec-4144-baa8-00820914054b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063242665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.2063242665
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.4250720330
Short name T118
Test name
Test status
Simulation time 1418649996 ps
CPU time 21.05 seconds
Started Jan 21 08:53:24 PM PST 24
Finished Jan 21 08:54:03 PM PST 24
Peak memory 218852 kb
Host smart-d54d2ae4-a82b-48b3-b18c-70bcb1993cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250720330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.4250720330
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.868676874
Short name T1196
Test name
Test status
Simulation time 922236708 ps
CPU time 3.73 seconds
Started Jan 21 09:22:47 PM PST 24
Finished Jan 21 09:22:53 PM PST 24
Peak memory 202624 kb
Host smart-7a92502f-4409-4ac6-9824-b23d65634d1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868676874 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.868676874
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.2374342201
Short name T193
Test name
Test status
Simulation time 10096868988 ps
CPU time 19.37 seconds
Started Jan 21 08:43:05 PM PST 24
Finished Jan 21 08:43:25 PM PST 24
Peak memory 307040 kb
Host smart-fbbba731-eff6-4478-8839-a1b2a29831c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374342201 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.2374342201
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.3489400058
Short name T426
Test name
Test status
Simulation time 10188775271 ps
CPU time 67.23 seconds
Started Jan 21 08:43:06 PM PST 24
Finished Jan 21 08:44:14 PM PST 24
Peak memory 591060 kb
Host smart-4e5d61f2-e47c-42b1-91ad-191347a748f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489400058 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.3489400058
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.2812375352
Short name T63
Test name
Test status
Simulation time 526354926 ps
CPU time 2.76 seconds
Started Jan 21 09:15:07 PM PST 24
Finished Jan 21 09:15:11 PM PST 24
Peak memory 202528 kb
Host smart-81ff1498-5868-4492-9d1a-9c7585694c8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812375352 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.2812375352
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.1363460036
Short name T1029
Test name
Test status
Simulation time 2680758925 ps
CPU time 6.54 seconds
Started Jan 21 08:43:01 PM PST 24
Finished Jan 21 08:43:08 PM PST 24
Peak memory 208780 kb
Host smart-95217d8d-cf0b-423c-bfbf-5c7e3d72c444
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363460036 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.1363460036
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.1041308770
Short name T1134
Test name
Test status
Simulation time 18099695878 ps
CPU time 71.95 seconds
Started Jan 21 08:43:06 PM PST 24
Finished Jan 21 08:44:19 PM PST 24
Peak memory 1053168 kb
Host smart-8ab17be7-4156-44be-957e-d0726f931835
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041308770 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.1041308770
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_perf.2595150216
Short name T1328
Test name
Test status
Simulation time 1428360918 ps
CPU time 4.46 seconds
Started Jan 21 08:43:06 PM PST 24
Finished Jan 21 08:43:11 PM PST 24
Peak memory 202560 kb
Host smart-e2d61f4b-9cbb-40df-89a6-c210021005e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595150216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_perf.2595150216
Directory /workspace/46.i2c_target_perf/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.3832703409
Short name T253
Test name
Test status
Simulation time 2543996475 ps
CPU time 17.13 seconds
Started Jan 21 08:42:51 PM PST 24
Finished Jan 21 08:43:08 PM PST 24
Peak memory 202588 kb
Host smart-1ffe972d-ff08-45ef-9e0e-b9673c9f3d57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832703409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.3832703409
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_all.2493407097
Short name T729
Test name
Test status
Simulation time 20840506040 ps
CPU time 296.79 seconds
Started Jan 21 08:43:06 PM PST 24
Finished Jan 21 08:48:04 PM PST 24
Peak memory 1607944 kb
Host smart-d9d8cce1-7594-4486-953c-de846e1809f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493407097 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.i2c_target_stress_all.2493407097
Directory /workspace/46.i2c_target_stress_all/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.3230096305
Short name T911
Test name
Test status
Simulation time 12989382551 ps
CPU time 38.72 seconds
Started Jan 21 08:43:04 PM PST 24
Finished Jan 21 08:43:43 PM PST 24
Peak memory 220648 kb
Host smart-ffb1706f-98ab-47ed-9a57-053afb1a4e0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230096305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.3230096305
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.2101078600
Short name T459
Test name
Test status
Simulation time 8070777574 ps
CPU time 35.26 seconds
Started Jan 21 08:43:06 PM PST 24
Finished Jan 21 08:43:42 PM PST 24
Peak memory 576608 kb
Host smart-44f32834-3e82-43ab-b5b6-728cbd2c15ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101078600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.2101078600
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.2494587162
Short name T895
Test name
Test status
Simulation time 2444200053 ps
CPU time 5.2 seconds
Started Jan 21 08:43:06 PM PST 24
Finished Jan 21 08:43:11 PM PST 24
Peak memory 202628 kb
Host smart-6bc06ad4-e907-4d28-a067-6860085f0ca3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494587162 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.2494587162
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_tx_ovf.1976127232
Short name T774
Test name
Test status
Simulation time 20253144643 ps
CPU time 80.47 seconds
Started Jan 21 08:43:06 PM PST 24
Finished Jan 21 08:44:27 PM PST 24
Peak memory 307004 kb
Host smart-bd740f6a-6fcd-4fe8-93db-110696ebaca3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976127232 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_tx_ovf.1976127232
Directory /workspace/46.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/46.i2c_target_unexp_stop.3755675229
Short name T1076
Test name
Test status
Simulation time 8373150977 ps
CPU time 7.49 seconds
Started Jan 21 08:43:07 PM PST 24
Finished Jan 21 08:43:15 PM PST 24
Peak memory 202648 kb
Host smart-0f016dcf-4d5f-4300-a41c-285e997fea95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755675229 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.i2c_target_unexp_stop.3755675229
Directory /workspace/46.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/47.i2c_alert_test.4121428804
Short name T1463
Test name
Test status
Simulation time 18164128 ps
CPU time 0.63 seconds
Started Jan 21 09:02:53 PM PST 24
Finished Jan 21 09:03:00 PM PST 24
Peak memory 201096 kb
Host smart-aed2da9f-4644-4476-b3af-46df24a7c904
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121428804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.4121428804
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.1010075836
Short name T804
Test name
Test status
Simulation time 165369283 ps
CPU time 1.24 seconds
Started Jan 21 08:43:30 PM PST 24
Finished Jan 21 08:43:31 PM PST 24
Peak memory 210744 kb
Host smart-aa3d2afe-dfae-41b1-9201-d14385bb5580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010075836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.1010075836
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.596667263
Short name T1068
Test name
Test status
Simulation time 1153143753 ps
CPU time 14.75 seconds
Started Jan 21 08:43:21 PM PST 24
Finished Jan 21 08:43:36 PM PST 24
Peak memory 258104 kb
Host smart-a4985ffa-134d-4a53-9af6-76030faf390d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596667263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empt
y.596667263
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.2486404061
Short name T520
Test name
Test status
Simulation time 14426133476 ps
CPU time 349.56 seconds
Started Jan 21 08:43:30 PM PST 24
Finished Jan 21 08:49:20 PM PST 24
Peak memory 1065392 kb
Host smart-43545b8d-a066-4970-b654-e26faa76378b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486404061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.2486404061
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.1101230437
Short name T246
Test name
Test status
Simulation time 6644890608 ps
CPU time 525.17 seconds
Started Jan 21 08:43:21 PM PST 24
Finished Jan 21 08:52:07 PM PST 24
Peak memory 1212452 kb
Host smart-d696a0bc-75ad-43ea-baa9-b36dfcfb1d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101230437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.1101230437
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.3299213994
Short name T734
Test name
Test status
Simulation time 436205258 ps
CPU time 1.09 seconds
Started Jan 21 08:43:22 PM PST 24
Finished Jan 21 08:43:24 PM PST 24
Peak memory 202308 kb
Host smart-6f140ebb-c327-4af2-aca5-a5ba997e9c61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299213994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.3299213994
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.3197032551
Short name T1382
Test name
Test status
Simulation time 329319370 ps
CPU time 9.24 seconds
Started Jan 21 08:43:22 PM PST 24
Finished Jan 21 08:43:32 PM PST 24
Peak memory 202764 kb
Host smart-0f488357-de8a-430c-b96c-2c296e9c0f2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197032551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.3197032551
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.392319344
Short name T1334
Test name
Test status
Simulation time 26928397756 ps
CPU time 419.35 seconds
Started Jan 21 08:43:19 PM PST 24
Finished Jan 21 08:50:19 PM PST 24
Peak memory 1711896 kb
Host smart-e4b995c7-3965-4740-b89c-300ff66291ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392319344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.392319344
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.2851227419
Short name T60
Test name
Test status
Simulation time 7321996793 ps
CPU time 98.87 seconds
Started Jan 21 09:04:15 PM PST 24
Finished Jan 21 09:06:03 PM PST 24
Peak memory 227948 kb
Host smart-8d04f041-e21d-4573-a90a-d0512d4333d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851227419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.2851227419
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.4073531260
Short name T1441
Test name
Test status
Simulation time 17419106 ps
CPU time 0.71 seconds
Started Jan 21 08:43:22 PM PST 24
Finished Jan 21 08:43:23 PM PST 24
Peak memory 201436 kb
Host smart-23f9a830-6173-4877-b3b3-1e83a148c110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073531260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.4073531260
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.2317190317
Short name T1432
Test name
Test status
Simulation time 12696632772 ps
CPU time 621.97 seconds
Started Jan 21 08:43:30 PM PST 24
Finished Jan 21 08:53:52 PM PST 24
Peak memory 202576 kb
Host smart-12cff5c4-a7c6-4223-8215-07f8d0748297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317190317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.2317190317
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_rx_oversample.289118598
Short name T936
Test name
Test status
Simulation time 3017805451 ps
CPU time 119.93 seconds
Started Jan 21 08:43:20 PM PST 24
Finished Jan 21 08:45:21 PM PST 24
Peak memory 356108 kb
Host smart-20bb55a2-7a80-430b-a7fa-e45140f867ce
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289118598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_rx_oversample.
289118598
Directory /workspace/47.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.849033027
Short name T340
Test name
Test status
Simulation time 16289794197 ps
CPU time 76.81 seconds
Started Jan 21 08:43:24 PM PST 24
Finished Jan 21 08:44:41 PM PST 24
Peak memory 308192 kb
Host smart-d0e481ca-7c4a-49b3-8809-af1fed4cf574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849033027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.849033027
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.2972043808
Short name T1439
Test name
Test status
Simulation time 7443013760 ps
CPU time 1067.55 seconds
Started Jan 21 08:43:45 PM PST 24
Finished Jan 21 09:01:34 PM PST 24
Peak memory 1493568 kb
Host smart-7136d5c5-588a-4360-ac91-7e4261de3438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972043808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.2972043808
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.544266642
Short name T1002
Test name
Test status
Simulation time 1430955790 ps
CPU time 10.92 seconds
Started Jan 21 08:43:30 PM PST 24
Finished Jan 21 08:43:42 PM PST 24
Peak memory 210888 kb
Host smart-42504f63-335a-4b15-91ee-5a670d142998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544266642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.544266642
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.2494404481
Short name T1292
Test name
Test status
Simulation time 7880176575 ps
CPU time 6.52 seconds
Started Jan 21 08:43:50 PM PST 24
Finished Jan 21 08:44:00 PM PST 24
Peak memory 202580 kb
Host smart-a3ba6779-6d90-4de5-98fa-8a8f3d8214e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494404481 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.2494404481
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.2401189578
Short name T1295
Test name
Test status
Simulation time 10687897891 ps
CPU time 10.79 seconds
Started Jan 21 08:53:39 PM PST 24
Finished Jan 21 08:54:08 PM PST 24
Peak memory 270876 kb
Host smart-977df351-e4ca-448d-9578-12d8e40b72ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401189578 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.2401189578
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.1055161481
Short name T1398
Test name
Test status
Simulation time 10033248248 ps
CPU time 71.17 seconds
Started Jan 21 09:33:02 PM PST 24
Finished Jan 21 09:34:22 PM PST 24
Peak memory 620852 kb
Host smart-9ee1fe2a-1981-4702-bf36-e8e63be52334
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055161481 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.1055161481
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.3395960363
Short name T826
Test name
Test status
Simulation time 572531837 ps
CPU time 2.87 seconds
Started Jan 21 08:43:50 PM PST 24
Finished Jan 21 08:43:56 PM PST 24
Peak memory 202620 kb
Host smart-cf579566-8719-4cb3-9ff4-d0debfcfdf42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395960363 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.3395960363
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.3453065028
Short name T538
Test name
Test status
Simulation time 7228646542 ps
CPU time 5.01 seconds
Started Jan 21 08:43:36 PM PST 24
Finished Jan 21 08:43:42 PM PST 24
Peak memory 202644 kb
Host smart-7563c5d9-f7d9-4144-af73-53cfdb029d13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453065028 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.3453065028
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.961565895
Short name T379
Test name
Test status
Simulation time 16432738537 ps
CPU time 372.69 seconds
Started Jan 21 08:43:35 PM PST 24
Finished Jan 21 08:49:49 PM PST 24
Peak memory 2741724 kb
Host smart-6353f0b0-6aea-4bad-aa95-757f63073942
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961565895 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.961565895
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_perf.3490911202
Short name T1278
Test name
Test status
Simulation time 478931805 ps
CPU time 3.05 seconds
Started Jan 21 08:43:52 PM PST 24
Finished Jan 21 08:43:57 PM PST 24
Peak memory 202500 kb
Host smart-f6a0de4f-e867-46f5-9c7e-fde26bb72f1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490911202 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_perf.3490911202
Directory /workspace/47.i2c_target_perf/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.1203173067
Short name T108
Test name
Test status
Simulation time 13838399736 ps
CPU time 55.32 seconds
Started Jan 21 08:43:39 PM PST 24
Finished Jan 21 08:44:35 PM PST 24
Peak memory 202580 kb
Host smart-dbca95a6-97c0-49d8-abe1-807b11cf257c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203173067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.1203173067
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_all.2559421291
Short name T163
Test name
Test status
Simulation time 38454931607 ps
CPU time 437.5 seconds
Started Jan 21 08:43:51 PM PST 24
Finished Jan 21 08:51:11 PM PST 24
Peak memory 506312 kb
Host smart-f8d6b7f5-d88a-4288-b230-e11e40a3a196
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559421291 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_target_stress_all.2559421291
Directory /workspace/47.i2c_target_stress_all/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.842422706
Short name T687
Test name
Test status
Simulation time 334222249 ps
CPU time 6.09 seconds
Started Jan 21 08:43:36 PM PST 24
Finished Jan 21 08:43:43 PM PST 24
Peak memory 202600 kb
Host smart-b76bcc2e-55b3-41ef-8949-e5e4a7760c4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842422706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_rd.842422706
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.4128552027
Short name T588
Test name
Test status
Simulation time 16608426038 ps
CPU time 83.49 seconds
Started Jan 21 08:43:38 PM PST 24
Finished Jan 21 08:45:02 PM PST 24
Peak memory 980656 kb
Host smart-b027737f-0b24-4d26-8f7d-160d1437bd10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128552027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.4128552027
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.1147716601
Short name T595
Test name
Test status
Simulation time 2082883190 ps
CPU time 7.98 seconds
Started Jan 21 08:43:46 PM PST 24
Finished Jan 21 08:43:55 PM PST 24
Peak memory 207368 kb
Host smart-edeeea33-0a37-4434-bd28-328f521036d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147716601 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.1147716601
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_ovf.1275190707
Short name T1112
Test name
Test status
Simulation time 11387186253 ps
CPU time 114.53 seconds
Started Jan 21 08:43:36 PM PST 24
Finished Jan 21 08:45:31 PM PST 24
Peak memory 324856 kb
Host smart-4214c90c-05c0-41b0-b96a-6ff7c039f17b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275190707 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_tx_ovf.1275190707
Directory /workspace/47.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/47.i2c_target_unexp_stop.2958067843
Short name T1361
Test name
Test status
Simulation time 1969940234 ps
CPU time 8.83 seconds
Started Jan 21 08:43:43 PM PST 24
Finished Jan 21 08:43:53 PM PST 24
Peak memory 202556 kb
Host smart-8bcb509d-8d94-4c9e-9ad3-9191ad25c08c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958067843 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.i2c_target_unexp_stop.2958067843
Directory /workspace/47.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/48.i2c_alert_test.2497024545
Short name T1267
Test name
Test status
Simulation time 34011484 ps
CPU time 0.61 seconds
Started Jan 21 08:44:30 PM PST 24
Finished Jan 21 08:44:32 PM PST 24
Peak memory 201332 kb
Host smart-25049e27-8d1c-4ebe-8a78-0bede3302590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497024545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.2497024545
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.1838817117
Short name T52
Test name
Test status
Simulation time 164395723 ps
CPU time 1.46 seconds
Started Jan 21 08:44:07 PM PST 24
Finished Jan 21 08:44:14 PM PST 24
Peak memory 210696 kb
Host smart-514b7e4c-6d70-4912-931e-f16393d6e16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838817117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.1838817117
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.1731377098
Short name T292
Test name
Test status
Simulation time 2769563066 ps
CPU time 11.23 seconds
Started Jan 21 08:44:07 PM PST 24
Finished Jan 21 08:44:24 PM PST 24
Peak memory 310664 kb
Host smart-836a34c9-e42d-431b-9ad8-095e9e0378b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731377098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.1731377098
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.2310833353
Short name T332
Test name
Test status
Simulation time 2024942418 ps
CPU time 69.27 seconds
Started Jan 21 08:44:07 PM PST 24
Finished Jan 21 08:45:22 PM PST 24
Peak memory 700692 kb
Host smart-94423c66-7280-42b1-8135-ae8377aae1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310833353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.2310833353
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.3759071040
Short name T282
Test name
Test status
Simulation time 8168958275 ps
CPU time 405.65 seconds
Started Jan 21 08:43:57 PM PST 24
Finished Jan 21 08:50:43 PM PST 24
Peak memory 1062120 kb
Host smart-8999c209-927b-49a0-bdb5-7f0d61ac7120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759071040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.3759071040
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.1386418618
Short name T240
Test name
Test status
Simulation time 388935245 ps
CPU time 1 seconds
Started Jan 21 08:43:59 PM PST 24
Finished Jan 21 08:44:02 PM PST 24
Peak memory 202468 kb
Host smart-ebd843e3-491f-45c3-9c99-9bf645dc222b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386418618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.1386418618
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.1752022551
Short name T762
Test name
Test status
Simulation time 182342667 ps
CPU time 4.66 seconds
Started Jan 21 08:44:08 PM PST 24
Finished Jan 21 08:44:18 PM PST 24
Peak memory 234536 kb
Host smart-9a8f1d6b-da14-4043-aa79-2a24afa3a73e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752022551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.1752022551
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.149023300
Short name T314
Test name
Test status
Simulation time 72449215066 ps
CPU time 745.36 seconds
Started Jan 21 08:43:59 PM PST 24
Finished Jan 21 08:56:26 PM PST 24
Peak memory 1644780 kb
Host smart-e968ff8e-cedf-4c41-be23-d9c5e6b301a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149023300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.149023300
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.1396360679
Short name T1386
Test name
Test status
Simulation time 2458852264 ps
CPU time 88.06 seconds
Started Jan 21 08:44:32 PM PST 24
Finished Jan 21 08:46:00 PM PST 24
Peak memory 309632 kb
Host smart-559b2065-2eba-43b2-9807-2f8a6757f158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396360679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.1396360679
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.1592477916
Short name T1521
Test name
Test status
Simulation time 21542513 ps
CPU time 0.67 seconds
Started Jan 21 08:44:00 PM PST 24
Finished Jan 21 08:44:06 PM PST 24
Peak memory 201472 kb
Host smart-e79db584-1a2c-43ae-8297-cb8f9650cd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592477916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.1592477916
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.1732104197
Short name T1514
Test name
Test status
Simulation time 4722045226 ps
CPU time 243.87 seconds
Started Jan 21 08:44:11 PM PST 24
Finished Jan 21 08:48:20 PM PST 24
Peak memory 218928 kb
Host smart-40fc0b1c-c319-44a7-938b-98630d4c3918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732104197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.1732104197
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_rx_oversample.1900250659
Short name T1310
Test name
Test status
Simulation time 8028234655 ps
CPU time 97.99 seconds
Started Jan 21 08:43:57 PM PST 24
Finished Jan 21 08:45:36 PM PST 24
Peak memory 332396 kb
Host smart-df09497c-3543-4177-81ad-b2bbeb3f57cf
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900250659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_rx_oversample
.1900250659
Directory /workspace/48.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.627202166
Short name T821
Test name
Test status
Simulation time 1564170872 ps
CPU time 96.88 seconds
Started Jan 21 08:44:00 PM PST 24
Finished Jan 21 08:45:39 PM PST 24
Peak memory 244768 kb
Host smart-ce775c5e-3c03-48e6-9062-a145ff2018fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627202166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.627202166
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.1660988820
Short name T1510
Test name
Test status
Simulation time 168211786071 ps
CPU time 840.28 seconds
Started Jan 21 08:44:15 PM PST 24
Finished Jan 21 08:58:17 PM PST 24
Peak memory 2550276 kb
Host smart-80149396-b5be-40db-92c2-73afd2d45357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660988820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.1660988820
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.4005327459
Short name T585
Test name
Test status
Simulation time 2755353905 ps
CPU time 13.38 seconds
Started Jan 21 08:44:11 PM PST 24
Finished Jan 21 08:44:29 PM PST 24
Peak memory 212852 kb
Host smart-50250370-6fbf-4b63-9114-3c6a8b57c39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005327459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.4005327459
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.2895834773
Short name T388
Test name
Test status
Simulation time 3323810688 ps
CPU time 3.94 seconds
Started Jan 21 08:44:23 PM PST 24
Finished Jan 21 08:44:28 PM PST 24
Peak memory 202564 kb
Host smart-f1f6cf83-7bbe-4c51-80b0-1eca9947a436
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895834773 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.2895834773
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.787219341
Short name T1022
Test name
Test status
Simulation time 10268943792 ps
CPU time 14.82 seconds
Started Jan 21 09:35:00 PM PST 24
Finished Jan 21 09:35:22 PM PST 24
Peak memory 275316 kb
Host smart-a717ef40-63df-4b11-b9a7-66ddd71823a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787219341 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_acq.787219341
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.3086991015
Short name T593
Test name
Test status
Simulation time 10120557531 ps
CPU time 14.83 seconds
Started Jan 21 08:44:23 PM PST 24
Finished Jan 21 08:44:39 PM PST 24
Peak memory 281752 kb
Host smart-a6bcc8cf-7cfa-446c-95e2-1ee2cabd08f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086991015 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.3086991015
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.3428094102
Short name T920
Test name
Test status
Simulation time 664226199 ps
CPU time 3.13 seconds
Started Jan 21 09:39:10 PM PST 24
Finished Jan 21 09:39:24 PM PST 24
Peak memory 202324 kb
Host smart-dd1a1ae6-a9f8-42e1-bb56-15729dbb6af8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428094102 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.3428094102
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.2301290766
Short name T1086
Test name
Test status
Simulation time 1091239868 ps
CPU time 5.12 seconds
Started Jan 21 08:44:16 PM PST 24
Finished Jan 21 08:44:22 PM PST 24
Peak memory 206624 kb
Host smart-7c5ccce5-9faa-450c-8735-d2f8430e6cca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301290766 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.2301290766
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.1688028170
Short name T1462
Test name
Test status
Simulation time 4146315044 ps
CPU time 5.8 seconds
Started Jan 21 10:05:22 PM PST 24
Finished Jan 21 10:05:32 PM PST 24
Peak memory 289372 kb
Host smart-22d4d578-3793-424d-b182-0d4862c69790
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688028170 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.1688028170
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_perf.3085945041
Short name T501
Test name
Test status
Simulation time 4022996635 ps
CPU time 5.8 seconds
Started Jan 21 08:58:40 PM PST 24
Finished Jan 21 08:59:15 PM PST 24
Peak memory 215560 kb
Host smart-f03940dc-785c-4a84-ae19-c6efb7d2309f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085945041 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_perf.3085945041
Directory /workspace/48.i2c_target_perf/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.2798569001
Short name T758
Test name
Test status
Simulation time 1352336712 ps
CPU time 16.14 seconds
Started Jan 21 08:44:17 PM PST 24
Finished Jan 21 08:44:34 PM PST 24
Peak memory 202548 kb
Host smart-ce10fc78-a123-4494-8c25-69044b7e16d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798569001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.2798569001
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.2141566086
Short name T196
Test name
Test status
Simulation time 2388474999 ps
CPU time 30.04 seconds
Started Jan 21 09:27:05 PM PST 24
Finished Jan 21 09:27:44 PM PST 24
Peak memory 202644 kb
Host smart-9b27786b-0a6f-4da3-95f1-61ab54ca38cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141566086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.2141566086
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.4168298826
Short name T1253
Test name
Test status
Simulation time 53988794776 ps
CPU time 1202.85 seconds
Started Jan 21 08:44:21 PM PST 24
Finished Jan 21 09:04:25 PM PST 24
Peak memory 6110212 kb
Host smart-01c0097c-639f-4c63-8e43-3dbc3eef6787
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168298826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.4168298826
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.903124263
Short name T1395
Test name
Test status
Simulation time 35400137428 ps
CPU time 615.62 seconds
Started Jan 21 08:44:14 PM PST 24
Finished Jan 21 08:54:32 PM PST 24
Peak memory 1596548 kb
Host smart-40cf16dd-36b4-4f9b-b148-9930e2dc6a99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903124263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_t
arget_stretch.903124263
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.3616432495
Short name T224
Test name
Test status
Simulation time 7287045196 ps
CPU time 7.44 seconds
Started Jan 21 08:44:17 PM PST 24
Finished Jan 21 08:44:25 PM PST 24
Peak memory 206892 kb
Host smart-cbb1afff-db18-4668-a728-c9228c980a0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616432495 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.3616432495
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_tx_ovf.1541700582
Short name T913
Test name
Test status
Simulation time 2059473102 ps
CPU time 58.27 seconds
Started Jan 21 08:44:14 PM PST 24
Finished Jan 21 08:45:15 PM PST 24
Peak memory 281608 kb
Host smart-0713d17b-ba73-48e1-9473-c37d307452ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541700582 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_tx_ovf.1541700582
Directory /workspace/48.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/48.i2c_target_unexp_stop.198700759
Short name T736
Test name
Test status
Simulation time 2160542446 ps
CPU time 9.14 seconds
Started Jan 21 09:03:44 PM PST 24
Finished Jan 21 09:04:09 PM PST 24
Peak memory 202884 kb
Host smart-5eb1c297-6fbe-43ec-b913-0c3dcbe05efe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198700759 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_unexp_stop.198700759
Directory /workspace/48.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/49.i2c_alert_test.3247412366
Short name T274
Test name
Test status
Simulation time 203213057 ps
CPU time 0.6 seconds
Started Jan 21 08:45:14 PM PST 24
Finished Jan 21 08:45:17 PM PST 24
Peak memory 201984 kb
Host smart-8923963b-495e-4ee1-9a39-94a013fc66a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247412366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.3247412366
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.894222755
Short name T822
Test name
Test status
Simulation time 190647651 ps
CPU time 1.52 seconds
Started Jan 21 09:12:13 PM PST 24
Finished Jan 21 09:12:18 PM PST 24
Peak memory 214824 kb
Host smart-a80fb913-bf1f-4cc7-ba9a-91eb43d04254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894222755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.894222755
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.499425454
Short name T1352
Test name
Test status
Simulation time 894288210 ps
CPU time 25.07 seconds
Started Jan 21 08:53:27 PM PST 24
Finished Jan 21 08:54:10 PM PST 24
Peak memory 298688 kb
Host smart-18637d95-9f21-4d6d-b827-b39d518bcbdd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499425454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empt
y.499425454
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.2958790539
Short name T882
Test name
Test status
Simulation time 8389415860 ps
CPU time 41.41 seconds
Started Jan 21 08:44:36 PM PST 24
Finished Jan 21 08:45:18 PM PST 24
Peak memory 273548 kb
Host smart-955a427b-cce2-4ef8-bf7f-487a395d17c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958790539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.2958790539
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.1667902473
Short name T591
Test name
Test status
Simulation time 8166802149 ps
CPU time 472.1 seconds
Started Jan 21 08:44:29 PM PST 24
Finished Jan 21 08:52:22 PM PST 24
Peak memory 1179884 kb
Host smart-ef779893-7b4b-4cc2-83f8-36334ce21653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667902473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.1667902473
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.3415238465
Short name T1111
Test name
Test status
Simulation time 69694269 ps
CPU time 0.85 seconds
Started Jan 21 08:44:44 PM PST 24
Finished Jan 21 08:44:45 PM PST 24
Peak memory 202280 kb
Host smart-534a1707-8891-4729-bc71-46270b311d42
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415238465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.3415238465
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.2840214879
Short name T1419
Test name
Test status
Simulation time 2547854163 ps
CPU time 3.89 seconds
Started Jan 21 08:44:42 PM PST 24
Finished Jan 21 08:44:46 PM PST 24
Peak memory 202544 kb
Host smart-dc6c8d3e-cd86-4949-9335-99a772772889
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840214879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.2840214879
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.1249531256
Short name T1266
Test name
Test status
Simulation time 3696162351 ps
CPU time 201.03 seconds
Started Jan 21 08:45:14 PM PST 24
Finished Jan 21 08:48:38 PM PST 24
Peak memory 292032 kb
Host smart-4d1c44d0-fbe6-4a34-9eb2-f30d68688c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249531256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.1249531256
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.1499014719
Short name T5
Test name
Test status
Simulation time 51269728 ps
CPU time 0.69 seconds
Started Jan 21 08:44:30 PM PST 24
Finished Jan 21 08:44:31 PM PST 24
Peak memory 201488 kb
Host smart-2f399b14-3b8f-4204-97ea-bdbd3f52ca91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499014719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1499014719
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.2263709172
Short name T803
Test name
Test status
Simulation time 2758972303 ps
CPU time 125.62 seconds
Started Jan 21 08:44:47 PM PST 24
Finished Jan 21 08:46:53 PM PST 24
Peak memory 223052 kb
Host smart-590b704c-915d-4e49-9252-beb93b2ee4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263709172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.2263709172
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_rx_oversample.4255774882
Short name T382
Test name
Test status
Simulation time 1682816097 ps
CPU time 73.24 seconds
Started Jan 21 08:44:29 PM PST 24
Finished Jan 21 08:45:42 PM PST 24
Peak memory 300384 kb
Host smart-0a14175c-c1aa-4f00-a711-ec91040822d6
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255774882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_rx_oversample
.4255774882
Directory /workspace/49.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.3736764016
Short name T766
Test name
Test status
Simulation time 6534253317 ps
CPU time 105.78 seconds
Started Jan 21 08:44:29 PM PST 24
Finished Jan 21 08:46:16 PM PST 24
Peak memory 243392 kb
Host smart-31f3e8fa-5364-421a-86cc-4f42cd4ca182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736764016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.3736764016
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.2945576249
Short name T189
Test name
Test status
Simulation time 15599593156 ps
CPU time 1186.81 seconds
Started Jan 21 08:44:46 PM PST 24
Finished Jan 21 09:04:34 PM PST 24
Peak memory 1238028 kb
Host smart-4bec8e87-4c54-4f42-a358-b10e1a3c513b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945576249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.2945576249
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.2919724912
Short name T1512
Test name
Test status
Simulation time 1108866591 ps
CPU time 40.62 seconds
Started Jan 21 08:44:47 PM PST 24
Finished Jan 21 08:45:28 PM PST 24
Peak memory 210684 kb
Host smart-b0361965-d203-4a3f-a046-5b9c0072e005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919724912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.2919724912
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.3992838794
Short name T217
Test name
Test status
Simulation time 903900309 ps
CPU time 3.73 seconds
Started Jan 21 08:45:18 PM PST 24
Finished Jan 21 08:45:27 PM PST 24
Peak memory 202516 kb
Host smart-a009542d-0f54-4a53-8e3c-db0a4b9dfb46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992838794 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.3992838794
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.1602046529
Short name T1052
Test name
Test status
Simulation time 10068555887 ps
CPU time 54.11 seconds
Started Jan 21 08:45:02 PM PST 24
Finished Jan 21 08:45:57 PM PST 24
Peak memory 492484 kb
Host smart-5a7f3bc1-17f9-4fa2-8ed4-6d0004f05d23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602046529 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.1602046529
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.2398272569
Short name T1270
Test name
Test status
Simulation time 10055359316 ps
CPU time 41.58 seconds
Started Jan 21 08:45:05 PM PST 24
Finished Jan 21 08:45:48 PM PST 24
Peak memory 424076 kb
Host smart-dd616345-7f03-41f4-a756-cc066ba29907
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398272569 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.2398272569
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.1071473420
Short name T1335
Test name
Test status
Simulation time 1933295655 ps
CPU time 2.71 seconds
Started Jan 21 08:45:10 PM PST 24
Finished Jan 21 08:45:16 PM PST 24
Peak memory 202664 kb
Host smart-ba7462dd-f981-4967-8ab4-74f3e735a36e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071473420 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.1071473420
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.1804495919
Short name T724
Test name
Test status
Simulation time 3287670819 ps
CPU time 6.38 seconds
Started Jan 21 09:04:15 PM PST 24
Finished Jan 21 09:04:32 PM PST 24
Peak memory 202644 kb
Host smart-86c1fb7c-a370-459f-b67c-cc47cb046a6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804495919 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.1804495919
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.3076247309
Short name T1039
Test name
Test status
Simulation time 13053656869 ps
CPU time 358.51 seconds
Started Jan 21 08:44:59 PM PST 24
Finished Jan 21 08:50:58 PM PST 24
Peak memory 2952816 kb
Host smart-2c579f86-31c2-4971-b6f9-0564e12eddfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076247309 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.3076247309
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_perf.1263263520
Short name T783
Test name
Test status
Simulation time 8049530644 ps
CPU time 3.4 seconds
Started Jan 21 08:45:04 PM PST 24
Finished Jan 21 08:45:08 PM PST 24
Peak memory 202836 kb
Host smart-684f79e7-9639-4aef-afd6-a6dfdeaab2c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263263520 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_perf.1263263520
Directory /workspace/49.i2c_target_perf/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.3346849262
Short name T1177
Test name
Test status
Simulation time 2839713385 ps
CPU time 18.05 seconds
Started Jan 21 08:44:48 PM PST 24
Finished Jan 21 08:45:06 PM PST 24
Peak memory 202608 kb
Host smart-3db4d3d0-9dab-462f-a5e0-293dbb047548
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346849262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.3346849262
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.143800120
Short name T231
Test name
Test status
Simulation time 993811626 ps
CPU time 39.72 seconds
Started Jan 21 08:44:53 PM PST 24
Finished Jan 21 08:45:34 PM PST 24
Peak memory 202536 kb
Host smart-ca388e5d-bb20-4d8d-9118-2407756d88eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143800120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c
_target_stress_rd.143800120
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.3651238371
Short name T702
Test name
Test status
Simulation time 14123065398 ps
CPU time 63.83 seconds
Started Jan 21 08:44:46 PM PST 24
Finished Jan 21 08:45:51 PM PST 24
Peak memory 1269236 kb
Host smart-a8a66660-6220-48d9-9483-72dc169463bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651238371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.3651238371
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.876904764
Short name T441
Test name
Test status
Simulation time 23321491971 ps
CPU time 186.18 seconds
Started Jan 21 08:44:50 PM PST 24
Finished Jan 21 08:47:57 PM PST 24
Peak memory 1452500 kb
Host smart-6273191e-5004-413c-9417-a8ad481d8466
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876904764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_t
arget_stretch.876904764
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.1586969135
Short name T1365
Test name
Test status
Simulation time 6714043220 ps
CPU time 8.06 seconds
Started Jan 21 09:08:59 PM PST 24
Finished Jan 21 09:09:16 PM PST 24
Peak memory 206096 kb
Host smart-da52dd18-9ff3-44b8-8cd4-435d4631e5df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586969135 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.1586969135
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_ovf.3811350586
Short name T1024
Test name
Test status
Simulation time 2596780708 ps
CPU time 51.19 seconds
Started Jan 21 08:45:02 PM PST 24
Finished Jan 21 08:45:54 PM PST 24
Peak memory 220508 kb
Host smart-8739d56b-76a9-48b9-bda7-16aa62fd769b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811350586 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_tx_ovf.3811350586
Directory /workspace/49.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/49.i2c_target_unexp_stop.3707573484
Short name T807
Test name
Test status
Simulation time 6492900645 ps
CPU time 9.24 seconds
Started Jan 21 08:44:59 PM PST 24
Finished Jan 21 08:45:09 PM PST 24
Peak memory 204036 kb
Host smart-2f437736-b144-4fdd-8ee6-aa0df60875c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707573484 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.i2c_target_unexp_stop.3707573484
Directory /workspace/49.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/5.i2c_alert_test.1758937638
Short name T506
Test name
Test status
Simulation time 94185514 ps
CPU time 0.61 seconds
Started Jan 21 08:20:49 PM PST 24
Finished Jan 21 08:20:51 PM PST 24
Peak memory 201096 kb
Host smart-bcc1ff4b-4697-4f07-a687-f684e235aeae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758937638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.1758937638
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.3016857336
Short name T419
Test name
Test status
Simulation time 110644314 ps
CPU time 1.58 seconds
Started Jan 21 08:20:28 PM PST 24
Finished Jan 21 08:20:31 PM PST 24
Peak memory 218880 kb
Host smart-86ebd615-3b87-45fd-b9be-6258859fcc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016857336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.3016857336
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.3195202808
Short name T1319
Test name
Test status
Simulation time 652669005 ps
CPU time 6.41 seconds
Started Jan 21 08:20:23 PM PST 24
Finished Jan 21 08:20:32 PM PST 24
Peak memory 272412 kb
Host smart-ca26fdc8-048d-4820-92f1-a41829894138
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195202808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.3195202808
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.2434231974
Short name T471
Test name
Test status
Simulation time 2216873690 ps
CPU time 163.19 seconds
Started Jan 21 08:20:23 PM PST 24
Finished Jan 21 08:23:08 PM PST 24
Peak memory 693804 kb
Host smart-84f98214-5707-408a-a563-75e790746f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434231974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.2434231974
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.3149465101
Short name T1415
Test name
Test status
Simulation time 4913265990 ps
CPU time 279.39 seconds
Started Jan 21 08:20:20 PM PST 24
Finished Jan 21 08:25:02 PM PST 24
Peak memory 1252032 kb
Host smart-b3dd0842-4ff5-4842-8aac-da04c338baff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149465101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.3149465101
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.1696161747
Short name T513
Test name
Test status
Simulation time 306817199 ps
CPU time 0.89 seconds
Started Jan 21 08:20:20 PM PST 24
Finished Jan 21 08:20:22 PM PST 24
Peak memory 202344 kb
Host smart-cb4018a8-f2f8-4474-9a3d-cdab823fbdc2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696161747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.1696161747
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.3976318916
Short name T739
Test name
Test status
Simulation time 305701977 ps
CPU time 4.82 seconds
Started Jan 21 08:20:21 PM PST 24
Finished Jan 21 08:20:28 PM PST 24
Peak memory 202496 kb
Host smart-9dc41ae0-7923-4218-a6e6-ae1aac8da0ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976318916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
3976318916
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.1941845749
Short name T1152
Test name
Test status
Simulation time 22131246717 ps
CPU time 317.84 seconds
Started Jan 21 08:20:31 PM PST 24
Finished Jan 21 08:25:50 PM PST 24
Peak memory 1614888 kb
Host smart-56d6186a-bdc0-4f8c-ad78-d4f876fe2491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941845749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.1941845749
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.1193538931
Short name T927
Test name
Test status
Simulation time 3442234621 ps
CPU time 84.88 seconds
Started Jan 21 08:20:53 PM PST 24
Finished Jan 21 08:22:19 PM PST 24
Peak memory 227092 kb
Host smart-f57a8a58-4ab7-466a-b994-cd47298f9a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193538931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.1193538931
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.2512499078
Short name T158
Test name
Test status
Simulation time 100515219 ps
CPU time 0.74 seconds
Started Jan 21 08:20:20 PM PST 24
Finished Jan 21 08:20:22 PM PST 24
Peak memory 202188 kb
Host smart-0bf8bcb2-dc06-4afc-98d1-b4319022b8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512499078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.2512499078
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.3858672440
Short name T747
Test name
Test status
Simulation time 13519408098 ps
CPU time 49.87 seconds
Started Jan 21 08:20:32 PM PST 24
Finished Jan 21 08:21:24 PM PST 24
Peak memory 210780 kb
Host smart-bd46748b-2e0d-45fd-ab31-231f9e309eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858672440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.3858672440
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_rx_oversample.4283987164
Short name T773
Test name
Test status
Simulation time 5558156635 ps
CPU time 134.21 seconds
Started Jan 21 08:20:22 PM PST 24
Finished Jan 21 08:22:39 PM PST 24
Peak memory 312984 kb
Host smart-bbc66c94-e824-449d-bc42-1ee6a1e4d5ad
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283987164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_rx_oversample.
4283987164
Directory /workspace/5.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.1771598468
Short name T825
Test name
Test status
Simulation time 4857095394 ps
CPU time 36.61 seconds
Started Jan 21 08:20:28 PM PST 24
Finished Jan 21 08:21:07 PM PST 24
Peak memory 253524 kb
Host smart-3d36fd33-65a9-4db2-a0d3-ab25d6ac5718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771598468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.1771598468
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.3705543924
Short name T715
Test name
Test status
Simulation time 1763562318 ps
CPU time 15.1 seconds
Started Jan 21 08:20:27 PM PST 24
Finished Jan 21 08:20:44 PM PST 24
Peak memory 214896 kb
Host smart-9b2c3f19-81ec-49fa-ad33-3c995582c094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705543924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.3705543924
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.170846871
Short name T17
Test name
Test status
Simulation time 10151214548 ps
CPU time 70.94 seconds
Started Jan 21 08:20:40 PM PST 24
Finished Jan 21 08:21:54 PM PST 24
Peak memory 533748 kb
Host smart-7e137d7f-24fa-42d1-a563-a0875713b23c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170846871 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_acq.170846871
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.2360770116
Short name T243
Test name
Test status
Simulation time 10603933738 ps
CPU time 9.84 seconds
Started Jan 21 08:20:35 PM PST 24
Finished Jan 21 08:20:48 PM PST 24
Peak memory 275236 kb
Host smart-223eec90-79cd-4e52-ab5d-5a19d928c3f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360770116 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.2360770116
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.2433516898
Short name T391
Test name
Test status
Simulation time 477673965 ps
CPU time 2.5 seconds
Started Jan 21 08:20:48 PM PST 24
Finished Jan 21 08:20:52 PM PST 24
Peak memory 202652 kb
Host smart-cb565066-ac68-4ec3-a158-2bb98501b729
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433516898 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.2433516898
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.3548062296
Short name T1135
Test name
Test status
Simulation time 3061415374 ps
CPU time 3.61 seconds
Started Jan 21 08:20:32 PM PST 24
Finished Jan 21 08:20:38 PM PST 24
Peak memory 202616 kb
Host smart-e264673b-44bb-4a33-b1f0-11078770ddd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548062296 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.3548062296
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.1329615828
Short name T877
Test name
Test status
Simulation time 20883903612 ps
CPU time 723.17 seconds
Started Jan 21 08:20:34 PM PST 24
Finished Jan 21 08:32:41 PM PST 24
Peak memory 3740556 kb
Host smart-58fe3d78-7b67-470e-b0f8-aa171fce8f43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329615828 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.1329615828
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_perf.3558259286
Short name T860
Test name
Test status
Simulation time 8002611918 ps
CPU time 6.35 seconds
Started Jan 21 08:20:50 PM PST 24
Finished Jan 21 08:20:58 PM PST 24
Peak memory 202692 kb
Host smart-a089c587-7f95-425a-8226-e86c9e309dcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558259286 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_perf.3558259286
Directory /workspace/5.i2c_target_perf/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.735463556
Short name T1518
Test name
Test status
Simulation time 4609048029 ps
CPU time 15.7 seconds
Started Jan 21 08:20:28 PM PST 24
Finished Jan 21 08:20:46 PM PST 24
Peak memory 202512 kb
Host smart-5ed8a8d4-9916-4f24-be3e-8d61f1a3949a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735463556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_targ
et_smoke.735463556
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_all.595988615
Short name T1373
Test name
Test status
Simulation time 27429324513 ps
CPU time 83.03 seconds
Started Jan 21 09:12:17 PM PST 24
Finished Jan 21 09:13:45 PM PST 24
Peak memory 219100 kb
Host smart-865b2b1c-f5fd-4769-9ccf-992080886f68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595988615 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.i2c_target_stress_all.595988615
Directory /workspace/5.i2c_target_stress_all/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.1254679847
Short name T1435
Test name
Test status
Simulation time 1002689695 ps
CPU time 41.88 seconds
Started Jan 21 08:20:29 PM PST 24
Finished Jan 21 08:21:13 PM PST 24
Peak memory 202544 kb
Host smart-a31c1d69-2bb1-40ff-8f82-f0dc052d9cb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254679847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.1254679847
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.1595708152
Short name T912
Test name
Test status
Simulation time 45684520494 ps
CPU time 2870.57 seconds
Started Jan 21 08:20:29 PM PST 24
Finished Jan 21 09:08:21 PM PST 24
Peak memory 9993532 kb
Host smart-f65896e4-ddb1-4da1-8f23-8ed7a20f0cb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595708152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.1595708152
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.3599251963
Short name T718
Test name
Test status
Simulation time 8524988036 ps
CPU time 112.89 seconds
Started Jan 21 08:20:31 PM PST 24
Finished Jan 21 08:22:26 PM PST 24
Peak memory 612800 kb
Host smart-bc372d0c-2f0e-4d6e-a51c-3fe6ee2cfdb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599251963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.3599251963
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.3014046485
Short name T284
Test name
Test status
Simulation time 41160791947 ps
CPU time 8.54 seconds
Started Jan 21 09:01:33 PM PST 24
Finished Jan 21 09:02:00 PM PST 24
Peak memory 216040 kb
Host smart-9819a751-12fc-4fb0-bdb0-cdfd585a6e4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014046485 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.3014046485
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_ovf.3099085468
Short name T1342
Test name
Test status
Simulation time 2791893304 ps
CPU time 56.44 seconds
Started Jan 21 08:20:36 PM PST 24
Finished Jan 21 08:21:37 PM PST 24
Peak memory 223824 kb
Host smart-35b5f887-a342-45ea-9ce8-68edf404cbc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099085468 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_tx_ovf.3099085468
Directory /workspace/5.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/5.i2c_target_unexp_stop.1072748871
Short name T1109
Test name
Test status
Simulation time 11125269263 ps
CPU time 6.18 seconds
Started Jan 21 08:20:37 PM PST 24
Finished Jan 21 08:20:47 PM PST 24
Peak memory 209324 kb
Host smart-cb24fcf9-3298-4a7d-ba44-dba20c90603e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072748871 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.i2c_target_unexp_stop.1072748871
Directory /workspace/5.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/6.i2c_alert_test.1915881009
Short name T1350
Test name
Test status
Simulation time 26903940 ps
CPU time 0.62 seconds
Started Jan 21 08:21:21 PM PST 24
Finished Jan 21 08:21:23 PM PST 24
Peak memory 201972 kb
Host smart-2bf9ef39-4447-4ea1-83cf-3272ac319022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915881009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.1915881009
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.1029666698
Short name T1113
Test name
Test status
Simulation time 75228077 ps
CPU time 1 seconds
Started Jan 21 08:20:58 PM PST 24
Finished Jan 21 08:21:00 PM PST 24
Peak memory 202536 kb
Host smart-90debda4-fcfc-4388-9ebc-7a0c9b414f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029666698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.1029666698
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.957278934
Short name T781
Test name
Test status
Simulation time 201632305 ps
CPU time 3.87 seconds
Started Jan 21 08:20:55 PM PST 24
Finished Jan 21 08:21:00 PM PST 24
Peak memory 231924 kb
Host smart-3f7ba70d-7b42-4ad2-90dd-b7ede21b5ef3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957278934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty
.957278934
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.3862716197
Short name T1360
Test name
Test status
Simulation time 2516466440 ps
CPU time 104 seconds
Started Jan 21 08:20:58 PM PST 24
Finished Jan 21 08:22:43 PM PST 24
Peak memory 803344 kb
Host smart-36a6798f-0abf-4cc0-890f-0940d1b5238c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862716197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.3862716197
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.2763468377
Short name T251
Test name
Test status
Simulation time 13807238469 ps
CPU time 546.52 seconds
Started Jan 21 08:20:50 PM PST 24
Finished Jan 21 08:29:58 PM PST 24
Peak memory 1759124 kb
Host smart-724912d5-f474-4d55-9630-15a5edd85e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763468377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.2763468377
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.1063415465
Short name T1232
Test name
Test status
Simulation time 351499109 ps
CPU time 0.93 seconds
Started Jan 21 08:20:50 PM PST 24
Finished Jan 21 08:20:52 PM PST 24
Peak memory 202336 kb
Host smart-42073daf-a3bb-47d0-acf3-7abd268d9131
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063415465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.1063415465
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.4202721710
Short name T1018
Test name
Test status
Simulation time 534810024 ps
CPU time 9.78 seconds
Started Jan 21 08:20:55 PM PST 24
Finished Jan 21 08:21:05 PM PST 24
Peak memory 202508 kb
Host smart-7d831a1f-5a80-4729-9570-52f0a087f8b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202721710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
4202721710
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.3532150011
Short name T182
Test name
Test status
Simulation time 78917120274 ps
CPU time 826.99 seconds
Started Jan 21 08:20:52 PM PST 24
Finished Jan 21 08:34:40 PM PST 24
Peak memory 1769552 kb
Host smart-fe4422f0-86ec-457a-8875-6d1225cc8219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532150011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.3532150011
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.240036096
Short name T812
Test name
Test status
Simulation time 1803325653 ps
CPU time 39.24 seconds
Started Jan 21 08:21:14 PM PST 24
Finished Jan 21 08:21:54 PM PST 24
Peak memory 264984 kb
Host smart-3428f4cb-e746-4a6b-8eec-4cae009837cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240036096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.240036096
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.2994514859
Short name T279
Test name
Test status
Simulation time 18644248 ps
CPU time 0.66 seconds
Started Jan 21 08:20:52 PM PST 24
Finished Jan 21 08:20:53 PM PST 24
Peak memory 202196 kb
Host smart-c4fd96bc-ce49-49c3-8fd8-f2ee4b818985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994514859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.2994514859
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.588645439
Short name T862
Test name
Test status
Simulation time 12376098083 ps
CPU time 246.93 seconds
Started Jan 21 08:20:58 PM PST 24
Finished Jan 21 08:25:06 PM PST 24
Peak memory 218496 kb
Host smart-9d71223a-d0b7-4413-a981-24ff95384d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588645439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.588645439
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_rx_oversample.1877288983
Short name T1064
Test name
Test status
Simulation time 6385867957 ps
CPU time 145.84 seconds
Started Jan 21 08:20:47 PM PST 24
Finished Jan 21 08:23:14 PM PST 24
Peak memory 267764 kb
Host smart-64f35857-877c-48e3-87c7-886b16032b48
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877288983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_rx_oversample.
1877288983
Directory /workspace/6.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.132856131
Short name T980
Test name
Test status
Simulation time 5597341100 ps
CPU time 132.97 seconds
Started Jan 21 08:20:46 PM PST 24
Finished Jan 21 08:23:00 PM PST 24
Peak memory 231564 kb
Host smart-63259567-a40b-4966-80fe-864fc2816005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132856131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.132856131
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.1170272806
Short name T451
Test name
Test status
Simulation time 8360953490 ps
CPU time 1119.57 seconds
Started Jan 21 08:21:08 PM PST 24
Finished Jan 21 08:39:49 PM PST 24
Peak memory 1805296 kb
Host smart-b3c6eca4-9dab-4268-bb0f-77f5041a6fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170272806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.1170272806
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.2633148804
Short name T768
Test name
Test status
Simulation time 3203770672 ps
CPU time 11.67 seconds
Started Jan 21 08:20:57 PM PST 24
Finished Jan 21 08:21:09 PM PST 24
Peak memory 210880 kb
Host smart-df4b12c1-14ed-42dd-81ee-85f770d15e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633148804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.2633148804
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.611269528
Short name T350
Test name
Test status
Simulation time 4812664319 ps
CPU time 4.39 seconds
Started Jan 21 08:21:12 PM PST 24
Finished Jan 21 08:21:18 PM PST 24
Peak memory 202628 kb
Host smart-bee01154-40d4-4995-8165-d035790a95f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611269528 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.611269528
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.1403705530
Short name T965
Test name
Test status
Simulation time 10061998546 ps
CPU time 24.52 seconds
Started Jan 21 08:21:07 PM PST 24
Finished Jan 21 08:21:33 PM PST 24
Peak memory 326500 kb
Host smart-31e71a73-a5c3-40cd-bbd1-b9806e5600e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403705530 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.1403705530
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.552928518
Short name T620
Test name
Test status
Simulation time 10457527932 ps
CPU time 14.86 seconds
Started Jan 21 08:21:09 PM PST 24
Finished Jan 21 08:21:26 PM PST 24
Peak memory 293248 kb
Host smart-bb89af7a-4a5a-41c8-96c5-19c703c4fc12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552928518 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_tx.552928518
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.2033293415
Short name T656
Test name
Test status
Simulation time 2260039294 ps
CPU time 2.86 seconds
Started Jan 21 08:21:13 PM PST 24
Finished Jan 21 08:21:17 PM PST 24
Peak memory 202644 kb
Host smart-b2333513-e2fe-49c2-b2e4-8e9e852c535d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033293415 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.2033293415
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.3106947762
Short name T640
Test name
Test status
Simulation time 7361627871 ps
CPU time 5.02 seconds
Started Jan 21 08:21:05 PM PST 24
Finished Jan 21 08:21:11 PM PST 24
Peak memory 202624 kb
Host smart-ab080241-9311-4d65-9e2b-fed248ecd7f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106947762 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.3106947762
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.553335284
Short name T843
Test name
Test status
Simulation time 12633977269 ps
CPU time 405.69 seconds
Started Jan 21 08:21:05 PM PST 24
Finished Jan 21 08:27:52 PM PST 24
Peak memory 2950576 kb
Host smart-1f7ccfb7-6ed8-4bcf-a1a5-75e3b51ebb29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553335284 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.553335284
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_perf.4101828139
Short name T966
Test name
Test status
Simulation time 2806857610 ps
CPU time 4.15 seconds
Started Jan 21 08:21:07 PM PST 24
Finished Jan 21 08:21:12 PM PST 24
Peak memory 205720 kb
Host smart-68869c99-b4ce-40bb-8145-7a8e351ec51e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101828139 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_perf.4101828139
Directory /workspace/6.i2c_target_perf/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.3867640745
Short name T628
Test name
Test status
Simulation time 637253572 ps
CPU time 6.65 seconds
Started Jan 21 08:21:05 PM PST 24
Finished Jan 21 08:21:13 PM PST 24
Peak memory 202544 kb
Host smart-da7f7778-024a-459c-a94b-e1da452edad7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867640745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.3867640745
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_all.4062024877
Short name T755
Test name
Test status
Simulation time 25774758937 ps
CPU time 328.03 seconds
Started Jan 21 08:21:14 PM PST 24
Finished Jan 21 08:26:43 PM PST 24
Peak memory 1207236 kb
Host smart-03c10c62-8e8d-4ee0-98db-4bf7d18db4c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062024877 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_target_stress_all.4062024877
Directory /workspace/6.i2c_target_stress_all/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.1124085850
Short name T402
Test name
Test status
Simulation time 2847328200 ps
CPU time 20.4 seconds
Started Jan 21 08:21:02 PM PST 24
Finished Jan 21 08:21:23 PM PST 24
Peak memory 206828 kb
Host smart-376ded64-f5f1-4a6a-b910-2fae1170d9bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124085850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.1124085850
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.4191831637
Short name T1072
Test name
Test status
Simulation time 9919794388 ps
CPU time 84.31 seconds
Started Jan 21 08:21:04 PM PST 24
Finished Jan 21 08:22:29 PM PST 24
Peak memory 1452864 kb
Host smart-24d6749e-daf5-4545-af07-379d14b5194a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191831637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.4191831637
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.1416045989
Short name T204
Test name
Test status
Simulation time 15703713638 ps
CPU time 153.08 seconds
Started Jan 21 08:21:01 PM PST 24
Finished Jan 21 08:23:35 PM PST 24
Peak memory 1462316 kb
Host smart-792b3ba9-5446-416c-acab-7c43db344bf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416045989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.1416045989
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.260668393
Short name T356
Test name
Test status
Simulation time 1818140650 ps
CPU time 7.66 seconds
Started Jan 21 08:21:10 PM PST 24
Finished Jan 21 08:21:19 PM PST 24
Peak memory 202580 kb
Host smart-21c6dd54-8172-4ec5-ac9d-0b25d2c9b963
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260668393 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_timeout.260668393
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_tx_ovf.4204755182
Short name T315
Test name
Test status
Simulation time 10624255839 ps
CPU time 44.23 seconds
Started Jan 21 08:21:09 PM PST 24
Finished Jan 21 08:21:55 PM PST 24
Peak memory 227172 kb
Host smart-caf90a5a-bfc8-40a8-8bf9-5ef1bb361632
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204755182 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_tx_ovf.4204755182
Directory /workspace/6.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/6.i2c_target_unexp_stop.1539594696
Short name T487
Test name
Test status
Simulation time 2374001175 ps
CPU time 6.09 seconds
Started Jan 21 08:21:09 PM PST 24
Finished Jan 21 08:21:17 PM PST 24
Peak memory 210492 kb
Host smart-1795b565-59df-4f29-954f-0a77786a7843
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539594696 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.i2c_target_unexp_stop.1539594696
Directory /workspace/6.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/7.i2c_alert_test.893857621
Short name T354
Test name
Test status
Simulation time 25092072 ps
CPU time 0.63 seconds
Started Jan 21 08:21:55 PM PST 24
Finished Jan 21 08:21:57 PM PST 24
Peak memory 202016 kb
Host smart-1ea4a169-3170-462d-adea-31e8df2f85ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893857621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.893857621
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.980090281
Short name T403
Test name
Test status
Simulation time 35814884 ps
CPU time 1.21 seconds
Started Jan 21 08:21:29 PM PST 24
Finished Jan 21 08:21:36 PM PST 24
Peak memory 210764 kb
Host smart-7f0287b7-d7a0-42a7-8411-904cba836451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980090281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.980090281
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.4007108493
Short name T265
Test name
Test status
Simulation time 1146126155 ps
CPU time 6.53 seconds
Started Jan 21 08:21:30 PM PST 24
Finished Jan 21 08:21:42 PM PST 24
Peak memory 260280 kb
Host smart-0f1838d7-0ea9-4fc0-9483-d43f5544e69f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007108493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.4007108493
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.43131075
Short name T638
Test name
Test status
Simulation time 3166076036 ps
CPU time 256.67 seconds
Started Jan 21 08:21:30 PM PST 24
Finished Jan 21 08:25:52 PM PST 24
Peak memory 850932 kb
Host smart-ac71026d-0df9-41dc-87b7-652e5b3441c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43131075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.43131075
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.1396967470
Short name T582
Test name
Test status
Simulation time 6001716578 ps
CPU time 507.53 seconds
Started Jan 21 08:21:28 PM PST 24
Finished Jan 21 08:29:57 PM PST 24
Peak memory 1685768 kb
Host smart-8dbf1c1b-7c9e-451d-8675-d38314b9faea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396967470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.1396967470
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.1967421521
Short name T1455
Test name
Test status
Simulation time 179781280 ps
CPU time 1.1 seconds
Started Jan 21 08:21:26 PM PST 24
Finished Jan 21 08:21:28 PM PST 24
Peak memory 202352 kb
Host smart-822128fd-9773-4c51-9d9d-91c771f093f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967421521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.1967421521
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.116582862
Short name T613
Test name
Test status
Simulation time 279850022 ps
CPU time 7.45 seconds
Started Jan 21 08:21:23 PM PST 24
Finished Jan 21 08:21:31 PM PST 24
Peak memory 258536 kb
Host smart-df32e8df-8201-4292-981c-3c8afb616bff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116582862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.116582862
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.873831202
Short name T434
Test name
Test status
Simulation time 32544472712 ps
CPU time 261.4 seconds
Started Jan 21 08:21:23 PM PST 24
Finished Jan 21 08:25:45 PM PST 24
Peak memory 1342816 kb
Host smart-a7201e68-e7b8-4569-925d-8b1b37b14746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873831202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.873831202
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.2652978996
Short name T393
Test name
Test status
Simulation time 6659736990 ps
CPU time 52.56 seconds
Started Jan 21 08:21:56 PM PST 24
Finished Jan 21 08:22:50 PM PST 24
Peak memory 302860 kb
Host smart-f8ffbefc-686f-4d19-b189-2d19ff9e4887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652978996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.2652978996
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.855414960
Short name T611
Test name
Test status
Simulation time 25902027 ps
CPU time 0.64 seconds
Started Jan 21 08:21:25 PM PST 24
Finished Jan 21 08:21:27 PM PST 24
Peak memory 201460 kb
Host smart-bebb08ff-06b2-415d-8b4d-dadf7a2822a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855414960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.855414960
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.1379333355
Short name T146
Test name
Test status
Simulation time 51085437154 ps
CPU time 242.41 seconds
Started Jan 21 08:21:27 PM PST 24
Finished Jan 21 08:25:32 PM PST 24
Peak memory 262072 kb
Host smart-609154e1-3883-4e3b-8331-7696e0a0214b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379333355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.1379333355
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_rx_oversample.3996796602
Short name T281
Test name
Test status
Simulation time 2440612897 ps
CPU time 103.92 seconds
Started Jan 21 08:21:23 PM PST 24
Finished Jan 21 08:23:08 PM PST 24
Peak memory 299372 kb
Host smart-6132069b-886d-4a66-9d36-e76e405d7c55
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996796602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_rx_oversample.
3996796602
Directory /workspace/7.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.1583286263
Short name T976
Test name
Test status
Simulation time 9432328105 ps
CPU time 156.82 seconds
Started Jan 21 08:21:21 PM PST 24
Finished Jan 21 08:23:59 PM PST 24
Peak memory 273788 kb
Host smart-40559161-13c1-4710-b303-81414722143d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583286263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.1583286263
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.2980355244
Short name T915
Test name
Test status
Simulation time 927571038 ps
CPU time 20.64 seconds
Started Jan 21 08:21:29 PM PST 24
Finished Jan 21 08:21:56 PM PST 24
Peak memory 210680 kb
Host smart-33c44874-15b7-4162-b059-d34a2a7b632a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980355244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.2980355244
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.2726875364
Short name T677
Test name
Test status
Simulation time 2601985986 ps
CPU time 4.91 seconds
Started Jan 21 08:21:47 PM PST 24
Finished Jan 21 08:21:56 PM PST 24
Peak memory 202576 kb
Host smart-1400ae30-90ee-4f9c-9b61-24da34d0cad8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726875364 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.2726875364
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.235259320
Short name T262
Test name
Test status
Simulation time 10189003091 ps
CPU time 38.23 seconds
Started Jan 21 08:21:44 PM PST 24
Finished Jan 21 08:22:29 PM PST 24
Peak memory 407752 kb
Host smart-7a281546-f65e-4d30-9b68-9047c43af762
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235259320 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_acq.235259320
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.4284867448
Short name T1468
Test name
Test status
Simulation time 10130562648 ps
CPU time 35.27 seconds
Started Jan 21 08:21:43 PM PST 24
Finished Jan 21 08:22:20 PM PST 24
Peak memory 454532 kb
Host smart-8fb2cb9e-3d92-4ac4-a407-9c41f8efb1cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284867448 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.4284867448
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.3931381021
Short name T1063
Test name
Test status
Simulation time 654757199 ps
CPU time 3.19 seconds
Started Jan 21 08:21:50 PM PST 24
Finished Jan 21 08:21:55 PM PST 24
Peak memory 202644 kb
Host smart-26571799-3b90-490e-9596-2a4eba832ea9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931381021 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.3931381021
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.2081565750
Short name T782
Test name
Test status
Simulation time 3529804912 ps
CPU time 7.71 seconds
Started Jan 21 08:21:34 PM PST 24
Finished Jan 21 08:21:44 PM PST 24
Peak memory 202600 kb
Host smart-1db5b456-3504-424e-8904-ef5bf6dca1c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081565750 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.2081565750
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.4119770049
Short name T841
Test name
Test status
Simulation time 22760864840 ps
CPU time 1150.34 seconds
Started Jan 21 08:21:41 PM PST 24
Finished Jan 21 08:40:53 PM PST 24
Peak memory 5232528 kb
Host smart-693553be-bb93-479d-afe7-a78da7fba7db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119770049 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.4119770049
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_perf.3920249383
Short name T712
Test name
Test status
Simulation time 819102154 ps
CPU time 4.67 seconds
Started Jan 21 08:21:40 PM PST 24
Finished Jan 21 08:21:46 PM PST 24
Peak memory 202564 kb
Host smart-51a2265f-5f14-4a2e-bfe1-13822d43a0a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920249383 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_perf.3920249383
Directory /workspace/7.i2c_target_perf/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.3165470916
Short name T785
Test name
Test status
Simulation time 6031044053 ps
CPU time 39.02 seconds
Started Jan 21 08:21:29 PM PST 24
Finished Jan 21 08:22:14 PM PST 24
Peak memory 202560 kb
Host smart-02e91de3-aa43-4076-9cf8-7bec9ab9ea77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165470916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.3165470916
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_all.3708651248
Short name T972
Test name
Test status
Simulation time 11188443186 ps
CPU time 88.71 seconds
Started Jan 21 08:21:48 PM PST 24
Finished Jan 21 08:23:20 PM PST 24
Peak memory 251148 kb
Host smart-e9e6ea0c-4245-495b-a971-d2cb24909330
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708651248 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_target_stress_all.3708651248
Directory /workspace/7.i2c_target_stress_all/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.3996014134
Short name T1473
Test name
Test status
Simulation time 1280150832 ps
CPU time 52.35 seconds
Started Jan 21 08:21:36 PM PST 24
Finished Jan 21 08:22:32 PM PST 24
Peak memory 202536 kb
Host smart-3a8d29e3-6f31-4e9b-af10-926f5924dbb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996014134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.3996014134
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.649369538
Short name T1434
Test name
Test status
Simulation time 44813998079 ps
CPU time 333.41 seconds
Started Jan 21 08:21:34 PM PST 24
Finished Jan 21 08:27:10 PM PST 24
Peak memory 2605448 kb
Host smart-db0d750e-6319-4a8e-a883-d479ee4ea371
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649369538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_wr.649369538
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.3302730976
Short name T463
Test name
Test status
Simulation time 7346745498 ps
CPU time 8.37 seconds
Started Jan 21 08:21:42 PM PST 24
Finished Jan 21 08:21:52 PM PST 24
Peak memory 210460 kb
Host smart-73a3ccf1-f04a-431d-80dc-1feb6bc6a67a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302730976 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.3302730976
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_ovf.1723351101
Short name T1307
Test name
Test status
Simulation time 12781673147 ps
CPU time 112.31 seconds
Started Jan 21 08:21:42 PM PST 24
Finished Jan 21 08:23:36 PM PST 24
Peak memory 338592 kb
Host smart-2d328fca-a5f1-4804-b3da-020473ec6fa1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723351101 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_tx_ovf.1723351101
Directory /workspace/7.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/7.i2c_target_unexp_stop.3309641482
Short name T1057
Test name
Test status
Simulation time 1093162547 ps
CPU time 5.27 seconds
Started Jan 21 08:21:42 PM PST 24
Finished Jan 21 08:21:49 PM PST 24
Peak memory 206768 kb
Host smart-6d8b62af-6099-44c4-8933-33fb5421fd1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309641482 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.i2c_target_unexp_stop.3309641482
Directory /workspace/7.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/8.i2c_alert_test.504301347
Short name T1194
Test name
Test status
Simulation time 26197517 ps
CPU time 0.62 seconds
Started Jan 21 08:22:21 PM PST 24
Finished Jan 21 08:22:23 PM PST 24
Peak memory 201084 kb
Host smart-600b24be-f358-4ab4-8a6c-6bbb68da5bc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504301347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.504301347
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.2740832489
Short name T48
Test name
Test status
Simulation time 50778587 ps
CPU time 1.43 seconds
Started Jan 21 08:22:03 PM PST 24
Finished Jan 21 08:22:06 PM PST 24
Peak memory 210780 kb
Host smart-43fb6281-d45f-4395-acbc-d9a598e64881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740832489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.2740832489
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.2265287874
Short name T65
Test name
Test status
Simulation time 596097536 ps
CPU time 11.87 seconds
Started Jan 21 08:22:05 PM PST 24
Finished Jan 21 08:22:18 PM PST 24
Peak memory 333632 kb
Host smart-eef964aa-d43c-41d2-81b7-7d861946340f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265287874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.2265287874
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.3133848813
Short name T760
Test name
Test status
Simulation time 4873103123 ps
CPU time 118.79 seconds
Started Jan 21 08:22:05 PM PST 24
Finished Jan 21 08:24:05 PM PST 24
Peak memory 364076 kb
Host smart-86158659-5439-4ef2-a713-27cf99ea0a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133848813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.3133848813
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.2402992161
Short name T948
Test name
Test status
Simulation time 14922005606 ps
CPU time 188.43 seconds
Started Jan 21 08:22:02 PM PST 24
Finished Jan 21 08:25:11 PM PST 24
Peak memory 1057736 kb
Host smart-17a063c8-2119-4c71-b552-5576c564f049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402992161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.2402992161
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.4036032304
Short name T199
Test name
Test status
Simulation time 189455090 ps
CPU time 1.02 seconds
Started Jan 21 08:22:03 PM PST 24
Finished Jan 21 08:22:05 PM PST 24
Peak memory 202292 kb
Host smart-0660d9ce-ac24-4adb-98f9-479c3880f90e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036032304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.4036032304
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.3976929490
Short name T563
Test name
Test status
Simulation time 352035564 ps
CPU time 4.22 seconds
Started Jan 21 08:22:03 PM PST 24
Finished Jan 21 08:22:08 PM PST 24
Peak memory 202612 kb
Host smart-25781954-a109-41c3-9eff-ba78c77202b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976929490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
3976929490
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.3814399464
Short name T1237
Test name
Test status
Simulation time 18521305348 ps
CPU time 199.82 seconds
Started Jan 21 08:22:04 PM PST 24
Finished Jan 21 08:25:25 PM PST 24
Peak memory 1033744 kb
Host smart-1c08ef99-337d-48af-822d-22c08a23d795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814399464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.3814399464
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.593283132
Short name T1225
Test name
Test status
Simulation time 30658676336 ps
CPU time 33.13 seconds
Started Jan 21 11:32:47 PM PST 24
Finished Jan 21 11:33:24 PM PST 24
Peak memory 248512 kb
Host smart-f32820de-257e-48fe-80fe-97b288a70a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593283132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.593283132
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.2185527083
Short name T499
Test name
Test status
Simulation time 16673573 ps
CPU time 0.65 seconds
Started Jan 21 08:21:53 PM PST 24
Finished Jan 21 08:21:55 PM PST 24
Peak memory 201520 kb
Host smart-37c7c82b-9870-4c56-b1af-13bee94c13c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185527083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.2185527083
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.2166396909
Short name T476
Test name
Test status
Simulation time 1072545871 ps
CPU time 12.96 seconds
Started Jan 21 08:22:05 PM PST 24
Finished Jan 21 08:22:19 PM PST 24
Peak memory 210688 kb
Host smart-53541ddd-aab8-4cf0-83d7-109eab3f7f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166396909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.2166396909
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_rx_oversample.2452367915
Short name T9
Test name
Test status
Simulation time 1980112314 ps
CPU time 91.35 seconds
Started Jan 21 08:21:54 PM PST 24
Finished Jan 21 08:23:27 PM PST 24
Peak memory 308956 kb
Host smart-eb038eb6-aaf6-43a6-80d6-f6bfdd15ddc0
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452367915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_rx_oversample.
2452367915
Directory /workspace/8.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.669944003
Short name T453
Test name
Test status
Simulation time 9821471872 ps
CPU time 70.16 seconds
Started Jan 21 08:21:57 PM PST 24
Finished Jan 21 08:23:08 PM PST 24
Peak memory 323956 kb
Host smart-2ce1be8c-3156-4dad-a6ca-fa654f2d2633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669944003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.669944003
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.2657513976
Short name T190
Test name
Test status
Simulation time 7751812130 ps
CPU time 1135.88 seconds
Started Jan 21 08:22:04 PM PST 24
Finished Jan 21 08:41:01 PM PST 24
Peak memory 1835956 kb
Host smart-790fddba-c305-4890-ba87-71a63492dd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657513976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.2657513976
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.2275217143
Short name T1450
Test name
Test status
Simulation time 1159874537 ps
CPU time 17.3 seconds
Started Jan 21 08:22:05 PM PST 24
Finished Jan 21 08:22:23 PM PST 24
Peak memory 218148 kb
Host smart-7d21fc4b-8fb6-4e0d-9022-480ffd831dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275217143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.2275217143
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.1476290748
Short name T477
Test name
Test status
Simulation time 896934985 ps
CPU time 3.82 seconds
Started Jan 21 08:22:16 PM PST 24
Finished Jan 21 08:22:23 PM PST 24
Peak memory 202544 kb
Host smart-a5fb1cec-2b92-4ac6-9762-562aff4e2b1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476290748 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.1476290748
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.3783473241
Short name T70
Test name
Test status
Simulation time 10031300525 ps
CPU time 50.72 seconds
Started Jan 21 08:22:13 PM PST 24
Finished Jan 21 08:23:08 PM PST 24
Peak memory 407196 kb
Host smart-e728da88-9210-4d90-a423-cf9928183264
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783473241 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.3783473241
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.731740470
Short name T1116
Test name
Test status
Simulation time 10098467082 ps
CPU time 81.5 seconds
Started Jan 21 08:22:09 PM PST 24
Finished Jan 21 08:23:32 PM PST 24
Peak memory 625604 kb
Host smart-758ab01d-e162-4266-bc68-280c30a5e17f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731740470 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_fifo_reset_tx.731740470
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.4223439939
Short name T428
Test name
Test status
Simulation time 2240150454 ps
CPU time 2.99 seconds
Started Jan 21 09:09:15 PM PST 24
Finished Jan 21 09:09:25 PM PST 24
Peak memory 202728 kb
Host smart-21e2205d-07c5-4dd0-8a1f-9638c386d6e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223439939 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.4223439939
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.2303669200
Short name T598
Test name
Test status
Simulation time 6009187271 ps
CPU time 6.09 seconds
Started Jan 21 08:22:08 PM PST 24
Finished Jan 21 08:22:17 PM PST 24
Peak memory 208768 kb
Host smart-74ab9570-2dff-430c-afbf-0f6bcd35d015
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303669200 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.2303669200
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.1648959609
Short name T1197
Test name
Test status
Simulation time 21269169219 ps
CPU time 124.87 seconds
Started Jan 21 08:22:09 PM PST 24
Finished Jan 21 08:24:15 PM PST 24
Peak memory 1353664 kb
Host smart-b507fa54-6828-4d4b-94b4-cf1f49bb78ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648959609 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.1648959609
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_perf.475814500
Short name T696
Test name
Test status
Simulation time 550126798 ps
CPU time 3.37 seconds
Started Jan 21 08:22:14 PM PST 24
Finished Jan 21 08:22:21 PM PST 24
Peak memory 202580 kb
Host smart-20fecc02-3c3a-41b4-a4be-0d4697ab267a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475814500 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.i2c_target_perf.475814500
Directory /workspace/8.i2c_target_perf/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.970925622
Short name T1041
Test name
Test status
Simulation time 1540600638 ps
CPU time 19.68 seconds
Started Jan 21 08:22:06 PM PST 24
Finished Jan 21 08:22:26 PM PST 24
Peak memory 202568 kb
Host smart-d80da1f6-33e0-45ea-aae4-9358821f95fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970925622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_targ
et_smoke.970925622
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_all.3986805748
Short name T813
Test name
Test status
Simulation time 60288739077 ps
CPU time 425.78 seconds
Started Jan 21 08:22:14 PM PST 24
Finished Jan 21 08:29:24 PM PST 24
Peak memory 1038452 kb
Host smart-1529212d-3603-48a9-bdb2-886aff3fd841
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986805748 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.i2c_target_stress_all.3986805748
Directory /workspace/8.i2c_target_stress_all/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.411142558
Short name T1422
Test name
Test status
Simulation time 2486226503 ps
CPU time 36.14 seconds
Started Jan 21 08:22:09 PM PST 24
Finished Jan 21 08:22:51 PM PST 24
Peak memory 231752 kb
Host smart-027e4610-fccf-4cc2-9ca1-e1b43d0bb7e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411142558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_rd.411142558
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.1822966418
Short name T1092
Test name
Test status
Simulation time 14601383641 ps
CPU time 28.75 seconds
Started Jan 21 08:48:09 PM PST 24
Finished Jan 21 08:48:58 PM PST 24
Peak memory 722588 kb
Host smart-bd5a5bb6-30ea-4667-955f-e8ceb3b321a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822966418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.1822966418
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.2013040381
Short name T238
Test name
Test status
Simulation time 19450363090 ps
CPU time 35.4 seconds
Started Jan 21 08:22:13 PM PST 24
Finished Jan 21 08:22:53 PM PST 24
Peak memory 498664 kb
Host smart-3536334e-25e8-497b-bc24-314a951a5037
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013040381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.2013040381
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.3943871043
Short name T1033
Test name
Test status
Simulation time 7363068947 ps
CPU time 8.03 seconds
Started Jan 21 08:22:09 PM PST 24
Finished Jan 21 08:22:23 PM PST 24
Peak memory 202636 kb
Host smart-6d54df39-e90a-424e-aa49-2c2933aa8c90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943871043 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.3943871043
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_ovf.971552671
Short name T1078
Test name
Test status
Simulation time 3384969959 ps
CPU time 114.37 seconds
Started Jan 21 08:22:10 PM PST 24
Finished Jan 21 08:24:11 PM PST 24
Peak memory 322600 kb
Host smart-32986181-a0f0-492a-8d4b-982d0b7d281f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971552671 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_tx_ovf.971552671
Directory /workspace/8.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/8.i2c_target_unexp_stop.3475900114
Short name T1515
Test name
Test status
Simulation time 1589753857 ps
CPU time 8.01 seconds
Started Jan 21 08:22:09 PM PST 24
Finished Jan 21 08:22:23 PM PST 24
Peak memory 207976 kb
Host smart-453f01e8-ed6f-48c4-b0b6-f6c6771613ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475900114 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.i2c_target_unexp_stop.3475900114
Directory /workspace/8.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/9.i2c_alert_test.1800149155
Short name T1271
Test name
Test status
Simulation time 18146020 ps
CPU time 0.64 seconds
Started Jan 21 08:22:51 PM PST 24
Finished Jan 21 08:22:52 PM PST 24
Peak memory 201132 kb
Host smart-f8d1e20e-c9fa-4450-a6b6-dd08150df38d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800149155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.1800149155
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.3723652536
Short name T579
Test name
Test status
Simulation time 34711516 ps
CPU time 1.48 seconds
Started Jan 21 08:22:32 PM PST 24
Finished Jan 21 08:22:34 PM PST 24
Peak memory 213172 kb
Host smart-f2c17faa-4abc-45dd-a633-8c246f85ed31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723652536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.3723652536
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.3449843140
Short name T223
Test name
Test status
Simulation time 1311900405 ps
CPU time 15.86 seconds
Started Jan 21 08:22:33 PM PST 24
Finished Jan 21 08:22:49 PM PST 24
Peak memory 263396 kb
Host smart-d9de693b-3a7b-492b-a062-fa3358eafe0b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449843140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.3449843140
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.838593819
Short name T365
Test name
Test status
Simulation time 1723981645 ps
CPU time 88.92 seconds
Started Jan 21 08:26:42 PM PST 24
Finished Jan 21 08:28:11 PM PST 24
Peak memory 210716 kb
Host smart-a1c187f9-73d0-4b72-9905-42465e5bcabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838593819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.838593819
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.629473375
Short name T649
Test name
Test status
Simulation time 22859589854 ps
CPU time 286.27 seconds
Started Jan 21 08:22:26 PM PST 24
Finished Jan 21 08:27:13 PM PST 24
Peak memory 1230204 kb
Host smart-10d0c6cc-68e5-4c6b-90bb-c6c11ee98d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629473375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.629473375
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.1095749024
Short name T674
Test name
Test status
Simulation time 160089779 ps
CPU time 1.06 seconds
Started Jan 21 08:55:25 PM PST 24
Finished Jan 21 08:55:40 PM PST 24
Peak memory 202352 kb
Host smart-3b644654-0495-48aa-9ae9-457104e49773
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095749024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.1095749024
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.2507217499
Short name T342
Test name
Test status
Simulation time 764503451 ps
CPU time 12.83 seconds
Started Jan 21 08:22:28 PM PST 24
Finished Jan 21 08:22:42 PM PST 24
Peak memory 242004 kb
Host smart-a16f1eb1-2428-4ab7-a97f-136e76e9d5f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507217499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
2507217499
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.1478490955
Short name T1009
Test name
Test status
Simulation time 6522698666 ps
CPU time 172.39 seconds
Started Jan 21 08:22:27 PM PST 24
Finished Jan 21 08:25:20 PM PST 24
Peak memory 1017092 kb
Host smart-66da1270-f26b-4ba9-8f51-719ae47cb68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478490955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.1478490955
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.2745678753
Short name T1231
Test name
Test status
Simulation time 2461058572 ps
CPU time 84.96 seconds
Started Jan 21 08:22:52 PM PST 24
Finished Jan 21 08:24:18 PM PST 24
Peak memory 313696 kb
Host smart-ba37b793-0ed5-4f92-bfdd-2c7d4a340c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745678753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.2745678753
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.2830961793
Short name T664
Test name
Test status
Simulation time 36358570 ps
CPU time 0.63 seconds
Started Jan 21 09:49:52 PM PST 24
Finished Jan 21 09:49:58 PM PST 24
Peak memory 201456 kb
Host smart-fbf65e04-73d1-491a-9943-688b4917d44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830961793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.2830961793
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.2069130387
Short name T1048
Test name
Test status
Simulation time 4586063265 ps
CPU time 31.34 seconds
Started Jan 21 08:22:28 PM PST 24
Finished Jan 21 08:23:00 PM PST 24
Peak memory 212228 kb
Host smart-50a18bae-da4f-4cc7-8877-94589c11417b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069130387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.2069130387
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_rx_oversample.3094819359
Short name T671
Test name
Test status
Simulation time 6402563185 ps
CPU time 80.6 seconds
Started Jan 21 08:22:20 PM PST 24
Finished Jan 21 08:23:42 PM PST 24
Peak memory 283888 kb
Host smart-87702ff2-756d-4e7c-94a3-f3a40735db14
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094819359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_rx_oversample.
3094819359
Directory /workspace/9.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.3560651223
Short name T1042
Test name
Test status
Simulation time 7950913614 ps
CPU time 151.59 seconds
Started Jan 21 08:22:23 PM PST 24
Finished Jan 21 08:24:55 PM PST 24
Peak memory 264312 kb
Host smart-b07c771c-5fe9-47c5-b258-f3bbf31ae05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560651223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.3560651223
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.2355932753
Short name T363
Test name
Test status
Simulation time 36011287715 ps
CPU time 3321.16 seconds
Started Jan 21 08:22:33 PM PST 24
Finished Jan 21 09:17:55 PM PST 24
Peak memory 4521656 kb
Host smart-4bb1ebc6-b649-4305-a06a-8d568c56448e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355932753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.2355932753
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.469847920
Short name T934
Test name
Test status
Simulation time 1628142952 ps
CPU time 21.3 seconds
Started Jan 21 08:22:33 PM PST 24
Finished Jan 21 08:22:55 PM PST 24
Peak memory 210716 kb
Host smart-560e5f26-fb73-4899-b406-870568138c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469847920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.469847920
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.2064525762
Short name T1438
Test name
Test status
Simulation time 3808319399 ps
CPU time 5.47 seconds
Started Jan 21 08:47:26 PM PST 24
Finished Jan 21 08:48:01 PM PST 24
Peak memory 202616 kb
Host smart-0886c784-27d2-434c-a074-e2f1a652ac09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064525762 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.2064525762
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.1511230644
Short name T617
Test name
Test status
Simulation time 11116945178 ps
CPU time 8.68 seconds
Started Jan 21 08:22:39 PM PST 24
Finished Jan 21 08:22:49 PM PST 24
Peak memory 231364 kb
Host smart-b0500fb9-cd20-49a8-b180-af0cebee9548
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511230644 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.1511230644
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.516919423
Short name T1384
Test name
Test status
Simulation time 10415666433 ps
CPU time 15.4 seconds
Started Jan 21 08:22:43 PM PST 24
Finished Jan 21 08:22:59 PM PST 24
Peak memory 293176 kb
Host smart-ae1f2047-2a14-4058-a220-408cfc872c47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516919423 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_fifo_reset_tx.516919423
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.2209411740
Short name T410
Test name
Test status
Simulation time 1044035199 ps
CPU time 2.56 seconds
Started Jan 21 08:22:44 PM PST 24
Finished Jan 21 08:22:47 PM PST 24
Peak memory 202628 kb
Host smart-2edbed86-2127-48e5-a846-611cc016bb60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209411740 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.2209411740
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.2699946398
Short name T852
Test name
Test status
Simulation time 1977178025 ps
CPU time 5.27 seconds
Started Jan 21 08:22:41 PM PST 24
Finished Jan 21 08:22:48 PM PST 24
Peak memory 202516 kb
Host smart-0f0e535f-ce62-4a6f-af7a-75c3919fa609
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699946398 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.2699946398
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.1164173278
Short name T1215
Test name
Test status
Simulation time 7469334135 ps
CPU time 40.28 seconds
Started Jan 21 08:22:39 PM PST 24
Finished Jan 21 08:23:21 PM PST 24
Peak memory 849360 kb
Host smart-052b168d-021c-4e13-a0bb-a7149c5bd828
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164173278 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.1164173278
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_perf.75009844
Short name T1332
Test name
Test status
Simulation time 11662028386 ps
CPU time 4.37 seconds
Started Jan 21 08:22:40 PM PST 24
Finished Jan 21 08:22:45 PM PST 24
Peak memory 202620 kb
Host smart-fe54c814-aac7-4d12-af11-224f15570c2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75009844 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.i2c_target_perf.75009844
Directory /workspace/9.i2c_target_perf/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.66526647
Short name T1281
Test name
Test status
Simulation time 22647829131 ps
CPU time 18.06 seconds
Started Jan 21 08:22:35 PM PST 24
Finished Jan 21 08:22:54 PM PST 24
Peak memory 202560 kb
Host smart-5ce116f3-fecb-48d0-b29c-604021fa6f3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66526647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_targe
t_smoke.66526647
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.1406497172
Short name T1181
Test name
Test status
Simulation time 3461201120 ps
CPU time 38.06 seconds
Started Jan 21 08:22:40 PM PST 24
Finished Jan 21 08:23:19 PM PST 24
Peak memory 202584 kb
Host smart-81a0430b-6491-49a0-b0ee-60a8458e5eb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406497172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.1406497172
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.1566029286
Short name T467
Test name
Test status
Simulation time 54183807706 ps
CPU time 1511.41 seconds
Started Jan 21 08:22:35 PM PST 24
Finished Jan 21 08:47:48 PM PST 24
Peak memory 6365564 kb
Host smart-faa7fd13-eebd-41b6-914a-d410796012fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566029286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.1566029286
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.1118869599
Short name T892
Test name
Test status
Simulation time 1300403077 ps
CPU time 6.65 seconds
Started Jan 21 08:22:42 PM PST 24
Finished Jan 21 08:22:50 PM PST 24
Peak memory 211192 kb
Host smart-3c3e4af4-84cc-44bf-a202-f08c4afca377
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118869599 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.1118869599
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_ovf.1136204864
Short name T660
Test name
Test status
Simulation time 38942805263 ps
CPU time 323.91 seconds
Started Jan 21 08:22:39 PM PST 24
Finished Jan 21 08:28:04 PM PST 24
Peak memory 533812 kb
Host smart-829e2cdb-0543-44a7-b45c-59534cc718ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136204864 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_tx_ovf.1136204864
Directory /workspace/9.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/9.i2c_target_unexp_stop.2102929821
Short name T1032
Test name
Test status
Simulation time 12057437046 ps
CPU time 7.65 seconds
Started Jan 21 08:22:40 PM PST 24
Finished Jan 21 08:22:49 PM PST 24
Peak memory 202668 kb
Host smart-bce9cb48-cff3-4de5-943d-4279b6d16475
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102929821 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.i2c_target_unexp_stop.2102929821
Directory /workspace/9.i2c_target_unexp_stop/latest
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