Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.01	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	15	45	75.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	15	45	75.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	321	1			T7	5		T8	8		T9	5
all_values[1]	321	1			T7	5		T8	8		T9	5
all_values[2]	321	1			T7	5		T8	8		T9	5
all_values[3]	321	1			T7	5		T8	8		T9	5
all_values[4]	321	1			T7	5		T8	8		T9	5
all_values[5]	321	1			T7	5		T8	8		T9	5
all_values[6]	321	1			T7	5		T8	8		T9	5
all_values[7]	321	1			T7	5		T8	8		T9	5
all_values[8]	321	1			T7	5		T8	8		T9	5
all_values[9]	321	1			T7	5		T8	8		T9	5
all_values[10]	321	1			T7	5		T8	8		T9	5
all_values[11]	321	1			T7	5		T8	8		T9	5
all_values[12]	321	1			T7	5		T8	8		T9	5
all_values[13]	321	1			T7	5		T8	8		T9	5
all_values[14]	321	1			T7	5		T8	8		T9	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3103

1

T7

51

T8

72

T9

64

auto[1]

1712

1

T7

24

T8

48

T9

11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1103

1

T7

21

T8

14

T9

18

auto[1]

3712

1

T7

54

T8

106

T9

57

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	15	45	75.00	15

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	[auto[0]]	--	--	15

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	76	1			T7	1		T15	1		T16	1
all_values[0]	auto[0]	auto[1]	126	1			T7	3		T8	5		T9	4
all_values[0]	auto[1]	auto[1]	119	1			T7	1		T8	3		T9	1
all_values[1]	auto[0]	auto[0]	87	1			T8	2		T15	1		T16	1
all_values[1]	auto[0]	auto[1]	119	1			T7	4		T8	3		T9	3
all_values[1]	auto[1]	auto[1]	115	1			T7	1		T8	3		T9	2
all_values[2]	auto[0]	auto[0]	80	1			T7	5		T8	2		T9	1
all_values[2]	auto[0]	auto[1]	131	1			T8	2		T9	4		T10	1
all_values[2]	auto[1]	auto[1]	110	1			T8	4		T10	3		T11	3
all_values[3]	auto[0]	auto[0]	57	1			T7	5		T9	1		T15	1
all_values[3]	auto[0]	auto[1]	138	1			T8	5		T9	4		T10	1
all_values[3]	auto[1]	auto[1]	126	1			T8	3		T10	4		T12	3
all_values[4]	auto[0]	auto[0]	79	1			T9	1		T15	1		T16	1
all_values[4]	auto[0]	auto[1]	128	1			T7	1		T8	5		T9	4
all_values[4]	auto[1]	auto[1]	114	1			T7	4		T8	3		T11	1
all_values[5]	auto[0]	auto[0]	73	1			T7	1		T8	2		T9	1
all_values[5]	auto[0]	auto[1]	133	1			T7	1		T8	3		T9	2
all_values[5]	auto[1]	auto[1]	115	1			T7	3		T8	3		T9	2
all_values[6]	auto[0]	auto[0]	65	1			T7	2		T9	1		T15	1
all_values[6]	auto[0]	auto[1]	141	1			T7	3		T8	6		T9	3
all_values[6]	auto[1]	auto[1]	115	1			T8	2		T9	1		T10	1
all_values[7]	auto[0]	auto[0]	83	1			T7	1		T9	1		T15	1
all_values[7]	auto[0]	auto[1]	118	1			T7	1		T8	1		T9	2
all_values[7]	auto[1]	auto[1]	120	1			T7	3		T8	7		T9	2
all_values[8]	auto[0]	auto[0]	72	1			T9	1		T15	1		T16	1
all_values[8]	auto[0]	auto[1]	134	1			T7	3		T8	3		T9	3
all_values[8]	auto[1]	auto[1]	115	1			T7	2		T8	5		T9	1
all_values[9]	auto[0]	auto[0]	63	1			T7	1		T8	1		T15	1
all_values[9]	auto[0]	auto[1]	142	1			T7	3		T8	4		T9	5
all_values[9]	auto[1]	auto[1]	116	1			T7	1		T8	3		T10	1
all_values[10]	auto[0]	auto[0]	69	1			T9	2		T15	1		T16	1
all_values[10]	auto[0]	auto[1]	150	1			T7	2		T8	3		T9	2
all_values[10]	auto[1]	auto[1]	102	1			T7	3		T8	5		T9	1
all_values[11]	auto[0]	auto[0]	83	1			T8	4		T9	5		T15	1
all_values[11]	auto[0]	auto[1]	146	1			T7	3		T8	4		T10	3
all_values[11]	auto[1]	auto[1]	92	1			T7	2		T10	2		T12	4
all_values[12]	auto[0]	auto[0]	80	1			T7	1		T8	3		T9	2
all_values[12]	auto[0]	auto[1]	146	1			T7	2		T8	2		T9	2
all_values[12]	auto[1]	auto[1]	95	1			T7	2		T8	3		T9	1
all_values[13]	auto[0]	auto[0]	69	1			T7	2		T15	1		T16	1
all_values[13]	auto[0]	auto[1]	117	1			T7	1		T8	5		T9	5
all_values[13]	auto[1]	auto[1]	135	1			T7	2		T8	3		T10	4
all_values[14]	auto[0]	auto[0]	67	1			T7	2		T9	2		T15	1
all_values[14]	auto[0]	auto[1]	131	1			T7	3		T8	7		T9	3
all_values[14]	auto[1]	auto[1]	123	1			T8	1		T10	4		T11	4