Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
59.13	52.44	59.04	94.90	0.00	53.13	100.00	54.41

Total tests in report: 165

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
50.44	50.44	49.66	49.66	49.87	49.87	92.33	92.33	0.00	0.00	50.38	50.38	92.28	92.28	18.59	18.59	/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.960372452
56.19	5.74	51.76	2.10	56.09	6.22	95.40	3.07	0.00	0.00	53.02	2.63	92.60	0.32	44.43	25.84	/workspace/coverage/cover_reg_top/8.i2c_intr_test.3331825177
58.05	1.87	51.76	0.00	58.37	2.28	99.49	4.09	0.00	0.00	53.13	0.11	96.78	4.18	46.85	2.42	/workspace/coverage/cover_reg_top/11.i2c_tl_errors.2006509049
58.62	0.57	51.76	0.00	58.37	0.00	100.00	0.51	0.00	0.00	53.13	0.00	96.78	0.00	50.32	3.47	/workspace/coverage/cover_reg_top/25.i2c_intr_test.1207845125
59.05	0.43	51.76	0.00	58.37	0.00	100.00	0.00	0.00	0.00	53.13	0.00	99.68	2.89	50.42	0.11	/workspace/coverage/cover_reg_top/15.i2c_csr_rw.2546419267
59.29	0.24	52.44	0.68	58.50	0.13	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.32	50.95	0.53	/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.4219240286
59.44	0.15	52.44	0.00	58.50	0.00	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	52.00	1.05	/workspace/coverage/cover_reg_top/18.i2c_intr_test.1250526486
59.54	0.11	52.44	0.00	58.50	0.00	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	52.73	0.74	/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3859571791
59.62	0.08	52.44	0.00	58.50	0.00	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	53.26	0.53	/workspace/coverage/cover_reg_top/26.i2c_intr_test.154376052
59.66	0.05	52.44	0.00	58.50	0.00	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	53.57	0.32	/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1476778163
59.70	0.03	52.44	0.00	58.63	0.13	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	53.68	0.11	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1179513390
59.73	0.03	52.44	0.00	58.77	0.13	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	53.78	0.11	/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2792451689
59.76	0.03	52.44	0.00	58.77	0.00	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	53.99	0.21	/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.189751657
59.79	0.03	52.44	0.00	58.77	0.00	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	54.20	0.21	/workspace/coverage/cover_reg_top/6.i2c_intr_test.1169467144
59.81	0.02	52.44	0.00	58.90	0.13	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	54.20	0.00	/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2488661754
59.83	0.02	52.44	0.00	59.04	0.13	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	54.20	0.00	/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.4032507451
59.84	0.02	52.44	0.00	59.04	0.00	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	54.31	0.11	/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.524911021
59.86	0.02	52.44	0.00	59.04	0.00	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	54.41	0.11	/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1785175667

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1354103890
/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1788361887
/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3555470318
/workspace/coverage/cover_reg_top/0.i2c_csr_rw.4223384004
/workspace/coverage/cover_reg_top/0.i2c_intr_test.3828405321
/workspace/coverage/cover_reg_top/0.i2c_tl_errors.3777167658
/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2117036794
/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3182296587
/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.4238179145
/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3678359350
/workspace/coverage/cover_reg_top/1.i2c_csr_rw.4002730728
/workspace/coverage/cover_reg_top/1.i2c_intr_test.537523322
/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2606448871
/workspace/coverage/cover_reg_top/1.i2c_tl_errors.1054565484
/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3716060403
/workspace/coverage/cover_reg_top/10.i2c_csr_rw.3929447075
/workspace/coverage/cover_reg_top/10.i2c_intr_test.3902993107
/workspace/coverage/cover_reg_top/10.i2c_tl_errors.2798041122
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.320603310
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.2857241105
/workspace/coverage/cover_reg_top/11.i2c_intr_test.997809205
/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3190157081
/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1694565760
/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.4187226920
/workspace/coverage/cover_reg_top/12.i2c_csr_rw.3917996258
/workspace/coverage/cover_reg_top/12.i2c_intr_test.2562183882
/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2275194665
/workspace/coverage/cover_reg_top/12.i2c_tl_errors.2955172236
/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.923154949
/workspace/coverage/cover_reg_top/13.i2c_csr_rw.1334682396
/workspace/coverage/cover_reg_top/13.i2c_intr_test.1860641020
/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.834929040
/workspace/coverage/cover_reg_top/13.i2c_tl_errors.2511568239
/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.712014980
/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.69744849
/workspace/coverage/cover_reg_top/14.i2c_csr_rw.1482187336
/workspace/coverage/cover_reg_top/14.i2c_intr_test.1147858285
/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.475728565
/workspace/coverage/cover_reg_top/14.i2c_tl_errors.2500249585
/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3301660439
/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1349838218
/workspace/coverage/cover_reg_top/15.i2c_intr_test.1319089147
/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2205649103
/workspace/coverage/cover_reg_top/15.i2c_tl_errors.4124614834
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3758813398
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.253614196
/workspace/coverage/cover_reg_top/16.i2c_intr_test.325452687
/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2399422781
/workspace/coverage/cover_reg_top/16.i2c_tl_errors.2465719
/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.76665595
/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.71824287
/workspace/coverage/cover_reg_top/17.i2c_csr_rw.2841190063
/workspace/coverage/cover_reg_top/17.i2c_intr_test.2035981350
/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3494334608
/workspace/coverage/cover_reg_top/17.i2c_tl_errors.3623816127
/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.7187763
/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1636464267
/workspace/coverage/cover_reg_top/18.i2c_csr_rw.575291022
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3197861879
/workspace/coverage/cover_reg_top/18.i2c_tl_errors.1869596643
/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3281382382
/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2092946169
/workspace/coverage/cover_reg_top/19.i2c_csr_rw.2014088392
/workspace/coverage/cover_reg_top/19.i2c_intr_test.4118775688
/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1956799705
/workspace/coverage/cover_reg_top/19.i2c_tl_errors.659795702
/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2897931938
/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.17700448
/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3976792984
/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.448080374
/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.406930697
/workspace/coverage/cover_reg_top/2.i2c_csr_rw.1081821958
/workspace/coverage/cover_reg_top/2.i2c_intr_test.568919477
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2755310927
/workspace/coverage/cover_reg_top/2.i2c_tl_errors.241674437
/workspace/coverage/cover_reg_top/20.i2c_intr_test.3230899967
/workspace/coverage/cover_reg_top/21.i2c_intr_test.4054838150
/workspace/coverage/cover_reg_top/22.i2c_intr_test.1970761314
/workspace/coverage/cover_reg_top/23.i2c_intr_test.3910017624
/workspace/coverage/cover_reg_top/24.i2c_intr_test.2628957596
/workspace/coverage/cover_reg_top/27.i2c_intr_test.1976048575
/workspace/coverage/cover_reg_top/28.i2c_intr_test.3990491063
/workspace/coverage/cover_reg_top/29.i2c_intr_test.1662155535
/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3742645155
/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2389200491
/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.951107963
/workspace/coverage/cover_reg_top/3.i2c_csr_rw.2417212929
/workspace/coverage/cover_reg_top/3.i2c_intr_test.2117302785
/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2244627061
/workspace/coverage/cover_reg_top/3.i2c_tl_errors.942321047
/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1067060552
/workspace/coverage/cover_reg_top/30.i2c_intr_test.2429589081
/workspace/coverage/cover_reg_top/31.i2c_intr_test.53470702
/workspace/coverage/cover_reg_top/32.i2c_intr_test.847995988
/workspace/coverage/cover_reg_top/33.i2c_intr_test.3456613516
/workspace/coverage/cover_reg_top/34.i2c_intr_test.1948382074
/workspace/coverage/cover_reg_top/35.i2c_intr_test.1267668118
/workspace/coverage/cover_reg_top/36.i2c_intr_test.3830496648
/workspace/coverage/cover_reg_top/37.i2c_intr_test.3523672309
/workspace/coverage/cover_reg_top/38.i2c_intr_test.4155909420
/workspace/coverage/cover_reg_top/39.i2c_intr_test.843583309
/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.984902669
/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.136435648
/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1755610338
/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.737783806
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.1104017312
/workspace/coverage/cover_reg_top/4.i2c_intr_test.957263486
/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.997284398
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.2429463824
/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3515004789
/workspace/coverage/cover_reg_top/40.i2c_intr_test.4041324828
/workspace/coverage/cover_reg_top/41.i2c_intr_test.1215171831
/workspace/coverage/cover_reg_top/42.i2c_intr_test.2952972357
/workspace/coverage/cover_reg_top/43.i2c_intr_test.3180629324
/workspace/coverage/cover_reg_top/44.i2c_intr_test.2318306603
/workspace/coverage/cover_reg_top/45.i2c_intr_test.2510335951
/workspace/coverage/cover_reg_top/46.i2c_intr_test.22000581
/workspace/coverage/cover_reg_top/47.i2c_intr_test.3689144286
/workspace/coverage/cover_reg_top/48.i2c_intr_test.1468661300
/workspace/coverage/cover_reg_top/49.i2c_intr_test.1854062823
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1730920266
/workspace/coverage/cover_reg_top/5.i2c_csr_rw.3312112922
/workspace/coverage/cover_reg_top/5.i2c_intr_test.364034182
/workspace/coverage/cover_reg_top/5.i2c_tl_errors.3830125489
/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1351088036
/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3130289213
/workspace/coverage/cover_reg_top/6.i2c_csr_rw.210763097
/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2747782519
/workspace/coverage/cover_reg_top/6.i2c_tl_errors.1483051809
/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3940368162
/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3890592155
/workspace/coverage/cover_reg_top/7.i2c_csr_rw.3998101676
/workspace/coverage/cover_reg_top/7.i2c_intr_test.1949152230
/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.977707089
/workspace/coverage/cover_reg_top/7.i2c_tl_errors.454701460
/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3643545193
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.4085357586
/workspace/coverage/cover_reg_top/8.i2c_csr_rw.1199284431
/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.201977954
/workspace/coverage/cover_reg_top/8.i2c_tl_errors.2100005213
/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2785572034
/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2739724335
/workspace/coverage/cover_reg_top/9.i2c_csr_rw.1295771708
/workspace/coverage/cover_reg_top/9.i2c_intr_test.2271267889
/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2385181386
/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3481156703
/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3513700073

Total test records in report: 165

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3758813398	Feb 04 12:44:38 PM PST 24	Feb 04 12:44:44 PM PST 24	27279295 ps
T2	/workspace/coverage/cover_reg_top/17.i2c_csr_rw.2841190063	Feb 04 12:44:45 PM PST 24	Feb 04 12:44:50 PM PST 24	17310674 ps
T3	/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3513700073	Feb 04 12:44:31 PM PST 24	Feb 04 12:44:34 PM PST 24	238544827 ps
T5	/workspace/coverage/cover_reg_top/4.i2c_csr_rw.1104017312	Feb 04 12:44:32 PM PST 24	Feb 04 12:44:33 PM PST 24	43107615 ps
T4	/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.4219240286	Feb 04 12:44:35 PM PST 24	Feb 04 12:44:41 PM PST 24	176067649 ps
T6	/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.960372452	Feb 04 12:44:32 PM PST 24	Feb 04 12:44:38 PM PST 24	534492316 ps
T7	/workspace/coverage/cover_reg_top/6.i2c_intr_test.1169467144	Feb 04 12:44:30 PM PST 24	Feb 04 12:44:32 PM PST 24	19871561 ps
T8	/workspace/coverage/cover_reg_top/8.i2c_intr_test.3331825177	Feb 04 12:44:32 PM PST 24	Feb 04 12:44:35 PM PST 24	19286132 ps
T13	/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.69744849	Feb 04 12:44:33 PM PST 24	Feb 04 12:44:38 PM PST 24	189418768 ps
T14	/workspace/coverage/cover_reg_top/14.i2c_csr_rw.1482187336	Feb 04 12:44:46 PM PST 24	Feb 04 12:44:50 PM PST 24	34474414 ps
T9	/workspace/coverage/cover_reg_top/26.i2c_intr_test.154376052	Feb 04 12:45:03 PM PST 24	Feb 04 12:45:08 PM PST 24	55524175 ps
T22	/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2117036794	Feb 04 12:44:25 PM PST 24	Feb 04 12:44:27 PM PST 24	581131294 ps
T15	/workspace/coverage/cover_reg_top/11.i2c_tl_errors.2006509049	Feb 04 12:44:30 PM PST 24	Feb 04 12:44:33 PM PST 24	458732620 ps
T16	/workspace/coverage/cover_reg_top/8.i2c_tl_errors.2100005213	Feb 04 12:44:17 PM PST 24	Feb 04 12:44:19 PM PST 24	49064817 ps
T25	/workspace/coverage/cover_reg_top/0.i2c_csr_rw.4223384004	Feb 04 12:44:25 PM PST 24	Feb 04 12:44:27 PM PST 24	49164097 ps
T26	/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.201977954	Feb 04 12:44:30 PM PST 24	Feb 04 12:44:31 PM PST 24	98438048 ps
T10	/workspace/coverage/cover_reg_top/20.i2c_intr_test.3230899967	Feb 04 12:44:56 PM PST 24	Feb 04 12:44:57 PM PST 24	16618712 ps
T27	/workspace/coverage/cover_reg_top/15.i2c_csr_rw.2546419267	Feb 04 12:44:32 PM PST 24	Feb 04 12:44:34 PM PST 24	50938706 ps
T28	/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1788361887	Feb 04 12:44:22 PM PST 24	Feb 04 12:44:26 PM PST 24	842942665 ps
T11	/workspace/coverage/cover_reg_top/16.i2c_intr_test.325452687	Feb 04 12:44:45 PM PST 24	Feb 04 12:44:50 PM PST 24	48933960 ps
T29	/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.984902669	Feb 04 12:44:39 PM PST 24	Feb 04 12:44:44 PM PST 24	64135766 ps
T17	/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.406930697	Feb 04 12:44:30 PM PST 24	Feb 04 12:44:31 PM PST 24	68339608 ps
T59	/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2739724335	Feb 04 12:44:19 PM PST 24	Feb 04 12:44:21 PM PST 24	30896073 ps
T30	/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2755310927	Feb 04 12:44:32 PM PST 24	Feb 04 12:44:35 PM PST 24	23502302 ps
T49	/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3197861879	Feb 04 12:44:44 PM PST 24	Feb 04 12:44:50 PM PST 24	74220920 ps
T82	/workspace/coverage/cover_reg_top/1.i2c_csr_rw.4002730728	Feb 04 12:44:16 PM PST 24	Feb 04 12:44:18 PM PST 24	33726387 ps
T18	/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1694565760	Feb 04 12:44:37 PM PST 24	Feb 04 12:44:43 PM PST 24	216036298 ps
T19	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1179513390	Feb 04 12:44:22 PM PST 24	Feb 04 12:44:25 PM PST 24	278704313 ps
T20	/workspace/coverage/cover_reg_top/13.i2c_tl_errors.2511568239	Feb 04 12:44:37 PM PST 24	Feb 04 12:44:45 PM PST 24	302055526 ps
T12	/workspace/coverage/cover_reg_top/7.i2c_intr_test.1949152230	Feb 04 12:44:17 PM PST 24	Feb 04 12:44:19 PM PST 24	22613975 ps
T21	/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.320603310	Feb 04 12:44:44 PM PST 24	Feb 04 12:44:50 PM PST 24	24585610 ps
T50	/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3859571791	Feb 04 12:44:37 PM PST 24	Feb 04 12:44:43 PM PST 24	25456112 ps
T83	/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1349838218	Feb 04 12:44:36 PM PST 24	Feb 04 12:44:42 PM PST 24	28326996 ps
T23	/workspace/coverage/cover_reg_top/18.i2c_tl_errors.1869596643	Feb 04 12:44:33 PM PST 24	Feb 04 12:44:40 PM PST 24	164092766 ps
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T51	/workspace/coverage/cover_reg_top/2.i2c_csr_rw.1081821958	Feb 04 12:44:28 PM PST 24	Feb 04 12:44:29 PM PST 24	23515175 ps
T52	/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3190157081	Feb 04 12:44:40 PM PST 24	Feb 04 12:44:49 PM PST 24	57525120 ps
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T57	/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.4032507451	Feb 04 12:44:44 PM PST 24	Feb 04 12:44:51 PM PST 24	1164838423 ps
T31	/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2244627061	Feb 04 12:44:35 PM PST 24	Feb 04 12:44:41 PM PST 24	23806199 ps
T84	/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3976792984	Feb 04 12:44:29 PM PST 24	Feb 04 12:44:34 PM PST 24	458619893 ps
T66	/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1785175667	Feb 04 12:44:32 PM PST 24	Feb 04 12:44:36 PM PST 24	181521517 ps
T32	/workspace/coverage/cover_reg_top/10.i2c_csr_rw.3929447075	Feb 04 12:44:32 PM PST 24	Feb 04 12:44:33 PM PST 24	21515632 ps
T60	/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3494334608	Feb 04 12:44:44 PM PST 24	Feb 04 12:44:50 PM PST 24	32789210 ps
T85	/workspace/coverage/cover_reg_top/2.i2c_tl_errors.241674437	Feb 04 12:44:31 PM PST 24	Feb 04 12:44:35 PM PST 24	160465614 ps
T79	/workspace/coverage/cover_reg_top/17.i2c_intr_test.2035981350	Feb 04 12:44:35 PM PST 24	Feb 04 12:44:41 PM PST 24	18409110 ps
T86	/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.4187226920	Feb 04 12:44:29 PM PST 24	Feb 04 12:44:30 PM PST 24	58058980 ps
T81	/workspace/coverage/cover_reg_top/10.i2c_intr_test.3902993107	Feb 04 12:44:30 PM PST 24	Feb 04 12:44:31 PM PST 24	17425688 ps
T87	/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3182296587	Feb 04 12:44:16 PM PST 24	Feb 04 12:44:19 PM PST 24	55331110 ps
T88	/workspace/coverage/cover_reg_top/0.i2c_intr_test.3828405321	Feb 04 12:44:33 PM PST 24	Feb 04 12:44:38 PM PST 24	42604302 ps
T89	/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2092946169	Feb 04 12:44:55 PM PST 24	Feb 04 12:44:57 PM PST 24	40570302 ps
T80	/workspace/coverage/cover_reg_top/48.i2c_intr_test.1468661300	Feb 04 12:44:49 PM PST 24	Feb 04 12:44:51 PM PST 24	24681479 ps
T90	/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.737783806	Feb 04 12:44:39 PM PST 24	Feb 04 12:44:50 PM PST 24	18904924 ps
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T61	/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2275194665	Feb 04 12:44:26 PM PST 24	Feb 04 12:44:28 PM PST 24	42936954 ps
T92	/workspace/coverage/cover_reg_top/28.i2c_intr_test.3990491063	Feb 04 12:45:01 PM PST 24	Feb 04 12:45:08 PM PST 24	21279740 ps
T93	/workspace/coverage/cover_reg_top/0.i2c_tl_errors.3777167658	Feb 04 12:44:25 PM PST 24	Feb 04 12:44:28 PM PST 24	45208418 ps
T94	/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.997284398	Feb 04 12:44:39 PM PST 24	Feb 04 12:44:44 PM PST 24	33853053 ps
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T97	/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1067060552	Feb 04 12:44:35 PM PST 24	Feb 04 12:44:42 PM PST 24	279329478 ps
T67	/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.7187763	Feb 04 12:44:39 PM PST 24	Feb 04 12:44:44 PM PST 24	112055757 ps
T98	/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2385181386	Feb 04 12:44:35 PM PST 24	Feb 04 12:44:42 PM PST 24	82044305 ps
T33	/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.951107963	Feb 04 12:44:31 PM PST 24	Feb 04 12:44:33 PM PST 24	111206370 ps
T44	/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1636464267	Feb 04 12:45:02 PM PST 24	Feb 04 12:45:08 PM PST 24	99607673 ps
T45	/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3515004789	Feb 04 12:44:37 PM PST 24	Feb 04 12:44:43 PM PST 24	69785876 ps
T46	/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2792451689	Feb 04 12:44:36 PM PST 24	Feb 04 12:44:42 PM PST 24	52716062 ps
T34	/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1755610338	Feb 04 12:44:33 PM PST 24	Feb 04 12:44:37 PM PST 24	24755980 ps
T47	/workspace/coverage/cover_reg_top/15.i2c_intr_test.1319089147	Feb 04 12:44:36 PM PST 24	Feb 04 12:44:42 PM PST 24	142500216 ps
T48	/workspace/coverage/cover_reg_top/12.i2c_intr_test.2562183882	Feb 04 12:44:37 PM PST 24	Feb 04 12:44:43 PM PST 24	17425833 ps
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T99	/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3130289213	Feb 04 12:44:36 PM PST 24	Feb 04 12:44:42 PM PST 24	55292085 ps
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T53	/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3643545193	Feb 04 12:44:31 PM PST 24	Feb 04 12:44:34 PM PST 24	131301807 ps
T100	/workspace/coverage/cover_reg_top/5.i2c_csr_rw.3312112922	Feb 04 12:44:33 PM PST 24	Feb 04 12:44:39 PM PST 24	25577402 ps
T63	/workspace/coverage/cover_reg_top/13.i2c_csr_rw.1334682396	Feb 04 12:44:35 PM PST 24	Feb 04 12:44:41 PM PST 24	19699048 ps
T101	/workspace/coverage/cover_reg_top/2.i2c_intr_test.568919477	Feb 04 12:44:36 PM PST 24	Feb 04 12:44:41 PM PST 24	35557173 ps
T102	/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.977707089	Feb 04 12:44:18 PM PST 24	Feb 04 12:44:20 PM PST 24	83815883 ps
T103	/workspace/coverage/cover_reg_top/6.i2c_tl_errors.1483051809	Feb 04 12:44:37 PM PST 24	Feb 04 12:44:44 PM PST 24	94439993 ps
T104	/workspace/coverage/cover_reg_top/30.i2c_intr_test.2429589081	Feb 04 12:45:00 PM PST 24	Feb 04 12:45:07 PM PST 24	35668641 ps
T105	/workspace/coverage/cover_reg_top/17.i2c_tl_errors.3623816127	Feb 04 12:44:35 PM PST 24	Feb 04 12:44:42 PM PST 24	838023055 ps
T106	/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.834929040	Feb 04 12:44:36 PM PST 24	Feb 04 12:44:42 PM PST 24	25626044 ps
T107	/workspace/coverage/cover_reg_top/15.i2c_tl_errors.4124614834	Feb 04 12:44:28 PM PST 24	Feb 04 12:44:31 PM PST 24	49245733 ps
T108	/workspace/coverage/cover_reg_top/23.i2c_intr_test.3910017624	Feb 04 12:45:06 PM PST 24	Feb 04 12:45:09 PM PST 24	16228476 ps
T64	/workspace/coverage/cover_reg_top/19.i2c_csr_rw.2014088392	Feb 04 12:45:00 PM PST 24	Feb 04 12:45:06 PM PST 24	112845598 ps
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T37	/workspace/coverage/cover_reg_top/11.i2c_csr_rw.2857241105	Feb 04 12:44:33 PM PST 24	Feb 04 12:44:38 PM PST 24	52967866 ps
T110	/workspace/coverage/cover_reg_top/44.i2c_intr_test.2318306603	Feb 04 12:44:46 PM PST 24	Feb 04 12:44:50 PM PST 24	25760678 ps
T75	/workspace/coverage/cover_reg_top/14.i2c_intr_test.1147858285	Feb 04 12:44:37 PM PST 24	Feb 04 12:44:42 PM PST 24	36390763 ps
T68	/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.76665595	Feb 04 12:44:34 PM PST 24	Feb 04 12:44:41 PM PST 24	66515903 ps
T111	/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1730920266	Feb 04 12:44:35 PM PST 24	Feb 04 12:44:41 PM PST 24	47626461 ps
T112	/workspace/coverage/cover_reg_top/41.i2c_intr_test.1215171831	Feb 04 12:45:14 PM PST 24	Feb 04 12:45:17 PM PST 24	42931663 ps
T113	/workspace/coverage/cover_reg_top/9.i2c_intr_test.2271267889	Feb 04 12:44:30 PM PST 24	Feb 04 12:44:32 PM PST 24	21665293 ps
T114	/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2606448871	Feb 04 12:44:25 PM PST 24	Feb 04 12:44:27 PM PST 24	33450532 ps
T115	/workspace/coverage/cover_reg_top/11.i2c_intr_test.997809205	Feb 04 12:44:38 PM PST 24	Feb 04 12:44:43 PM PST 24	74133452 ps
T116	/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.524911021	Feb 04 12:44:21 PM PST 24	Feb 04 12:44:24 PM PST 24	212867333 ps
T117	/workspace/coverage/cover_reg_top/45.i2c_intr_test.2510335951	Feb 04 12:45:04 PM PST 24	Feb 04 12:45:08 PM PST 24	201253163 ps
T118	/workspace/coverage/cover_reg_top/24.i2c_intr_test.2628957596	Feb 04 12:44:50 PM PST 24	Feb 04 12:44:52 PM PST 24	24631418 ps
T119	/workspace/coverage/cover_reg_top/3.i2c_tl_errors.942321047	Feb 04 12:44:32 PM PST 24	Feb 04 12:44:35 PM PST 24	60950413 ps
T54	/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2785572034	Feb 04 12:44:21 PM PST 24	Feb 04 12:44:24 PM PST 24	121453515 ps
T120	/workspace/coverage/cover_reg_top/37.i2c_intr_test.3523672309	Feb 04 12:45:03 PM PST 24	Feb 04 12:45:08 PM PST 24	23085772 ps
T121	/workspace/coverage/cover_reg_top/27.i2c_intr_test.1976048575	Feb 04 12:45:00 PM PST 24	Feb 04 12:45:07 PM PST 24	17919305 ps
T62	/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1476778163	Feb 04 12:44:35 PM PST 24	Feb 04 12:44:42 PM PST 24	220568095 ps
T122	/workspace/coverage/cover_reg_top/18.i2c_csr_rw.575291022	Feb 04 12:44:39 PM PST 24	Feb 04 12:44:44 PM PST 24	45957453 ps
T123	/workspace/coverage/cover_reg_top/8.i2c_csr_rw.1199284431	Feb 04 12:44:32 PM PST 24	Feb 04 12:44:37 PM PST 24	19176280 ps
T124	/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.448080374	Feb 04 12:44:28 PM PST 24	Feb 04 12:44:30 PM PST 24	17119493 ps
T125	/workspace/coverage/cover_reg_top/1.i2c_tl_errors.1054565484	Feb 04 12:44:21 PM PST 24	Feb 04 12:44:24 PM PST 24	334554396 ps
T38	/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.17700448	Feb 04 12:44:31 PM PST 24	Feb 04 12:44:33 PM PST 24	44433893 ps
T126	/workspace/coverage/cover_reg_top/19.i2c_tl_errors.659795702	Feb 04 12:44:57 PM PST 24	Feb 04 12:45:00 PM PST 24	278700832 ps
T127	/workspace/coverage/cover_reg_top/31.i2c_intr_test.53470702	Feb 04 12:45:06 PM PST 24	Feb 04 12:45:09 PM PST 24	25789952 ps
T128	/workspace/coverage/cover_reg_top/47.i2c_intr_test.3689144286	Feb 04 12:45:01 PM PST 24	Feb 04 12:45:08 PM PST 24	42697370 ps
T129	/workspace/coverage/cover_reg_top/10.i2c_tl_errors.2798041122	Feb 04 12:44:32 PM PST 24	Feb 04 12:44:36 PM PST 24	517535970 ps
T130	/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.475728565	Feb 04 12:44:37 PM PST 24	Feb 04 12:44:43 PM PST 24	68588404 ps
T39	/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.136435648	Feb 04 12:44:32 PM PST 24	Feb 04 12:44:38 PM PST 24	189221354 ps
T131	/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.712014980	Feb 04 12:44:38 PM PST 24	Feb 04 12:44:44 PM PST 24	72013285 ps
T132	/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1354103890	Feb 04 12:44:18 PM PST 24	Feb 04 12:44:20 PM PST 24	38375781 ps
T133	/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.4085357586	Feb 04 12:44:25 PM PST 24	Feb 04 12:44:27 PM PST 24	26597174 ps
T134	/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3678359350	Feb 04 12:44:28 PM PST 24	Feb 04 12:44:30 PM PST 24	27265749 ps
T40	/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3742645155	Feb 04 12:44:34 PM PST 24	Feb 04 12:44:41 PM PST 24	30166392 ps
T135	/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.923154949	Feb 04 12:44:44 PM PST 24	Feb 04 12:44:50 PM PST 24	33682769 ps
T136	/workspace/coverage/cover_reg_top/39.i2c_intr_test.843583309	Feb 04 12:45:01 PM PST 24	Feb 04 12:45:08 PM PST 24	21076293 ps
T137	/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3716060403	Feb 04 12:44:31 PM PST 24	Feb 04 12:44:33 PM PST 24	92141311 ps
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T140	/workspace/coverage/cover_reg_top/7.i2c_csr_rw.3998101676	Feb 04 12:44:19 PM PST 24	Feb 04 12:44:21 PM PST 24	72578531 ps
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T143	/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3481156703	Feb 04 12:44:34 PM PST 24	Feb 04 12:44:41 PM PST 24	37863650 ps
T144	/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1956799705	Feb 04 12:45:08 PM PST 24	Feb 04 12:45:10 PM PST 24	20541561 ps
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T146	/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3555470318	Feb 04 12:44:21 PM PST 24	Feb 04 12:44:24 PM PST 24	64807890 ps
T147	/workspace/coverage/cover_reg_top/3.i2c_intr_test.2117302785	Feb 04 12:44:33 PM PST 24	Feb 04 12:44:38 PM PST 24	21572704 ps
T148	/workspace/coverage/cover_reg_top/14.i2c_tl_errors.2500249585	Feb 04 12:44:33 PM PST 24	Feb 04 12:44:40 PM PST 24	337683113 ps
T149	/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.71824287	Feb 04 12:44:34 PM PST 24	Feb 04 12:44:40 PM PST 24	24908512 ps
T150	/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2747782519	Feb 04 12:44:35 PM PST 24	Feb 04 12:44:41 PM PST 24	43632810 ps
T41	/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2389200491	Feb 04 12:44:37 PM PST 24	Feb 04 12:44:44 PM PST 24	191112012 ps
T151	/workspace/coverage/cover_reg_top/7.i2c_tl_errors.454701460	Feb 04 12:44:30 PM PST 24	Feb 04 12:44:33 PM PST 24	176446197 ps
T152	/workspace/coverage/cover_reg_top/16.i2c_csr_rw.253614196	Feb 04 12:44:45 PM PST 24	Feb 04 12:44:50 PM PST 24	18595518 ps
T153	/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3940368162	Feb 04 12:44:36 PM PST 24	Feb 04 12:44:43 PM PST 24	278859486 ps
T154	/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2205649103	Feb 04 12:44:34 PM PST 24	Feb 04 12:44:39 PM PST 24	21107434 ps
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T156	/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2399422781	Feb 04 12:44:36 PM PST 24	Feb 04 12:44:42 PM PST 24	57136698 ps
T157	/workspace/coverage/cover_reg_top/43.i2c_intr_test.3180629324	Feb 04 12:44:57 PM PST 24	Feb 04 12:45:00 PM PST 24	17408670 ps
T158	/workspace/coverage/cover_reg_top/38.i2c_intr_test.4155909420	Feb 04 12:45:06 PM PST 24	Feb 04 12:45:08 PM PST 24	57099992 ps
T159	/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.4238179145	Feb 04 12:44:25 PM PST 24	Feb 04 12:44:27 PM PST 24	18371377 ps
T160	/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3890592155	Feb 04 12:44:32 PM PST 24	Feb 04 12:44:35 PM PST 24	24417365 ps
T161	/workspace/coverage/cover_reg_top/4.i2c_tl_errors.2429463824	Feb 04 12:44:31 PM PST 24	Feb 04 12:44:34 PM PST 24	54085163 ps
T162	/workspace/coverage/cover_reg_top/5.i2c_intr_test.364034182	Feb 04 12:44:33 PM PST 24	Feb 04 12:44:38 PM PST 24	26837775 ps
T163	/workspace/coverage/cover_reg_top/33.i2c_intr_test.3456613516	Feb 04 12:45:01 PM PST 24	Feb 04 12:45:08 PM PST 24	16679322 ps
T42	/workspace/coverage/cover_reg_top/12.i2c_csr_rw.3917996258	Feb 04 12:44:37 PM PST 24	Feb 04 12:44:43 PM PST 24	14886266 ps
T164	/workspace/coverage/cover_reg_top/40.i2c_intr_test.4041324828	Feb 04 12:45:04 PM PST 24	Feb 04 12:45:08 PM PST 24	16785638 ps
T43	/workspace/coverage/cover_reg_top/3.i2c_csr_rw.2417212929	Feb 04 12:44:27 PM PST 24	Feb 04 12:44:29 PM PST 24	23443089 ps
T165	/workspace/coverage/cover_reg_top/36.i2c_intr_test.3830496648	Feb 04 12:44:53 PM PST 24	Feb 04 12:44:54 PM PST 24	54370750 ps

Test location	/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.960372452
Short name	T6
Test name
Test status
Simulation time	534492316 ps
CPU time	1.84 seconds
Started	Feb 04 12:44:32 PM PST 24
Finished	Feb 04 12:44:38 PM PST 24
Peak memory	202580 kb
Host	smart-ee4f366e-5caa-4a7c-bb47-1c17d4b38e57
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960372452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.960372452
Directory	/workspace/2.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_intr_test.3331825177
Short name	T8
Test name
Test status
Simulation time	19286132 ps
CPU time	0.77 seconds
Started	Feb 04 12:44:32 PM PST 24
Finished	Feb 04 12:44:35 PM PST 24
Peak memory	202228 kb
Host	smart-b7edb89d-5a67-4681-87b0-e8149d372869
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331825177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.3331825177
Directory	/workspace/8.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_tl_errors.2006509049
Short name	T15
Test name
Test status
Simulation time	458732620 ps
CPU time	2.27 seconds
Started	Feb 04 12:44:30 PM PST 24
Finished	Feb 04 12:44:33 PM PST 24
Peak memory	202412 kb
Host	smart-ed2cbf2a-0179-433a-9e3f-38d95233005d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006509049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.2006509049
Directory	/workspace/11.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/25.i2c_intr_test.1207845125
Short name	T70
Test name
Test status
Simulation time	25356354 ps
CPU time	0.68 seconds
Started	Feb 04 12:45:07 PM PST 24
Finished	Feb 04 12:45:10 PM PST 24
Peak memory	202128 kb
Host	smart-f6d493d3-f686-4838-b02d-a08169a04ab3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207845125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1207845125
Directory	/workspace/25.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_csr_rw.2546419267
Short name	T27
Test name
Test status
Simulation time	50938706 ps
CPU time	0.71 seconds
Started	Feb 04 12:44:32 PM PST 24
Finished	Feb 04 12:44:34 PM PST 24
Peak memory	202328 kb
Host	smart-4b74a526-ab80-45ad-9640-22471a518bf4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546419267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.2546419267
Directory	/workspace/15.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.4219240286
Short name	T4
Test name
Test status
Simulation time	176067649 ps
CPU time	0.95 seconds
Started	Feb 04 12:44:35 PM PST 24
Finished	Feb 04 12:44:41 PM PST 24
Peak memory	202404 kb
Host	smart-7242a9d6-5fec-434f-9f50-3aa5c915cf86
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219240286 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.4219240286
Directory	/workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_intr_test.1250526486
Short name	T69
Test name
Test status
Simulation time	38702935 ps
CPU time	0.7 seconds
Started	Feb 04 12:44:38 PM PST 24
Finished	Feb 04 12:44:43 PM PST 24
Peak memory	202048 kb
Host	smart-8fde9792-d519-47b3-9385-7e52ace8af55
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250526486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.1250526486
Directory	/workspace/18.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3859571791
Short name	T50
Test name
Test status
Simulation time	25456112 ps
CPU time	0.78 seconds
Started	Feb 04 12:44:37 PM PST 24
Finished	Feb 04 12:44:43 PM PST 24
Peak memory	201896 kb
Host	smart-2eb2b648-7a73-4e53-9607-d1546ba6945d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859571791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou tstanding.3859571791
Directory	/workspace/5.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/26.i2c_intr_test.154376052
Short name	T9
Test name
Test status
Simulation time	55524175 ps
CPU time	0.67 seconds
Started	Feb 04 12:45:03 PM PST 24
Finished	Feb 04 12:45:08 PM PST 24
Peak memory	202216 kb
Host	smart-fa055e50-963d-4165-a244-0475a14d3c3a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154376052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.154376052
Directory	/workspace/26.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1476778163
Short name	T62
Test name
Test status
Simulation time	220568095 ps
CPU time	0.98 seconds
Started	Feb 04 12:44:35 PM PST 24
Finished	Feb 04 12:44:42 PM PST 24
Peak memory	202288 kb
Host	smart-ad01c6a8-5c41-4eea-8fb7-b1f3043d2c23
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476778163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o utstanding.1476778163
Directory	/workspace/10.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1179513390
Short name	T19
Test name
Test status
Simulation time	278704313 ps
CPU time	1.77 seconds
Started	Feb 04 12:44:22 PM PST 24
Finished	Feb 04 12:44:25 PM PST 24
Peak memory	202540 kb
Host	smart-d92f9938-aa42-4bbe-87dd-945216de9284
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179513390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.1179513390
Directory	/workspace/1.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2792451689
Short name	T46
Test name
Test status
Simulation time	52716062 ps
CPU time	1.22 seconds
Started	Feb 04 12:44:36 PM PST 24
Finished	Feb 04 12:44:42 PM PST 24
Peak memory	202348 kb
Host	smart-531f86e6-47a6-4180-9911-dcc18ae9789e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792451689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.2792451689
Directory	/workspace/15.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.189751657
Short name	T65
Test name
Test status
Simulation time	29587749 ps
CPU time	0.72 seconds
Started	Feb 04 12:44:19 PM PST 24
Finished	Feb 04 12:44:22 PM PST 24
Peak memory	202328 kb
Host	smart-7ffe6da6-9568-40c1-aa03-4fe9eb777616
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189751657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.189751657
Directory	/workspace/0.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_intr_test.1169467144
Short name	T7
Test name
Test status
Simulation time	19871561 ps
CPU time	0.64 seconds
Started	Feb 04 12:44:30 PM PST 24
Finished	Feb 04 12:44:32 PM PST 24
Peak memory	202172 kb
Host	smart-cd491886-1edb-4131-b33e-e10a478b3d5c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169467144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1169467144
Directory	/workspace/6.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2488661754
Short name	T56
Test name
Test status
Simulation time	138838249 ps
CPU time	1.23 seconds
Started	Feb 04 12:44:20 PM PST 24
Finished	Feb 04 12:44:23 PM PST 24
Peak memory	202496 kb
Host	smart-8d42b286-68ff-44ee-b5f8-fb735fed95ee
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488661754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.2488661754
Directory	/workspace/0.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.4032507451
Short name	T57
Test name
Test status
Simulation time	1164838423 ps
CPU time	1.89 seconds
Started	Feb 04 12:44:44 PM PST 24
Finished	Feb 04 12:44:51 PM PST 24
Peak memory	202472 kb
Host	smart-f6fd3789-6f58-445b-a867-b59e785a16a0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032507451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.4032507451
Directory	/workspace/12.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.524911021
Short name	T116
Test name
Test status
Simulation time	212867333 ps
CPU time	1.09 seconds
Started	Feb 04 12:44:21 PM PST 24
Finished	Feb 04 12:44:24 PM PST 24
Peak memory	202508 kb
Host	smart-52ab0570-12ed-4ece-9052-37718a776a43
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524911021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_out standing.524911021
Directory	/workspace/0.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1785175667
Short name	T66
Test name
Test status
Simulation time	181521517 ps
CPU time	1.2 seconds
Started	Feb 04 12:44:32 PM PST 24
Finished	Feb 04 12:44:36 PM PST 24
Peak memory	202488 kb
Host	smart-101558f3-2098-477e-957b-66822ff8d7ad
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785175667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1785175667
Directory	/workspace/10.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1354103890
Short name	T132
Test name
Test status
Simulation time	38375781 ps
CPU time	0.97 seconds
Started	Feb 04 12:44:18 PM PST 24
Finished	Feb 04 12:44:20 PM PST 24
Peak memory	202256 kb
Host	smart-45df29e7-ab45-4a72-8c55-1c5e5621b749
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354103890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1354103890
Directory	/workspace/0.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1788361887
Short name	T28
Test name
Test status
Simulation time	842942665 ps
CPU time	2.56 seconds
Started	Feb 04 12:44:22 PM PST 24
Finished	Feb 04 12:44:26 PM PST 24
Peak memory	202456 kb
Host	smart-0d68e8ef-e0e2-43b0-a601-ce799bfc6896
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788361887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.1788361887
Directory	/workspace/0.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3555470318
Short name	T146
Test name
Test status
Simulation time	64807890 ps
CPU time	1.17 seconds
Started	Feb 04 12:44:21 PM PST 24
Finished	Feb 04 12:44:24 PM PST 24
Peak memory	202528 kb
Host	smart-38b5a2ad-ef51-42b1-bd98-308f0e8c0c5d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555470318 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.3555470318
Directory	/workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_rw.4223384004
Short name	T25
Test name
Test status
Simulation time	49164097 ps
CPU time	0.71 seconds
Started	Feb 04 12:44:25 PM PST 24
Finished	Feb 04 12:44:27 PM PST 24
Peak memory	202308 kb
Host	smart-994b9c7b-d75c-4fa3-8a55-cb63d961fcbc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223384004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.4223384004
Directory	/workspace/0.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_intr_test.3828405321
Short name	T88
Test name
Test status
Simulation time	42604302 ps
CPU time	0.66 seconds
Started	Feb 04 12:44:33 PM PST 24
Finished	Feb 04 12:44:38 PM PST 24
Peak memory	202200 kb
Host	smart-7445fe8f-704c-470d-8b97-9adfdc338ddc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828405321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3828405321
Directory	/workspace/0.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_tl_errors.3777167658
Short name	T93
Test name
Test status
Simulation time	45208418 ps
CPU time	2.11 seconds
Started	Feb 04 12:44:25 PM PST 24
Finished	Feb 04 12:44:28 PM PST 24
Peak memory	202512 kb
Host	smart-7e87dd20-7642-48ff-a5b0-10b52cdc9c78
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777167658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.3777167658
Directory	/workspace/0.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2117036794
Short name	T22
Test name
Test status
Simulation time	581131294 ps
CPU time	0.88 seconds
Started	Feb 04 12:44:25 PM PST 24
Finished	Feb 04 12:44:27 PM PST 24
Peak memory	202328 kb
Host	smart-c1cac50c-e729-412c-8468-d31ecd5b51ef
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117036794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.2117036794
Directory	/workspace/1.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3182296587
Short name	T87
Test name
Test status
Simulation time	55331110 ps
CPU time	2.16 seconds
Started	Feb 04 12:44:16 PM PST 24
Finished	Feb 04 12:44:19 PM PST 24
Peak memory	202476 kb
Host	smart-ba770ad0-e83c-4d39-9abb-670fce170251
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182296587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.3182296587
Directory	/workspace/1.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.4238179145
Short name	T159
Test name
Test status
Simulation time	18371377 ps
CPU time	0.65 seconds
Started	Feb 04 12:44:25 PM PST 24
Finished	Feb 04 12:44:27 PM PST 24
Peak memory	202136 kb
Host	smart-533c7abd-bb73-4cbf-90fb-4c6ebcb569cf
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238179145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.4238179145
Directory	/workspace/1.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3678359350
Short name	T134
Test name
Test status
Simulation time	27265749 ps
CPU time	0.71 seconds
Started	Feb 04 12:44:28 PM PST 24
Finished	Feb 04 12:44:30 PM PST 24
Peak memory	202380 kb
Host	smart-6389c184-9b6c-417b-b71a-ac99dc43d576
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678359350 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.3678359350
Directory	/workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_rw.4002730728
Short name	T82
Test name
Test status
Simulation time	33726387 ps
CPU time	0.7 seconds
Started	Feb 04 12:44:16 PM PST 24
Finished	Feb 04 12:44:18 PM PST 24
Peak memory	202324 kb
Host	smart-1371b28e-fcd8-498b-815b-3985b12f8f66
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002730728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.4002730728
Directory	/workspace/1.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_intr_test.537523322
Short name	T145
Test name
Test status
Simulation time	150939270 ps
CPU time	0.68 seconds
Started	Feb 04 12:44:26 PM PST 24
Finished	Feb 04 12:44:28 PM PST 24
Peak memory	202228 kb
Host	smart-a45711ef-367d-4125-934d-f15bb65bc4d4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537523322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.537523322
Directory	/workspace/1.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2606448871
Short name	T114
Test name
Test status
Simulation time	33450532 ps
CPU time	0.87 seconds
Started	Feb 04 12:44:25 PM PST 24
Finished	Feb 04 12:44:27 PM PST 24
Peak memory	202308 kb
Host	smart-cd6292ef-2473-4b51-aea8-603d44afb555
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606448871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou tstanding.2606448871
Directory	/workspace/1.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_tl_errors.1054565484
Short name	T125
Test name
Test status
Simulation time	334554396 ps
CPU time	2.18 seconds
Started	Feb 04 12:44:21 PM PST 24
Finished	Feb 04 12:44:24 PM PST 24
Peak memory	202600 kb
Host	smart-f95a6677-b400-4d33-9774-8461da5497c8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054565484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.1054565484
Directory	/workspace/1.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3716060403
Short name	T137
Test name
Test status
Simulation time	92141311 ps
CPU time	0.87 seconds
Started	Feb 04 12:44:31 PM PST 24
Finished	Feb 04 12:44:33 PM PST 24
Peak memory	202416 kb
Host	smart-f73cd45c-1080-49ca-970b-55bd308d246f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716060403 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.3716060403
Directory	/workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_csr_rw.3929447075
Short name	T32
Test name
Test status
Simulation time	21515632 ps
CPU time	0.64 seconds
Started	Feb 04 12:44:32 PM PST 24
Finished	Feb 04 12:44:33 PM PST 24
Peak memory	201356 kb
Host	smart-61aa1a9e-2c53-4699-a7ff-61ff11aac11a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929447075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3929447075
Directory	/workspace/10.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_intr_test.3902993107
Short name	T81
Test name
Test status
Simulation time	17425688 ps
CPU time	0.62 seconds
Started	Feb 04 12:44:30 PM PST 24
Finished	Feb 04 12:44:31 PM PST 24
Peak memory	202228 kb
Host	smart-aa118e0b-3fce-4a42-94e8-8f351f6a1ce4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902993107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3902993107
Directory	/workspace/10.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_tl_errors.2798041122
Short name	T129
Test name
Test status
Simulation time	517535970 ps
CPU time	2.79 seconds
Started	Feb 04 12:44:32 PM PST 24
Finished	Feb 04 12:44:36 PM PST 24
Peak memory	202564 kb
Host	smart-dfdab4d2-3bb7-44c6-9c54-536122ab86f6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798041122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.2798041122
Directory	/workspace/10.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.320603310
Short name	T21
Test name
Test status
Simulation time	24585610 ps
CPU time	1.17 seconds
Started	Feb 04 12:44:44 PM PST 24
Finished	Feb 04 12:44:50 PM PST 24
Peak memory	202564 kb
Host	smart-b08d4414-a791-43fe-a2e2-ebc7c9d23fe4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320603310 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.320603310
Directory	/workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_csr_rw.2857241105
Short name	T37
Test name
Test status
Simulation time	52967866 ps
CPU time	0.65 seconds
Started	Feb 04 12:44:33 PM PST 24
Finished	Feb 04 12:44:38 PM PST 24
Peak memory	202332 kb
Host	smart-ba573ab5-dc63-455b-9978-3a4c9e817975
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857241105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2857241105
Directory	/workspace/11.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_intr_test.997809205
Short name	T115
Test name
Test status
Simulation time	74133452 ps
CPU time	0.63 seconds
Started	Feb 04 12:44:38 PM PST 24
Finished	Feb 04 12:44:43 PM PST 24
Peak memory	202232 kb
Host	smart-d360f0c8-f904-4d23-a6cc-b3e9097eeaf5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997809205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.997809205
Directory	/workspace/11.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3190157081
Short name	T52
Test name
Test status
Simulation time	57525120 ps
CPU time	0.81 seconds
Started	Feb 04 12:44:40 PM PST 24
Finished	Feb 04 12:44:49 PM PST 24
Peak memory	202348 kb
Host	smart-9af0a045-9fab-45b0-a8ce-163850a51e99
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190157081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o utstanding.3190157081
Directory	/workspace/11.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1694565760
Short name	T18
Test name
Test status
Simulation time	216036298 ps
CPU time	1.24 seconds
Started	Feb 04 12:44:37 PM PST 24
Finished	Feb 04 12:44:43 PM PST 24
Peak memory	202428 kb
Host	smart-e0dd216c-d057-4980-9ca5-f37c300edf5e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694565760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.1694565760
Directory	/workspace/11.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.4187226920
Short name	T86
Test name
Test status
Simulation time	58058980 ps
CPU time	0.74 seconds
Started	Feb 04 12:44:29 PM PST 24
Finished	Feb 04 12:44:30 PM PST 24
Peak memory	202364 kb
Host	smart-be510450-a232-49a2-aba4-d86f703c2535
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187226920 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.4187226920
Directory	/workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_csr_rw.3917996258
Short name	T42
Test name
Test status
Simulation time	14886266 ps
CPU time	0.63 seconds
Started	Feb 04 12:44:37 PM PST 24
Finished	Feb 04 12:44:43 PM PST 24
Peak memory	202284 kb
Host	smart-bceb8d4e-1e63-44b1-84b5-5c36d378b6a3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917996258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.3917996258
Directory	/workspace/12.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_intr_test.2562183882
Short name	T48
Test name
Test status
Simulation time	17425833 ps
CPU time	0.67 seconds
Started	Feb 04 12:44:37 PM PST 24
Finished	Feb 04 12:44:43 PM PST 24
Peak memory	202048 kb
Host	smart-abee1786-deac-481f-a57f-c31ee2284aa8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562183882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2562183882
Directory	/workspace/12.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2275194665
Short name	T61
Test name
Test status
Simulation time	42936954 ps
CPU time	0.89 seconds
Started	Feb 04 12:44:26 PM PST 24
Finished	Feb 04 12:44:28 PM PST 24
Peak memory	202276 kb
Host	smart-b4fd914f-f058-4ba7-823a-86e215f93eb5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275194665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o utstanding.2275194665
Directory	/workspace/12.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_tl_errors.2955172236
Short name	T155
Test name
Test status
Simulation time	82413684 ps
CPU time	1.66 seconds
Started	Feb 04 12:44:28 PM PST 24
Finished	Feb 04 12:44:30 PM PST 24
Peak memory	202484 kb
Host	smart-21836e04-6dcc-4b7d-a58a-e4c8b3396d34
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955172236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.2955172236
Directory	/workspace/12.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.923154949
Short name	T135
Test name
Test status
Simulation time	33682769 ps
CPU time	0.75 seconds
Started	Feb 04 12:44:44 PM PST 24
Finished	Feb 04 12:44:50 PM PST 24
Peak memory	202352 kb
Host	smart-eb4ccd00-024a-4b4f-a697-246a630c519f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923154949 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.923154949
Directory	/workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_csr_rw.1334682396
Short name	T63
Test name
Test status
Simulation time	19699048 ps
CPU time	0.72 seconds
Started	Feb 04 12:44:35 PM PST 24
Finished	Feb 04 12:44:41 PM PST 24
Peak memory	202236 kb
Host	smart-668f2ca9-811e-433c-8636-d7f3c67b504a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334682396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1334682396
Directory	/workspace/13.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_intr_test.1860641020
Short name	T74
Test name
Test status
Simulation time	32504072 ps
CPU time	0.67 seconds
Started	Feb 04 12:44:35 PM PST 24
Finished	Feb 04 12:44:41 PM PST 24
Peak memory	202184 kb
Host	smart-3b867903-8f79-47af-b1a0-9b4e37658b6e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860641020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1860641020
Directory	/workspace/13.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.834929040
Short name	T106
Test name
Test status
Simulation time	25626044 ps
CPU time	0.74 seconds
Started	Feb 04 12:44:36 PM PST 24
Finished	Feb 04 12:44:42 PM PST 24
Peak memory	202292 kb
Host	smart-7e051326-a038-481a-9297-5220b8f01998
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834929040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_ou tstanding.834929040
Directory	/workspace/13.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_tl_errors.2511568239
Short name	T20
Test name
Test status
Simulation time	302055526 ps
CPU time	2.71 seconds
Started	Feb 04 12:44:37 PM PST 24
Finished	Feb 04 12:44:45 PM PST 24
Peak memory	202520 kb
Host	smart-89677f5a-a7b2-4b3d-bab0-81c3231ee004
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511568239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2511568239
Directory	/workspace/13.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.712014980
Short name	T131
Test name
Test status
Simulation time	72013285 ps
CPU time	1.73 seconds
Started	Feb 04 12:44:38 PM PST 24
Finished	Feb 04 12:44:44 PM PST 24
Peak memory	202436 kb
Host	smart-dd94ecd7-d4a3-4246-8241-7e2e1196b93f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712014980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.712014980
Directory	/workspace/13.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.69744849
Short name	T13
Test name
Test status
Simulation time	189418768 ps
CPU time	0.83 seconds
Started	Feb 04 12:44:33 PM PST 24
Finished	Feb 04 12:44:38 PM PST 24
Peak memory	202412 kb
Host	smart-f26d4395-651a-4b9e-9928-e1a671a99072
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69744849 -assert nopostproc +UVM_TESTNAME=i 2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.69744849
Directory	/workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_csr_rw.1482187336
Short name	T14
Test name
Test status
Simulation time	34474414 ps
CPU time	0.66 seconds
Started	Feb 04 12:44:46 PM PST 24
Finished	Feb 04 12:44:50 PM PST 24
Peak memory	201412 kb
Host	smart-bfd3322c-0fd6-4ee6-99da-00891b915973
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482187336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.1482187336
Directory	/workspace/14.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_intr_test.1147858285
Short name	T75
Test name
Test status
Simulation time	36390763 ps
CPU time	0.66 seconds
Started	Feb 04 12:44:37 PM PST 24
Finished	Feb 04 12:44:42 PM PST 24
Peak memory	202052 kb
Host	smart-91172014-096c-4c62-8cdd-dc344f1d3fcb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147858285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1147858285
Directory	/workspace/14.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.475728565
Short name	T130
Test name
Test status
Simulation time	68588404 ps
CPU time	0.95 seconds
Started	Feb 04 12:44:37 PM PST 24
Finished	Feb 04 12:44:43 PM PST 24
Peak memory	202244 kb
Host	smart-05cef21f-8b72-45bb-94e8-970a8bf0b41b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475728565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_ou tstanding.475728565
Directory	/workspace/14.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_tl_errors.2500249585
Short name	T148
Test name
Test status
Simulation time	337683113 ps
CPU time	2.09 seconds
Started	Feb 04 12:44:33 PM PST 24
Finished	Feb 04 12:44:40 PM PST 24
Peak memory	202512 kb
Host	smart-cd684018-fd44-412f-a24a-c2da939e45f4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500249585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.2500249585
Directory	/workspace/14.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3301660439
Short name	T95
Test name
Test status
Simulation time	161773134 ps
CPU time	1.14 seconds
Started	Feb 04 12:44:34 PM PST 24
Finished	Feb 04 12:44:40 PM PST 24
Peak memory	202432 kb
Host	smart-168f5220-8332-4a79-90d6-7891d3852045
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301660439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.3301660439
Directory	/workspace/14.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1349838218
Short name	T83
Test name
Test status
Simulation time	28326996 ps
CPU time	0.77 seconds
Started	Feb 04 12:44:36 PM PST 24
Finished	Feb 04 12:44:42 PM PST 24
Peak memory	202348 kb
Host	smart-5bccb1e0-9385-487b-bf36-e1b80a50064d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349838218 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.1349838218
Directory	/workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_intr_test.1319089147
Short name	T47
Test name
Test status
Simulation time	142500216 ps
CPU time	0.68 seconds
Started	Feb 04 12:44:36 PM PST 24
Finished	Feb 04 12:44:42 PM PST 24
Peak memory	201908 kb
Host	smart-b70c8820-70ea-4702-8907-ecc3c350c414
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319089147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1319089147
Directory	/workspace/15.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2205649103
Short name	T154
Test name
Test status
Simulation time	21107434 ps
CPU time	0.75 seconds
Started	Feb 04 12:44:34 PM PST 24
Finished	Feb 04 12:44:39 PM PST 24
Peak memory	202248 kb
Host	smart-33db21fc-d75d-404f-8fc9-98930b282040
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205649103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o utstanding.2205649103
Directory	/workspace/15.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_tl_errors.4124614834
Short name	T107
Test name
Test status
Simulation time	49245733 ps
CPU time	2.43 seconds
Started	Feb 04 12:44:28 PM PST 24
Finished	Feb 04 12:44:31 PM PST 24
Peak memory	202508 kb
Host	smart-087e5450-2dc9-4977-815d-687f481ccc4f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124614834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.4124614834
Directory	/workspace/15.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3758813398
Short name	T1
Test name
Test status
Simulation time	27279295 ps
CPU time	1.27 seconds
Started	Feb 04 12:44:38 PM PST 24
Finished	Feb 04 12:44:44 PM PST 24
Peak memory	202492 kb
Host	smart-3522588e-b112-4301-aa54-79d94ffeb896
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758813398 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.3758813398
Directory	/workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_csr_rw.253614196
Short name	T152
Test name
Test status
Simulation time	18595518 ps
CPU time	0.7 seconds
Started	Feb 04 12:44:45 PM PST 24
Finished	Feb 04 12:44:50 PM PST 24
Peak memory	202288 kb
Host	smart-59231700-4ceb-46d4-83e4-9c3944a9af62
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253614196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.253614196
Directory	/workspace/16.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_intr_test.325452687
Short name	T11
Test name
Test status
Simulation time	48933960 ps
CPU time	0.63 seconds
Started	Feb 04 12:44:45 PM PST 24
Finished	Feb 04 12:44:50 PM PST 24
Peak memory	202196 kb
Host	smart-3f33a2f0-a5ed-4b01-9ac8-559ffba7a4d1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325452687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.325452687
Directory	/workspace/16.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2399422781
Short name	T156
Test name
Test status
Simulation time	57136698 ps
CPU time	0.75 seconds
Started	Feb 04 12:44:36 PM PST 24
Finished	Feb 04 12:44:42 PM PST 24
Peak memory	202144 kb
Host	smart-cd318d7c-7f1f-47fe-a7f9-2a930e664db0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399422781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o utstanding.2399422781
Directory	/workspace/16.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_tl_errors.2465719
Short name	T141
Test name
Test status
Simulation time	115273417 ps
CPU time	2.12 seconds
Started	Feb 04 12:44:34 PM PST 24
Finished	Feb 04 12:44:41 PM PST 24
Peak memory	202556 kb
Host	smart-0f9f4f73-f1e4-4c22-803f-c02454c982c3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.2465719
Directory	/workspace/16.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.76665595
Short name	T68
Test name
Test status
Simulation time	66515903 ps
CPU time	1.2 seconds
Started	Feb 04 12:44:34 PM PST 24
Finished	Feb 04 12:44:41 PM PST 24
Peak memory	202432 kb
Host	smart-f5195fa9-7261-4193-a1c6-d99558d475ac
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76665595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.76665595
Directory	/workspace/16.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.71824287
Short name	T149
Test name
Test status
Simulation time	24908512 ps
CPU time	0.69 seconds
Started	Feb 04 12:44:34 PM PST 24
Finished	Feb 04 12:44:40 PM PST 24
Peak memory	202380 kb
Host	smart-a71e6bdd-c296-4a54-beb4-baac630a2490
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71824287 -assert nopostproc +UVM_TESTNAME=i 2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.71824287
Directory	/workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_csr_rw.2841190063
Short name	T2
Test name
Test status
Simulation time	17310674 ps
CPU time	0.64 seconds
Started	Feb 04 12:44:45 PM PST 24
Finished	Feb 04 12:44:50 PM PST 24
Peak memory	202288 kb
Host	smart-59919e6d-0fdf-40f3-a3c4-1bd0de564b0f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841190063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.2841190063
Directory	/workspace/17.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_intr_test.2035981350
Short name	T79
Test name
Test status
Simulation time	18409110 ps
CPU time	0.63 seconds
Started	Feb 04 12:44:35 PM PST 24
Finished	Feb 04 12:44:41 PM PST 24
Peak memory	202224 kb
Host	smart-05a278c5-61d0-4639-ac41-f1abee1e2ba5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035981350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2035981350
Directory	/workspace/17.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3494334608
Short name	T60
Test name
Test status
Simulation time	32789210 ps
CPU time	0.84 seconds
Started	Feb 04 12:44:44 PM PST 24
Finished	Feb 04 12:44:50 PM PST 24
Peak memory	202276 kb
Host	smart-fda7c9e9-46ec-4fda-9984-020de2ab1022
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494334608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o utstanding.3494334608
Directory	/workspace/17.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_tl_errors.3623816127
Short name	T105
Test name
Test status
Simulation time	838023055 ps
CPU time	1.34 seconds
Started	Feb 04 12:44:35 PM PST 24
Finished	Feb 04 12:44:42 PM PST 24
Peak memory	202584 kb
Host	smart-fe3b69f6-871b-440d-9785-3107c31558ac
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623816127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3623816127
Directory	/workspace/17.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.7187763
Short name	T67
Test name
Test status
Simulation time	112055757 ps
CPU time	1.21 seconds
Started	Feb 04 12:44:39 PM PST 24
Finished	Feb 04 12:44:44 PM PST 24
Peak memory	202440 kb
Host	smart-f85c7ee9-c654-4c34-b7c5-d98ed8da4948
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7187763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.7187763
Directory	/workspace/17.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1636464267
Short name	T44
Test name
Test status
Simulation time	99607673 ps
CPU time	1.24 seconds
Started	Feb 04 12:45:02 PM PST 24
Finished	Feb 04 12:45:08 PM PST 24
Peak memory	202524 kb
Host	smart-7b20c5ef-7779-472c-831c-0cb5dd0d41ea
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636464267 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1636464267
Directory	/workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_csr_rw.575291022
Short name	T122
Test name
Test status
Simulation time	45957453 ps
CPU time	0.67 seconds
Started	Feb 04 12:44:39 PM PST 24
Finished	Feb 04 12:44:44 PM PST 24
Peak memory	202316 kb
Host	smart-e0f7ddec-92a9-413f-997c-41d456a375b5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575291022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.575291022
Directory	/workspace/18.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3197861879
Short name	T49
Test name
Test status
Simulation time	74220920 ps
CPU time	0.93 seconds
Started	Feb 04 12:44:44 PM PST 24
Finished	Feb 04 12:44:50 PM PST 24
Peak memory	202448 kb
Host	smart-015c0237-ce23-41cd-a179-8237bc7a5f42
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197861879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o utstanding.3197861879
Directory	/workspace/18.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_tl_errors.1869596643
Short name	T23
Test name
Test status
Simulation time	164092766 ps
CPU time	1.99 seconds
Started	Feb 04 12:44:33 PM PST 24
Finished	Feb 04 12:44:40 PM PST 24
Peak memory	202508 kb
Host	smart-b801c205-46e3-4b70-b273-9a1089beb729
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869596643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.1869596643
Directory	/workspace/18.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3281382382
Short name	T24
Test name
Test status
Simulation time	359645392 ps
CPU time	1.7 seconds
Started	Feb 04 12:44:38 PM PST 24
Finished	Feb 04 12:44:44 PM PST 24
Peak memory	202440 kb
Host	smart-0d3c4bfc-2857-4453-a40b-a49671536242
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281382382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.3281382382
Directory	/workspace/18.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2092946169
Short name	T89
Test name
Test status
Simulation time	40570302 ps
CPU time	0.71 seconds
Started	Feb 04 12:44:55 PM PST 24
Finished	Feb 04 12:44:57 PM PST 24
Peak memory	202412 kb
Host	smart-ac3bf651-25cb-4c90-898b-557f7785f123
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092946169 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2092946169
Directory	/workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_csr_rw.2014088392
Short name	T64
Test name
Test status
Simulation time	112845598 ps
CPU time	0.63 seconds
Started	Feb 04 12:45:00 PM PST 24
Finished	Feb 04 12:45:06 PM PST 24
Peak memory	201524 kb
Host	smart-2e9dde30-9aba-4204-9889-a359dd877c48
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014088392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2014088392
Directory	/workspace/19.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_intr_test.4118775688
Short name	T77
Test name
Test status
Simulation time	167841895 ps
CPU time	0.64 seconds
Started	Feb 04 12:44:59 PM PST 24
Finished	Feb 04 12:45:01 PM PST 24
Peak memory	202152 kb
Host	smart-16fbd3cb-c40c-4498-9b20-be7fa11ec18e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118775688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.4118775688
Directory	/workspace/19.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1956799705
Short name	T144
Test name
Test status
Simulation time	20541561 ps
CPU time	0.76 seconds
Started	Feb 04 12:45:08 PM PST 24
Finished	Feb 04 12:45:10 PM PST 24
Peak memory	202476 kb
Host	smart-c4a53d66-d726-4638-a150-45c82a353073
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956799705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o utstanding.1956799705
Directory	/workspace/19.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_tl_errors.659795702
Short name	T126
Test name
Test status
Simulation time	278700832 ps
CPU time	1.42 seconds
Started	Feb 04 12:44:57 PM PST 24
Finished	Feb 04 12:45:00 PM PST 24
Peak memory	202416 kb
Host	smart-93b2b641-0507-4336-af35-82c03658e6e2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659795702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.659795702
Directory	/workspace/19.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2897931938
Short name	T55
Test name
Test status
Simulation time	217528017 ps
CPU time	1.3 seconds
Started	Feb 04 12:45:06 PM PST 24
Finished	Feb 04 12:45:08 PM PST 24
Peak memory	202404 kb
Host	smart-6a4c4900-c735-49b6-aa7e-a717e49a316a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897931938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.2897931938
Directory	/workspace/19.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.17700448
Short name	T38
Test name
Test status
Simulation time	44433893 ps
CPU time	0.98 seconds
Started	Feb 04 12:44:31 PM PST 24
Finished	Feb 04 12:44:33 PM PST 24
Peak memory	202356 kb
Host	smart-5efdf845-6fe2-4f77-b13a-b9d0c4d80436
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17700448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.17700448
Directory	/workspace/2.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3976792984
Short name	T84
Test name
Test status
Simulation time	458619893 ps
CPU time	4.34 seconds
Started	Feb 04 12:44:29 PM PST 24
Finished	Feb 04 12:44:34 PM PST 24
Peak memory	202504 kb
Host	smart-80fe8662-8638-4887-ba51-a74639ae9f60
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976792984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.3976792984
Directory	/workspace/2.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.448080374
Short name	T124
Test name
Test status
Simulation time	17119493 ps
CPU time	0.64 seconds
Started	Feb 04 12:44:28 PM PST 24
Finished	Feb 04 12:44:30 PM PST 24
Peak memory	201152 kb
Host	smart-938a4845-968b-4ba1-98fa-cd9ebfc09fd7
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448080374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.448080374
Directory	/workspace/2.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.406930697
Short name	T17
Test name
Test status
Simulation time	68339608 ps
CPU time	1.02 seconds
Started	Feb 04 12:44:30 PM PST 24
Finished	Feb 04 12:44:31 PM PST 24
Peak memory	202332 kb
Host	smart-b9c7dc53-b26b-4c79-98fd-50c4623cf053
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406930697 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.406930697
Directory	/workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_rw.1081821958
Short name	T51
Test name
Test status
Simulation time	23515175 ps
CPU time	0.67 seconds
Started	Feb 04 12:44:28 PM PST 24
Finished	Feb 04 12:44:29 PM PST 24
Peak memory	202100 kb
Host	smart-ba9db30d-16c8-4a60-bbc0-a824f25def62
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081821958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.1081821958
Directory	/workspace/2.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_intr_test.568919477
Short name	T101
Test name
Test status
Simulation time	35557173 ps
CPU time	0.63 seconds
Started	Feb 04 12:44:36 PM PST 24
Finished	Feb 04 12:44:41 PM PST 24
Peak memory	202164 kb
Host	smart-0acd6bbf-de6d-4392-b74b-9b9cfe8fb482
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568919477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.568919477
Directory	/workspace/2.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2755310927
Short name	T30
Test name
Test status
Simulation time	23502302 ps
CPU time	0.91 seconds
Started	Feb 04 12:44:32 PM PST 24
Finished	Feb 04 12:44:35 PM PST 24
Peak memory	202484 kb
Host	smart-e8929157-9069-4a90-9c38-535d8cb43777
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755310927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou tstanding.2755310927
Directory	/workspace/2.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_tl_errors.241674437
Short name	T85
Test name
Test status
Simulation time	160465614 ps
CPU time	3.07 seconds
Started	Feb 04 12:44:31 PM PST 24
Finished	Feb 04 12:44:35 PM PST 24
Peak memory	202516 kb
Host	smart-6e8226bf-9242-4a08-a1cf-2c0a023758ea
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241674437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.241674437
Directory	/workspace/2.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/20.i2c_intr_test.3230899967
Short name	T10
Test name
Test status
Simulation time	16618712 ps
CPU time	0.65 seconds
Started	Feb 04 12:44:56 PM PST 24
Finished	Feb 04 12:44:57 PM PST 24
Peak memory	202160 kb
Host	smart-be61a54e-eb51-42e7-ab84-a6256fdd751a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230899967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.3230899967
Directory	/workspace/20.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.i2c_intr_test.4054838150
Short name	T138
Test name
Test status
Simulation time	57162158 ps
CPU time	0.66 seconds
Started	Feb 04 12:45:04 PM PST 24
Finished	Feb 04 12:45:08 PM PST 24
Peak memory	202208 kb
Host	smart-e99ce49f-f28b-4a32-8001-3c40e562e47f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054838150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.4054838150
Directory	/workspace/21.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.i2c_intr_test.1970761314
Short name	T91
Test name
Test status
Simulation time	51185574 ps
CPU time	0.64 seconds
Started	Feb 04 12:44:53 PM PST 24
Finished	Feb 04 12:44:55 PM PST 24
Peak memory	202160 kb
Host	smart-a5d74e8f-d8b9-4465-b880-e75c7e9145e4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970761314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1970761314
Directory	/workspace/22.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.i2c_intr_test.3910017624
Short name	T108
Test name
Test status
Simulation time	16228476 ps
CPU time	0.65 seconds
Started	Feb 04 12:45:06 PM PST 24
Finished	Feb 04 12:45:09 PM PST 24
Peak memory	202124 kb
Host	smart-8cb9fdc1-6008-40f7-98f4-0c2249370bea
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910017624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.3910017624
Directory	/workspace/23.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.i2c_intr_test.2628957596
Short name	T118
Test name
Test status
Simulation time	24631418 ps
CPU time	0.73 seconds
Started	Feb 04 12:44:50 PM PST 24
Finished	Feb 04 12:44:52 PM PST 24
Peak memory	202192 kb
Host	smart-2c720417-9e82-4525-abea-78ea61685d9a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628957596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.2628957596
Directory	/workspace/24.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.i2c_intr_test.1976048575
Short name	T121
Test name
Test status
Simulation time	17919305 ps
CPU time	0.63 seconds
Started	Feb 04 12:45:00 PM PST 24
Finished	Feb 04 12:45:07 PM PST 24
Peak memory	202184 kb
Host	smart-5bef2bda-17da-4b1d-b24b-03f85fdaf659
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976048575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.1976048575
Directory	/workspace/27.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.i2c_intr_test.3990491063
Short name	T92
Test name
Test status
Simulation time	21279740 ps
CPU time	0.7 seconds
Started	Feb 04 12:45:01 PM PST 24
Finished	Feb 04 12:45:08 PM PST 24
Peak memory	202160 kb
Host	smart-c4eb08d8-fa92-4379-b29a-13864c35cceb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990491063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.3990491063
Directory	/workspace/28.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.i2c_intr_test.1662155535
Short name	T142
Test name
Test status
Simulation time	43596066 ps
CPU time	0.66 seconds
Started	Feb 04 12:45:00 PM PST 24
Finished	Feb 04 12:45:07 PM PST 24
Peak memory	200208 kb
Host	smart-a6062dff-de40-46fa-86f7-26fbc3cc1884
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662155535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.1662155535
Directory	/workspace/29.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3742645155
Short name	T40
Test name
Test status
Simulation time	30166392 ps
CPU time	1.32 seconds
Started	Feb 04 12:44:34 PM PST 24
Finished	Feb 04 12:44:41 PM PST 24
Peak memory	202520 kb
Host	smart-5e2db5e0-e481-47e1-9f4b-78f21a5ee9a5
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742645155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3742645155
Directory	/workspace/3.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2389200491
Short name	T41
Test name
Test status
Simulation time	191112012 ps
CPU time	2.05 seconds
Started	Feb 04 12:44:37 PM PST 24
Finished	Feb 04 12:44:44 PM PST 24
Peak memory	202528 kb
Host	smart-8e46396c-2f21-4b2d-aa2a-df4a02d9c114
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389200491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.2389200491
Directory	/workspace/3.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.951107963
Short name	T33
Test name
Test status
Simulation time	111206370 ps
CPU time	0.65 seconds
Started	Feb 04 12:44:31 PM PST 24
Finished	Feb 04 12:44:33 PM PST 24
Peak memory	202188 kb
Host	smart-f1ffdb38-e19b-4bd9-8a92-22e4c2272874
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951107963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.951107963
Directory	/workspace/3.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_rw.2417212929
Short name	T43
Test name
Test status
Simulation time	23443089 ps
CPU time	0.73 seconds
Started	Feb 04 12:44:27 PM PST 24
Finished	Feb 04 12:44:29 PM PST 24
Peak memory	202384 kb
Host	smart-01f03436-94fa-4457-9647-c4c275f3fcbd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417212929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.2417212929
Directory	/workspace/3.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_intr_test.2117302785
Short name	T147
Test name
Test status
Simulation time	21572704 ps
CPU time	0.66 seconds
Started	Feb 04 12:44:33 PM PST 24
Finished	Feb 04 12:44:38 PM PST 24
Peak memory	202260 kb
Host	smart-8cfb9a0f-6908-4032-9430-7c3b58979f43
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117302785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.2117302785
Directory	/workspace/3.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2244627061
Short name	T31
Test name
Test status
Simulation time	23806199 ps
CPU time	1.06 seconds
Started	Feb 04 12:44:35 PM PST 24
Finished	Feb 04 12:44:41 PM PST 24
Peak memory	202512 kb
Host	smart-a3709b24-a32c-4533-999a-7e47c0ef2c51
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244627061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou tstanding.2244627061
Directory	/workspace/3.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_tl_errors.942321047
Short name	T119
Test name
Test status
Simulation time	60950413 ps
CPU time	1.16 seconds
Started	Feb 04 12:44:32 PM PST 24
Finished	Feb 04 12:44:35 PM PST 24
Peak memory	202488 kb
Host	smart-e7bdfe9a-c972-4fed-8564-719228ab1e95
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942321047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.942321047
Directory	/workspace/3.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1067060552
Short name	T97
Test name
Test status
Simulation time	279329478 ps
CPU time	1.76 seconds
Started	Feb 04 12:44:35 PM PST 24
Finished	Feb 04 12:44:42 PM PST 24
Peak memory	202180 kb
Host	smart-8ac8935d-110c-442a-9a3b-e192130cc9a7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067060552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.1067060552
Directory	/workspace/3.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.i2c_intr_test.2429589081
Short name	T104
Test name
Test status
Simulation time	35668641 ps
CPU time	0.63 seconds
Started	Feb 04 12:45:00 PM PST 24
Finished	Feb 04 12:45:07 PM PST 24
Peak memory	202136 kb
Host	smart-71e00c0c-2799-4162-b4e4-e0d3d63e60ff
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429589081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2429589081
Directory	/workspace/30.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.i2c_intr_test.53470702
Short name	T127
Test name
Test status
Simulation time	25789952 ps
CPU time	0.7 seconds
Started	Feb 04 12:45:06 PM PST 24
Finished	Feb 04 12:45:09 PM PST 24
Peak memory	202168 kb
Host	smart-d3702999-c8bf-4735-a305-aeb4589dd7b2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53470702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.53470702
Directory	/workspace/31.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.i2c_intr_test.847995988
Short name	T72
Test name
Test status
Simulation time	43022975 ps
CPU time	0.67 seconds
Started	Feb 04 12:45:00 PM PST 24
Finished	Feb 04 12:45:07 PM PST 24
Peak memory	202156 kb
Host	smart-9fa52020-2aa5-44f4-932a-e0131d98a7b5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847995988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.847995988
Directory	/workspace/32.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.i2c_intr_test.3456613516
Short name	T163
Test name
Test status
Simulation time	16679322 ps
CPU time	0.66 seconds
Started	Feb 04 12:45:01 PM PST 24
Finished	Feb 04 12:45:08 PM PST 24
Peak memory	202056 kb
Host	smart-e39e3e80-ec69-4607-831c-19abf0f80698
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456613516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.3456613516
Directory	/workspace/33.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.i2c_intr_test.1948382074
Short name	T109
Test name
Test status
Simulation time	30115560 ps
CPU time	0.63 seconds
Started	Feb 04 12:44:59 PM PST 24
Finished	Feb 04 12:45:01 PM PST 24
Peak memory	202156 kb
Host	smart-82154fd9-f609-4d83-81a2-3d62f068e0bc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948382074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.1948382074
Directory	/workspace/34.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.i2c_intr_test.1267668118
Short name	T73
Test name
Test status
Simulation time	19613618 ps
CPU time	0.65 seconds
Started	Feb 04 12:45:02 PM PST 24
Finished	Feb 04 12:45:07 PM PST 24
Peak memory	202180 kb
Host	smart-ae4f7a55-2317-43c3-85ca-16438375f4de
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267668118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.1267668118
Directory	/workspace/35.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.i2c_intr_test.3830496648
Short name	T165
Test name
Test status
Simulation time	54370750 ps
CPU time	0.65 seconds
Started	Feb 04 12:44:53 PM PST 24
Finished	Feb 04 12:44:54 PM PST 24
Peak memory	202140 kb
Host	smart-10c70a2c-cb75-4d8e-bbb9-f130953874d3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830496648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.3830496648
Directory	/workspace/36.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.i2c_intr_test.3523672309
Short name	T120
Test name
Test status
Simulation time	23085772 ps
CPU time	0.67 seconds
Started	Feb 04 12:45:03 PM PST 24
Finished	Feb 04 12:45:08 PM PST 24
Peak memory	202412 kb
Host	smart-47d07549-6cbe-412a-a763-31c4f47d2365
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523672309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3523672309
Directory	/workspace/37.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.i2c_intr_test.4155909420
Short name	T158
Test name
Test status
Simulation time	57099992 ps
CPU time	0.64 seconds
Started	Feb 04 12:45:06 PM PST 24
Finished	Feb 04 12:45:08 PM PST 24
Peak memory	202416 kb
Host	smart-6e6b7fdb-268e-4876-b526-0eb9b3066722
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155909420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.4155909420
Directory	/workspace/38.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.i2c_intr_test.843583309
Short name	T136
Test name
Test status
Simulation time	21076293 ps
CPU time	0.67 seconds
Started	Feb 04 12:45:01 PM PST 24
Finished	Feb 04 12:45:08 PM PST 24
Peak memory	202156 kb
Host	smart-961432ad-61e7-4695-b9a3-eafc3c4d702e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843583309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.843583309
Directory	/workspace/39.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.984902669
Short name	T29
Test name
Test status
Simulation time	64135766 ps
CPU time	0.91 seconds
Started	Feb 04 12:44:39 PM PST 24
Finished	Feb 04 12:44:44 PM PST 24
Peak memory	202336 kb
Host	smart-ab6bc59b-da10-490d-ac4b-fd9267198413
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984902669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.984902669
Directory	/workspace/4.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.136435648
Short name	T39
Test name
Test status
Simulation time	189221354 ps
CPU time	2.42 seconds
Started	Feb 04 12:44:32 PM PST 24
Finished	Feb 04 12:44:38 PM PST 24
Peak memory	202456 kb
Host	smart-1e2ca859-ab07-4977-8c53-d7e4cea199df
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136435648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.136435648
Directory	/workspace/4.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1755610338
Short name	T34
Test name
Test status
Simulation time	24755980 ps
CPU time	0.74 seconds
Started	Feb 04 12:44:33 PM PST 24
Finished	Feb 04 12:44:37 PM PST 24
Peak memory	202368 kb
Host	smart-c57774e5-8c7e-4b42-a27c-6ff4fa069cff
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755610338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.1755610338
Directory	/workspace/4.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.737783806
Short name	T90
Test name
Test status
Simulation time	18904924 ps
CPU time	0.81 seconds
Started	Feb 04 12:44:39 PM PST 24
Finished	Feb 04 12:44:50 PM PST 24
Peak memory	202376 kb
Host	smart-a91613f6-f976-4872-a03c-df1ec2747570
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737783806 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.737783806
Directory	/workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_rw.1104017312
Short name	T5
Test name
Test status
Simulation time	43107615 ps
CPU time	0.72 seconds
Started	Feb 04 12:44:32 PM PST 24
Finished	Feb 04 12:44:33 PM PST 24
Peak memory	202288 kb
Host	smart-c26213cb-02a3-4fcf-8fd8-e5f87ee2d95a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104017312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1104017312
Directory	/workspace/4.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_intr_test.957263486
Short name	T96
Test name
Test status
Simulation time	18153136 ps
CPU time	0.76 seconds
Started	Feb 04 12:44:34 PM PST 24
Finished	Feb 04 12:44:40 PM PST 24
Peak memory	202220 kb
Host	smart-3c28646d-62ec-4936-84e4-eba3fa380dec
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957263486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.957263486
Directory	/workspace/4.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.997284398
Short name	T94
Test name
Test status
Simulation time	33853053 ps
CPU time	0.78 seconds
Started	Feb 04 12:44:39 PM PST 24
Finished	Feb 04 12:44:44 PM PST 24
Peak memory	202312 kb
Host	smart-9be172a8-14d5-4510-958f-76ec85e31501
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997284398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_out standing.997284398
Directory	/workspace/4.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_tl_errors.2429463824
Short name	T161
Test name
Test status
Simulation time	54085163 ps
CPU time	2.64 seconds
Started	Feb 04 12:44:31 PM PST 24
Finished	Feb 04 12:44:34 PM PST 24
Peak memory	202508 kb
Host	smart-0539eb0a-e5fa-4f60-85f6-05554685856f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429463824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2429463824
Directory	/workspace/4.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3515004789
Short name	T45
Test name
Test status
Simulation time	69785876 ps
CPU time	1.26 seconds
Started	Feb 04 12:44:37 PM PST 24
Finished	Feb 04 12:44:43 PM PST 24
Peak memory	202424 kb
Host	smart-56475fd8-2615-486f-8bac-9cd05e56bcfb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515004789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.3515004789
Directory	/workspace/4.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.i2c_intr_test.4041324828
Short name	T164
Test name
Test status
Simulation time	16785638 ps
CPU time	0.67 seconds
Started	Feb 04 12:45:04 PM PST 24
Finished	Feb 04 12:45:08 PM PST 24
Peak memory	202180 kb
Host	smart-9a49cf0e-5d27-4763-8b8e-5c29774bb4b1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041324828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.4041324828
Directory	/workspace/40.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.i2c_intr_test.1215171831
Short name	T112
Test name
Test status
Simulation time	42931663 ps
CPU time	0.64 seconds
Started	Feb 04 12:45:14 PM PST 24
Finished	Feb 04 12:45:17 PM PST 24
Peak memory	202160 kb
Host	smart-25a32ca5-3a3a-48d6-a751-c361204ecc83
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215171831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1215171831
Directory	/workspace/41.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.i2c_intr_test.2952972357
Short name	T71
Test name
Test status
Simulation time	41173845 ps
CPU time	0.61 seconds
Started	Feb 04 12:44:58 PM PST 24
Finished	Feb 04 12:45:00 PM PST 24
Peak memory	200204 kb
Host	smart-bc5b3ece-b764-4b92-b403-75092c7cf16e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952972357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2952972357
Directory	/workspace/42.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.i2c_intr_test.3180629324
Short name	T157
Test name
Test status
Simulation time	17408670 ps
CPU time	0.69 seconds
Started	Feb 04 12:44:57 PM PST 24
Finished	Feb 04 12:45:00 PM PST 24
Peak memory	202244 kb
Host	smart-1dbc55c0-b710-474e-9675-b3ea5258e61d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180629324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.3180629324
Directory	/workspace/43.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.i2c_intr_test.2318306603
Short name	T110
Test name
Test status
Simulation time	25760678 ps
CPU time	0.66 seconds
Started	Feb 04 12:44:46 PM PST 24
Finished	Feb 04 12:44:50 PM PST 24
Peak memory	202216 kb
Host	smart-b8c662bd-122a-42b6-9841-c64adb7fc0cb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318306603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.2318306603
Directory	/workspace/44.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.i2c_intr_test.2510335951
Short name	T117
Test name
Test status
Simulation time	201253163 ps
CPU time	0.71 seconds
Started	Feb 04 12:45:04 PM PST 24
Finished	Feb 04 12:45:08 PM PST 24
Peak memory	202192 kb
Host	smart-4927f0d2-ed37-41ed-a5e8-c7898005c8e4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510335951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2510335951
Directory	/workspace/45.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.i2c_intr_test.22000581
Short name	T78
Test name
Test status
Simulation time	40088356 ps
CPU time	0.65 seconds
Started	Feb 04 12:45:03 PM PST 24
Finished	Feb 04 12:45:08 PM PST 24
Peak memory	202172 kb
Host	smart-62aa0546-f504-46ad-9cee-92907a765215
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22000581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.22000581
Directory	/workspace/46.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.i2c_intr_test.3689144286
Short name	T128
Test name
Test status
Simulation time	42697370 ps
CPU time	0.67 seconds
Started	Feb 04 12:45:01 PM PST 24
Finished	Feb 04 12:45:08 PM PST 24
Peak memory	202148 kb
Host	smart-b7084d00-6508-431a-8c29-ed45bd6a0bac
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689144286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.3689144286
Directory	/workspace/47.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.i2c_intr_test.1468661300
Short name	T80
Test name
Test status
Simulation time	24681479 ps
CPU time	0.62 seconds
Started	Feb 04 12:44:49 PM PST 24
Finished	Feb 04 12:44:51 PM PST 24
Peak memory	202052 kb
Host	smart-43fd44a1-61ee-4107-a68a-1f5aa862db90
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468661300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.1468661300
Directory	/workspace/48.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.i2c_intr_test.1854062823
Short name	T76
Test name
Test status
Simulation time	21921281 ps
CPU time	0.64 seconds
Started	Feb 04 12:44:49 PM PST 24
Finished	Feb 04 12:44:51 PM PST 24
Peak memory	202172 kb
Host	smart-f2390ac8-2a93-4328-b378-ac79a21e98a2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854062823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.1854062823
Directory	/workspace/49.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1730920266
Short name	T111
Test name
Test status
Simulation time	47626461 ps
CPU time	0.7 seconds
Started	Feb 04 12:44:35 PM PST 24
Finished	Feb 04 12:44:41 PM PST 24
Peak memory	202380 kb
Host	smart-d3288f4d-878b-4c0e-a866-b404497921d4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730920266 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.1730920266
Directory	/workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_csr_rw.3312112922
Short name	T100
Test name
Test status
Simulation time	25577402 ps
CPU time	0.79 seconds
Started	Feb 04 12:44:33 PM PST 24
Finished	Feb 04 12:44:39 PM PST 24
Peak memory	202252 kb
Host	smart-86ec75f4-4598-4595-8b3e-fbb55841172b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312112922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3312112922
Directory	/workspace/5.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_intr_test.364034182
Short name	T162
Test name
Test status
Simulation time	26837775 ps
CPU time	0.65 seconds
Started	Feb 04 12:44:33 PM PST 24
Finished	Feb 04 12:44:38 PM PST 24
Peak memory	202224 kb
Host	smart-cdb7b18e-28b7-4a54-b3ab-512a9a2067f1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364034182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.364034182
Directory	/workspace/5.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_tl_errors.3830125489
Short name	T139
Test name
Test status
Simulation time	46151794 ps
CPU time	1.24 seconds
Started	Feb 04 12:44:32 PM PST 24
Finished	Feb 04 12:44:37 PM PST 24
Peak memory	202532 kb
Host	smart-cbad1df6-4479-44a2-85bf-73a158e596d7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830125489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3830125489
Directory	/workspace/5.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1351088036
Short name	T58
Test name
Test status
Simulation time	427562306 ps
CPU time	1.84 seconds
Started	Feb 04 12:44:37 PM PST 24
Finished	Feb 04 12:44:44 PM PST 24
Peak memory	202400 kb
Host	smart-a41ccd34-d0cf-4014-b4c1-f2a2db908c20
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351088036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.1351088036
Directory	/workspace/5.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3130289213
Short name	T99
Test name
Test status
Simulation time	55292085 ps
CPU time	0.93 seconds
Started	Feb 04 12:44:36 PM PST 24
Finished	Feb 04 12:44:42 PM PST 24
Peak memory	202104 kb
Host	smart-a9538f72-bdf6-4fbc-830d-64f15100c0e9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130289213 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3130289213
Directory	/workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_csr_rw.210763097
Short name	T35
Test name
Test status
Simulation time	24895704 ps
CPU time	0.68 seconds
Started	Feb 04 12:44:26 PM PST 24
Finished	Feb 04 12:44:28 PM PST 24
Peak memory	202248 kb
Host	smart-7194c405-6ec4-4e3b-aa0f-a05093e4b2bb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210763097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.210763097
Directory	/workspace/6.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2747782519
Short name	T150
Test name
Test status
Simulation time	43632810 ps
CPU time	0.76 seconds
Started	Feb 04 12:44:35 PM PST 24
Finished	Feb 04 12:44:41 PM PST 24
Peak memory	202288 kb
Host	smart-68371721-4b0a-46a1-a888-ddcaa72f060e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747782519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou tstanding.2747782519
Directory	/workspace/6.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_tl_errors.1483051809
Short name	T103
Test name
Test status
Simulation time	94439993 ps
CPU time	1.77 seconds
Started	Feb 04 12:44:37 PM PST 24
Finished	Feb 04 12:44:44 PM PST 24
Peak memory	201984 kb
Host	smart-2a9318a0-a0ea-4d10-8c5b-da76ca933a63
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483051809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.1483051809
Directory	/workspace/6.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3940368162
Short name	T153
Test name
Test status
Simulation time	278859486 ps
CPU time	1.7 seconds
Started	Feb 04 12:44:36 PM PST 24
Finished	Feb 04 12:44:43 PM PST 24
Peak memory	202468 kb
Host	smart-efb6dbd9-0def-488b-acd7-50e7e3af411d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940368162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.3940368162
Directory	/workspace/6.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3890592155
Short name	T160
Test name
Test status
Simulation time	24417365 ps
CPU time	1 seconds
Started	Feb 04 12:44:32 PM PST 24
Finished	Feb 04 12:44:35 PM PST 24
Peak memory	202372 kb
Host	smart-d45d69b0-fe12-41d8-ba51-3394c95c12e1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890592155 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.3890592155
Directory	/workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_csr_rw.3998101676
Short name	T140
Test name
Test status
Simulation time	72578531 ps
CPU time	0.69 seconds
Started	Feb 04 12:44:19 PM PST 24
Finished	Feb 04 12:44:21 PM PST 24
Peak memory	201968 kb
Host	smart-46bb4e5a-ba16-417e-98ef-46deece073fe
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998101676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.3998101676
Directory	/workspace/7.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_intr_test.1949152230
Short name	T12
Test name
Test status
Simulation time	22613975 ps
CPU time	0.7 seconds
Started	Feb 04 12:44:17 PM PST 24
Finished	Feb 04 12:44:19 PM PST 24
Peak memory	202248 kb
Host	smart-a250a445-ccf9-49de-8441-4d7ba76b55db
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949152230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.1949152230
Directory	/workspace/7.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.977707089
Short name	T102
Test name
Test status
Simulation time	83815883 ps
CPU time	0.91 seconds
Started	Feb 04 12:44:18 PM PST 24
Finished	Feb 04 12:44:20 PM PST 24
Peak memory	202428 kb
Host	smart-ed43b794-8361-4866-9e18-a6ec45edd2ef
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977707089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_out standing.977707089
Directory	/workspace/7.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_tl_errors.454701460
Short name	T151
Test name
Test status
Simulation time	176446197 ps
CPU time	2 seconds
Started	Feb 04 12:44:30 PM PST 24
Finished	Feb 04 12:44:33 PM PST 24
Peak memory	202484 kb
Host	smart-0f8ef9a0-acd1-4c8d-abbc-749bde10ba4e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454701460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.454701460
Directory	/workspace/7.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3643545193
Short name	T53
Test name
Test status
Simulation time	131301807 ps
CPU time	1.91 seconds
Started	Feb 04 12:44:31 PM PST 24
Finished	Feb 04 12:44:34 PM PST 24
Peak memory	202496 kb
Host	smart-ef25b0d7-19e1-47d3-987c-9468561bfcbf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643545193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.3643545193
Directory	/workspace/7.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.4085357586
Short name	T133
Test name
Test status
Simulation time	26597174 ps
CPU time	1.19 seconds
Started	Feb 04 12:44:25 PM PST 24
Finished	Feb 04 12:44:27 PM PST 24
Peak memory	202560 kb
Host	smart-d9f2c51a-4def-43ea-a8f7-5e244814a6b6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085357586 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.4085357586
Directory	/workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_csr_rw.1199284431
Short name	T123
Test name
Test status
Simulation time	19176280 ps
CPU time	0.67 seconds
Started	Feb 04 12:44:32 PM PST 24
Finished	Feb 04 12:44:37 PM PST 24
Peak memory	201608 kb
Host	smart-c7977518-503f-45bf-901b-d6b9c70bbc74
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199284431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1199284431
Directory	/workspace/8.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.201977954
Short name	T26
Test name
Test status
Simulation time	98438048 ps
CPU time	0.79 seconds
Started	Feb 04 12:44:30 PM PST 24
Finished	Feb 04 12:44:31 PM PST 24
Peak memory	202248 kb
Host	smart-9fbc77e2-a013-4c79-a755-ea0a7aea2dee
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201977954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_out standing.201977954
Directory	/workspace/8.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_tl_errors.2100005213
Short name	T16
Test name
Test status
Simulation time	49064817 ps
CPU time	1.16 seconds
Started	Feb 04 12:44:17 PM PST 24
Finished	Feb 04 12:44:19 PM PST 24
Peak memory	202384 kb
Host	smart-e56c283a-599f-44b0-af2e-3ab2e7da651c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100005213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.2100005213
Directory	/workspace/8.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2785572034
Short name	T54
Test name
Test status
Simulation time	121453515 ps
CPU time	1.95 seconds
Started	Feb 04 12:44:21 PM PST 24
Finished	Feb 04 12:44:24 PM PST 24
Peak memory	202460 kb
Host	smart-3e5c5254-2df5-4012-a5a3-0bab6daf6495
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785572034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.2785572034
Directory	/workspace/8.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2739724335
Short name	T59
Test name
Test status
Simulation time	30896073 ps
CPU time	0.86 seconds
Started	Feb 04 12:44:19 PM PST 24
Finished	Feb 04 12:44:21 PM PST 24
Peak memory	202372 kb
Host	smart-fa1eb45d-3a5b-4f87-bc21-bd74280abd55
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739724335 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2739724335
Directory	/workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_csr_rw.1295771708
Short name	T36
Test name
Test status
Simulation time	21284678 ps
CPU time	0.69 seconds
Started	Feb 04 12:44:36 PM PST 24
Finished	Feb 04 12:44:41 PM PST 24
Peak memory	201492 kb
Host	smart-a9dbeb76-4093-4e68-984f-fdcef4dc7351
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295771708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1295771708
Directory	/workspace/9.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_intr_test.2271267889
Short name	T113
Test name
Test status
Simulation time	21665293 ps
CPU time	0.63 seconds
Started	Feb 04 12:44:30 PM PST 24
Finished	Feb 04 12:44:32 PM PST 24
Peak memory	202240 kb
Host	smart-a186826f-3c00-4422-ba3f-2898d03bfa2a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271267889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2271267889
Directory	/workspace/9.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2385181386
Short name	T98
Test name
Test status
Simulation time	82044305 ps
CPU time	0.93 seconds
Started	Feb 04 12:44:35 PM PST 24
Finished	Feb 04 12:44:42 PM PST 24
Peak memory	202180 kb
Host	smart-6361282e-691f-44df-a760-e6c9b4f44650
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385181386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou tstanding.2385181386
Directory	/workspace/9.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3481156703
Short name	T143
Test name
Test status
Simulation time	37863650 ps
CPU time	1.84 seconds
Started	Feb 04 12:44:34 PM PST 24
Finished	Feb 04 12:44:41 PM PST 24
Peak memory	202560 kb
Host	smart-3bc50761-5d71-4f5e-b936-f5836d2d625c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481156703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.3481156703
Directory	/workspace/9.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3513700073
Short name	T3
Test name
Test status
Simulation time	238544827 ps
CPU time	1.77 seconds
Started	Feb 04 12:44:31 PM PST 24
Finished	Feb 04 12:44:34 PM PST 24
Peak memory	202500 kb
Host	smart-abe79d11-9571-4416-bce5-f97959db6973
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513700073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.3513700073
Directory	/workspace/9.i2c_tl_intg_err/latest