Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	321	1			T7	5		T8	8		T9	5
all_pins[1]	321	1			T7	5		T8	8		T9	5
all_pins[2]	321	1			T7	5		T8	8		T9	5
all_pins[3]	321	1			T7	5		T8	8		T9	5
all_pins[4]	321	1			T7	5		T8	8		T9	5
all_pins[5]	321	1			T7	5		T8	8		T9	5
all_pins[6]	321	1			T7	5		T8	8		T9	5
all_pins[7]	321	1			T7	5		T8	8		T9	5
all_pins[8]	321	1			T7	5		T8	8		T9	5
all_pins[9]	321	1			T7	5		T8	8		T9	5
all_pins[10]	321	1			T7	5		T8	8		T9	5
all_pins[11]	321	1			T7	5		T8	8		T9	5
all_pins[12]	321	1			T7	5		T8	8		T9	5
all_pins[13]	321	1			T7	5		T8	8		T9	5
all_pins[14]	321	1			T7	5		T8	8		T9	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	3961	1			T7	67		T8	93		T9	67
values[0x1]	854	1			T7	8		T8	27		T9	8
transitions[0x0=>0x1]	645	1			T7	6		T8	20		T9	8
transitions[0x1=>0x0]	656	1			T7	6		T8	20		T9	8

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	254	1			T7	4		T8	7		T9	5
all_pins[0]	values[0x1]	67	1			T7	1		T8	1		T10	2
all_pins[0]	transitions[0x0=>0x1]	57	1			T7	1		T8	1		T10	2
all_pins[0]	transitions[0x1=>0x0]	44	1			T7	1		T8	3		T9	1
all_pins[1]	values[0x0]	267	1			T7	4		T8	5		T9	4
all_pins[1]	values[0x1]	54	1			T7	1		T8	3		T9	1
all_pins[1]	transitions[0x0=>0x1]	39	1			T7	1		T8	1		T9	1
all_pins[1]	transitions[0x1=>0x0]	43	1			T8	1		T10	2		T11	2
all_pins[2]	values[0x0]	263	1			T7	5		T8	5		T9	5
all_pins[2]	values[0x1]	58	1			T8	3		T10	2		T11	2
all_pins[2]	transitions[0x0=>0x1]	38	1			T8	2		T11	2		T12	2
all_pins[2]	transitions[0x1=>0x0]	40	1			T8	1		T10	2		T12	1
all_pins[3]	values[0x0]	261	1			T7	5		T8	6		T9	5
all_pins[3]	values[0x1]	60	1			T8	2		T10	4		T12	1
all_pins[3]	transitions[0x0=>0x1]	50	1			T8	1		T10	4		T12	1
all_pins[3]	transitions[0x1=>0x0]	47	1			T7	1		T11	1		T12	2
all_pins[4]	values[0x0]	264	1			T7	4		T8	7		T9	5
all_pins[4]	values[0x1]	57	1			T7	1		T8	1		T11	1
all_pins[4]	transitions[0x0=>0x1]	44	1			T7	1		T8	1		T11	1
all_pins[4]	transitions[0x1=>0x0]	45	1			T8	2		T9	2		T10	3
all_pins[5]	values[0x0]	263	1			T7	5		T8	6		T9	3
all_pins[5]	values[0x1]	58	1			T8	2		T9	2		T10	3
all_pins[5]	transitions[0x0=>0x1]	43	1			T8	2		T9	2		T10	2
all_pins[5]	transitions[0x1=>0x0]	38	1			T8	2		T9	1		T11	1
all_pins[6]	values[0x0]	268	1			T7	5		T8	6		T9	4
all_pins[6]	values[0x1]	53	1			T8	2		T9	1		T10	1
all_pins[6]	transitions[0x0=>0x1]	47	1			T8	1		T9	1		T11	1
all_pins[6]	transitions[0x1=>0x0]	44	1			T7	1		T8	2		T9	2
all_pins[7]	values[0x0]	271	1			T7	4		T8	5		T9	3
all_pins[7]	values[0x1]	50	1			T7	1		T8	3		T9	2
all_pins[7]	transitions[0x0=>0x1]	36	1			T7	1		T8	1		T9	2
all_pins[7]	transitions[0x1=>0x0]	41	1			T8	1		T12	2		T69	1
all_pins[8]	values[0x0]	266	1			T7	5		T8	5		T9	5
all_pins[8]	values[0x1]	55	1			T8	3		T10	1		T12	2
all_pins[8]	transitions[0x0=>0x1]	47	1			T8	3		T10	1		T12	2
all_pins[8]	transitions[0x1=>0x0]	39	1			T12	1		T70	2		T69	1
all_pins[9]	values[0x0]	274	1			T7	5		T8	8		T9	5
all_pins[9]	values[0x1]	47	1			T12	1		T70	2		T69	1
all_pins[9]	transitions[0x0=>0x1]	35	1			T12	1		T70	1		T69	1
all_pins[9]	transitions[0x1=>0x0]	47	1			T7	2		T8	3		T9	1
all_pins[10]	values[0x0]	262	1			T7	3		T8	5		T9	4
all_pins[10]	values[0x1]	59	1			T7	2		T8	3		T9	1
all_pins[10]	transitions[0x0=>0x1]	50	1			T8	3		T9	1		T12	1
all_pins[10]	transitions[0x1=>0x0]	46	1			T10	1		T12	4		T70	1
all_pins[11]	values[0x0]	266	1			T7	3		T8	8		T9	5
all_pins[11]	values[0x1]	55	1			T7	2		T10	1		T12	4
all_pins[11]	transitions[0x0=>0x1]	40	1			T7	2		T10	1		T12	2
all_pins[11]	transitions[0x1=>0x0]	36	1			T8	2		T9	1		T11	1
all_pins[12]	values[0x0]	270	1			T7	5		T8	6		T9	4
all_pins[12]	values[0x1]	51	1			T8	2		T9	1		T11	1
all_pins[12]	transitions[0x0=>0x1]	39	1			T8	2		T9	1		T11	1
all_pins[12]	transitions[0x1=>0x0]	56	1			T8	2		T10	1		T12	3
all_pins[13]	values[0x0]	253	1			T7	5		T8	6		T9	5
all_pins[13]	values[0x1]	68	1			T8	2		T10	1		T12	3
all_pins[13]	transitions[0x0=>0x1]	45	1			T8	2		T12	3		T71	2
all_pins[13]	transitions[0x1=>0x0]	39	1			T10	1		T11	2		T12	1
all_pins[14]	values[0x0]	259	1			T7	5		T8	8		T9	5
all_pins[14]	values[0x1]	62	1			T10	2		T11	2		T12	1
all_pins[14]	transitions[0x0=>0x1]	35	1			T10	1		T11	1		T69	2
all_pins[14]	transitions[0x1=>0x0]	51	1			T7	1		T8	1		T10	2