Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	251	1			T7	4		T8	7		T9	4
all_values[1]	251	1			T7	4		T8	7		T9	4
all_values[2]	251	1			T7	4		T8	7		T9	4
all_values[3]	251	1			T7	4		T8	7		T9	4
all_values[4]	251	1			T7	4		T8	7		T9	4
all_values[5]	251	1			T7	4		T8	7		T9	4
all_values[6]	251	1			T7	4		T8	7		T9	4
all_values[7]	251	1			T7	4		T8	7		T9	4
all_values[8]	251	1			T7	4		T8	7		T9	4
all_values[9]	251	1			T7	4		T8	7		T9	4
all_values[10]	251	1			T7	4		T8	7		T9	4
all_values[11]	251	1			T7	4		T8	7		T9	4
all_values[12]	251	1			T7	4		T8	7		T9	4
all_values[13]	251	1			T7	4		T8	7		T9	4
all_values[14]	251	1			T7	4		T8	7		T9	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2081

1

T7

29

T8

69

T9

20

auto[1]

1684

1

T7

31

T8

36

T9

40

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

744

1

T7

19

T8

14

T9

17

auto[1]

3021

1

T7

41

T8

91

T9

43

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2271

1

T7

39

T8

58

T9

35

auto[1]

1494

1

T7

21

T8

47

T9

25

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	39	1			T7	1		T10	1		T11	3
all_values[0]	auto[0]	auto[0]	auto[1]	57	1			T8	5		T9	2		T12	2
all_values[0]	auto[0]	auto[1]	auto[0]	11	1			T11	1		T69	1		T72	1
all_values[0]	auto[0]	auto[1]	auto[1]	40	1			T7	1		T10	1		T70	2
all_values[0]	auto[1]	auto[0]	auto[1]	56	1			T8	2		T10	1		T12	3
all_values[0]	auto[1]	auto[1]	auto[1]	48	1			T7	2		T9	2		T10	1
all_values[1]	auto[0]	auto[0]	auto[0]	43	1			T8	2		T10	1		T69	1
all_values[1]	auto[0]	auto[0]	auto[1]	46	1			T10	2		T11	1		T70	1
all_values[1]	auto[0]	auto[1]	auto[0]	19	1			T70	1		T71	1		T73	1
all_values[1]	auto[0]	auto[1]	auto[1]	55	1			T7	3		T8	2		T9	1
all_values[1]	auto[1]	auto[0]	auto[1]	46	1			T8	2		T9	1		T10	1
all_values[1]	auto[1]	auto[1]	auto[1]	42	1			T7	1		T8	1		T9	2
all_values[2]	auto[0]	auto[0]	auto[0]	36	1			T7	2		T8	2		T10	1
all_values[2]	auto[0]	auto[0]	auto[1]	39	1			T9	1		T10	1		T12	1
all_values[2]	auto[0]	auto[1]	auto[0]	18	1			T7	2		T9	1		T70	1
all_values[2]	auto[0]	auto[1]	auto[1]	52	1			T8	1		T10	1		T11	1
all_values[2]	auto[1]	auto[0]	auto[1]	58	1			T8	2		T9	1		T11	3
all_values[2]	auto[1]	auto[1]	auto[1]	48	1			T8	2		T9	1		T10	1
all_values[3]	auto[0]	auto[0]	auto[0]	24	1			T7	4		T11	2		T69	1
all_values[3]	auto[0]	auto[0]	auto[1]	57	1			T8	3		T9	2		T11	1
all_values[3]	auto[0]	auto[1]	auto[0]	10	1			T9	1		T74	1		T75	1
all_values[3]	auto[0]	auto[1]	auto[1]	64	1			T8	1		T10	1		T12	1
all_values[3]	auto[1]	auto[0]	auto[1]	63	1			T8	3		T10	1		T11	1
all_values[3]	auto[1]	auto[1]	auto[1]	33	1			T9	1		T10	2		T12	2
all_values[4]	auto[0]	auto[0]	auto[0]	38	1			T10	4		T70	2		T73	1
all_values[4]	auto[0]	auto[0]	auto[1]	51	1			T7	2		T8	2		T9	1
all_values[4]	auto[0]	auto[1]	auto[0]	16	1			T9	1		T11	1		T12	1
all_values[4]	auto[0]	auto[1]	auto[1]	43	1			T9	1		T11	1		T12	4
all_values[4]	auto[1]	auto[0]	auto[1]	59	1			T7	1		T8	3		T69	2
all_values[4]	auto[1]	auto[1]	auto[1]	44	1			T7	1		T8	2		T9	1
all_values[5]	auto[0]	auto[0]	auto[0]	31	1			T8	2		T9	1		T76	3
all_values[5]	auto[0]	auto[0]	auto[1]	48	1			T7	2		T8	1		T12	1
all_values[5]	auto[0]	auto[1]	auto[0]	20	1			T7	1		T70	1		T77	1
all_values[5]	auto[0]	auto[1]	auto[1]	62	1			T8	3		T9	1		T10	1
all_values[5]	auto[1]	auto[0]	auto[1]	50	1			T7	1		T8	1		T9	1
all_values[5]	auto[1]	auto[1]	auto[1]	40	1			T9	1		T10	1		T11	2
all_values[6]	auto[0]	auto[0]	auto[0]	25	1			T7	1		T10	1		T12	1
all_values[6]	auto[0]	auto[0]	auto[1]	64	1			T8	1		T9	1		T10	1
all_values[6]	auto[0]	auto[1]	auto[0]	17	1			T7	1		T9	1		T78	1
all_values[6]	auto[0]	auto[1]	auto[1]	46	1			T7	1		T8	2		T10	1
all_values[6]	auto[1]	auto[0]	auto[1]	60	1			T8	3		T11	1		T12	2
all_values[6]	auto[1]	auto[1]	auto[1]	39	1			T7	1		T8	1		T9	2
all_values[7]	auto[0]	auto[0]	auto[0]	41	1			T7	1		T77	2		T79	1
all_values[7]	auto[0]	auto[0]	auto[1]	51	1			T7	1		T8	1		T12	3
all_values[7]	auto[0]	auto[1]	auto[0]	18	1			T9	1		T11	4		T12	1
all_values[7]	auto[0]	auto[1]	auto[1]	42	1			T7	1		T8	1		T9	1
all_values[7]	auto[1]	auto[0]	auto[1]	59	1			T8	4		T10	1		T12	2
all_values[7]	auto[1]	auto[1]	auto[1]	40	1			T7	1		T8	1		T9	2
all_values[8]	auto[0]	auto[0]	auto[0]	33	1			T11	2		T70	1		T71	1
all_values[8]	auto[0]	auto[0]	auto[1]	51	1			T8	1		T10	2		T11	1
all_values[8]	auto[0]	auto[1]	auto[0]	17	1			T9	1		T77	1		T76	1
all_values[8]	auto[0]	auto[1]	auto[1]	45	1			T7	1		T8	3		T9	1
all_values[8]	auto[1]	auto[0]	auto[1]	54	1			T7	3		T8	1		T9	1
all_values[8]	auto[1]	auto[1]	auto[1]	51	1			T8	2		T9	1		T12	2
all_values[9]	auto[0]	auto[0]	auto[0]	23	1			T8	1		T12	1		T71	1
all_values[9]	auto[0]	auto[0]	auto[1]	65	1			T7	2		T8	3		T10	1
all_values[9]	auto[0]	auto[1]	auto[0]	17	1			T7	1		T12	2		T76	2
all_values[9]	auto[0]	auto[1]	auto[1]	40	1			T9	1		T10	2		T11	1
all_values[9]	auto[1]	auto[0]	auto[1]	71	1			T7	1		T8	3		T9	2
all_values[9]	auto[1]	auto[1]	auto[1]	35	1			T9	1		T11	1		T12	1
all_values[10]	auto[0]	auto[0]	auto[0]	27	1			T10	3		T70	2		T80	2
all_values[10]	auto[0]	auto[0]	auto[1]	43	1			T7	1		T8	1		T11	2
all_values[10]	auto[0]	auto[1]	auto[0]	18	1			T9	2		T10	1		T12	1
all_values[10]	auto[0]	auto[1]	auto[1]	61	1			T8	1		T9	1		T11	1
all_values[10]	auto[1]	auto[0]	auto[1]	47	1			T8	3		T9	1		T11	1
all_values[10]	auto[1]	auto[1]	auto[1]	55	1			T7	3		T8	2		T12	2
all_values[11]	auto[0]	auto[0]	auto[0]	34	1			T8	2		T9	2		T73	1
all_values[11]	auto[0]	auto[0]	auto[1]	59	1			T7	1		T8	2		T10	2
all_values[11]	auto[0]	auto[1]	auto[0]	24	1			T8	2		T9	2		T11	1
all_values[11]	auto[0]	auto[1]	auto[1]	43	1			T7	1		T12	3		T70	1
all_values[11]	auto[1]	auto[0]	auto[1]	41	1			T10	1		T70	1		T69	2
all_values[11]	auto[1]	auto[1]	auto[1]	50	1			T7	2		T8	1		T10	1
all_values[12]	auto[0]	auto[0]	auto[0]	29	1			T7	1		T8	1		T10	3
all_values[12]	auto[0]	auto[0]	auto[1]	48	1			T7	1		T11	1		T12	2
all_values[12]	auto[0]	auto[1]	auto[0]	25	1			T8	2		T9	2		T10	1
all_values[12]	auto[0]	auto[1]	auto[1]	54	1			T8	1		T9	1		T11	1
all_values[12]	auto[1]	auto[0]	auto[1]	54	1			T7	2		T8	2		T11	2
all_values[12]	auto[1]	auto[1]	auto[1]	41	1			T8	1		T9	1		T12	4
all_values[13]	auto[0]	auto[0]	auto[0]	27	1			T69	1		T77	2		T81	3
all_values[13]	auto[0]	auto[0]	auto[1]	49	1			T7	1		T8	2		T9	1
all_values[13]	auto[0]	auto[1]	auto[0]	19	1			T7	2		T11	2		T70	1
all_values[13]	auto[0]	auto[1]	auto[1]	49	1			T8	2		T9	1		T11	1
all_values[13]	auto[1]	auto[0]	auto[1]	54	1			T8	3		T10	2		T12	2
all_values[13]	auto[1]	auto[1]	auto[1]	53	1			T7	1		T9	2		T10	1
all_values[14]	auto[0]	auto[0]	auto[0]	30	1			T9	2		T69	1		T71	1
all_values[14]	auto[0]	auto[0]	auto[1]	46	1			T8	3		T10	1		T11	1
all_values[14]	auto[0]	auto[1]	auto[0]	15	1			T7	2		T70	2		T71	1
all_values[14]	auto[0]	auto[1]	auto[1]	57	1			T7	1		T8	2		T9	1
all_values[14]	auto[1]	auto[0]	auto[1]	55	1			T8	2		T10	1		T12	2
all_values[14]	auto[1]	auto[1]	auto[1]	48	1			T7	1		T9	1		T10	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal