Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.67	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	5	55	91.67

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	5	55	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6901751	1			T1	3		T2	3		T3	3
all_values[1]	6901751	1			T1	3		T2	3		T3	3
all_values[2]	6901751	1			T1	3		T2	3		T3	3
all_values[3]	6901751	1			T1	3		T2	3		T3	3
all_values[4]	6901751	1			T1	3		T2	3		T3	3
all_values[5]	6901751	1			T1	3		T2	3		T3	3
all_values[6]	6901751	1			T1	3		T2	3		T3	3
all_values[7]	6901751	1			T1	3		T2	3		T3	3
all_values[8]	6901751	1			T1	3		T2	3		T3	3
all_values[9]	6901751	1			T1	3		T2	3		T3	3
all_values[10]	6901751	1			T1	3		T2	3		T3	3
all_values[11]	6901751	1			T1	3		T2	3		T3	3
all_values[12]	6901751	1			T1	3		T2	3		T3	3
all_values[13]	6901751	1			T1	3		T2	3		T3	3
all_values[14]	6901751	1			T1	3		T2	3		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97423817

1

T1

44

T2

41

T3

44

auto[1]

6102448

1

T1

1

T2

4

T3

1

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

90659273

1

T1

45

T2

45

T3

45

auto[1]

12866992

1

T11

122443

T12

581298

T64

318690

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	5	55	91.67	5

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	5310801	1			T1	3		T2	3		T3	3
all_values[0]	auto[0]	auto[1]	622892	1			T11	102033		T12	42698		T64	100951
all_values[0]	auto[1]	auto[0]	774731	1			T8	1		T9	13		T31	1
all_values[0]	auto[1]	auto[1]	193327	1			T11	4		T12	5744		T64	26902
all_values[1]	auto[0]	auto[0]	5499112	1			T1	3		T2	3		T3	3
all_values[1]	auto[0]	auto[1]	697009	1			T12	43978		T64	186246		T13	16
all_values[1]	auto[1]	auto[0]	565184	1			T9	70		T14	210		T11	49
all_values[1]	auto[1]	auto[1]	140446	1			T12	4464		T64	32258		T13	4
all_values[2]	auto[0]	auto[0]	6010722	1			T1	3		T2	3		T3	3
all_values[2]	auto[0]	auto[1]	890834	1			T11	102033		T64	218503		T13	18
all_values[2]	auto[1]	auto[1]	195	1			T11	2		T13	4		T95	3
all_values[3]	auto[0]	auto[0]	5962250	1			T1	3		T2	3		T3	3
all_values[3]	auto[0]	auto[1]	939290	1			T11	102035		T12	48440		T64	218500
all_values[3]	auto[1]	auto[1]	211	1			T11	2		T12	2		T64	4
all_values[4]	auto[0]	auto[0]	6064256	1			T1	3		T2	3		T3	3
all_values[4]	auto[0]	auto[1]	837233	1			T12	48438		T64	218503		T13	11
all_values[4]	auto[1]	auto[0]	44	1			T41	23		T43	21		-	-
all_values[4]	auto[1]	auto[1]	218	1			T12	2		T13	6		T95	3
all_values[5]	auto[0]	auto[0]	6080034	1			T1	3		T2	3		T3	3
all_values[5]	auto[0]	auto[1]	821499	1			T12	48442		T64	218500		T13	14
all_values[5]	auto[1]	auto[1]	218	1			T64	4		T13	8		T95	1
all_values[6]	auto[0]	auto[0]	5307318	1			T1	3		T2	2		T3	3
all_values[6]	auto[0]	auto[1]	573207	1			T11	102034		T64	174341		T13	15
all_values[6]	auto[1]	auto[0]	861212	1			T2	1		T8	1		T9	32
all_values[6]	auto[1]	auto[1]	160014	1			T11	3		T64	44161		T13	7
all_values[7]	auto[0]	auto[0]	5673342	1			T1	3		T2	2		T3	3
all_values[7]	auto[0]	auto[1]	877421	1			T11	101603		T12	48375		T64	213391
all_values[7]	auto[1]	auto[0]	320577	1			T2	1		T9	1020		T10	1
all_values[7]	auto[1]	auto[1]	30411	1			T11	433		T12	67		T64	5113
all_values[8]	auto[0]	auto[0]	4997187	1			T1	3		T2	2		T3	3
all_values[8]	auto[0]	auto[1]	698538	1			T11	102022		T12	42448		T64	173583
all_values[8]	auto[1]	auto[0]	1039909	1			T2	1		T9	408		T10	1
all_values[8]	auto[1]	auto[1]	166117	1			T11	14		T12	5993		T64	44921
all_values[9]	auto[0]	auto[0]	5015114	1			T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	720329	1			T11	102033		T12	43171		T64	174682
all_values[9]	auto[1]	auto[0]	947162	1			T1	1		T2	1		T3	1
all_values[9]	auto[1]	auto[1]	219146	1			T11	4		T12	5271		T64	43822
all_values[10]	auto[0]	auto[0]	5882834	1			T1	3		T2	3		T3	3
all_values[10]	auto[0]	auto[1]	869278	1			T11	102034		T12	48440		T64	218501
all_values[10]	auto[1]	auto[0]	149454	1			T17	2489		T18	2047		T172	2628
all_values[10]	auto[1]	auto[1]	185	1			T11	2		T12	2		T64	3
all_values[11]	auto[0]	auto[0]	5429333	1			T1	3		T2	3		T3	3
all_values[11]	auto[0]	auto[1]	939284	1			T11	102035		T12	48438		T64	218501
all_values[11]	auto[1]	auto[0]	532908	1			T17	5943		T18	6204		T19	5897
all_values[11]	auto[1]	auto[1]	226	1			T11	2		T12	2		T64	3
all_values[12]	auto[0]	auto[0]	6086127	1			T1	3		T2	3		T3	3
all_values[12]	auto[0]	auto[1]	815455	1			T11	102036		T12	48441		T64	218499
all_values[12]	auto[1]	auto[1]	169	1			T11	1		T12	1		T64	5
all_values[13]	auto[0]	auto[0]	6181450	1			T1	3		T2	3		T3	3
all_values[13]	auto[0]	auto[1]	720095	1			T11	102036		T64	218500		T13	12
all_values[13]	auto[1]	auto[0]	10	1			T37	1		T54	1		T184	1
all_values[13]	auto[1]	auto[1]	196	1			T11	1		T64	4		T13	8
all_values[14]	auto[0]	auto[0]	5968202	1			T1	3		T2	3		T3	3
all_values[14]	auto[0]	auto[1]	933371	1			T11	102035		T12	48438		T64	218500
all_values[14]	auto[1]	auto[1]	178	1			T11	2		T12	3		T64	4