Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6901751	1			T1	3		T2	3		T3	3
all_pins[1]	6901751	1			T1	3		T2	3		T3	3
all_pins[2]	6901751	1			T1	3		T2	3		T3	3
all_pins[3]	6901751	1			T1	3		T2	3		T3	3
all_pins[4]	6901751	1			T1	3		T2	3		T3	3
all_pins[5]	6901751	1			T1	3		T2	3		T3	3
all_pins[6]	6901751	1			T1	3		T2	3		T3	3
all_pins[7]	6901751	1			T1	3		T2	3		T3	3
all_pins[8]	6901751	1			T1	3		T2	3		T3	3
all_pins[9]	6901751	1			T1	3		T2	3		T3	3
all_pins[10]	6901751	1			T1	3		T2	3		T3	3
all_pins[11]	6901751	1			T1	3		T2	3		T3	3
all_pins[12]	6901751	1			T1	3		T2	3		T3	3
all_pins[13]	6901751	1			T1	3		T2	3		T3	3
all_pins[14]	6901751	1			T1	3		T2	3		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	97349544	1			T1	44		T2	41		T3	44
values[0x1]	6176721	1			T1	1		T2	4		T3	1
transitions[0x0=>0x1]	4195988	1			T1	1		T2	1		T3	1
transitions[0x1=>0x0]	4195998	1			T1	1		T2	1		T3	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	5933483	1			T1	3		T2	3		T3	3
all_pins[0]	values[0x1]	968268	1			T8	1		T9	16		T31	2
all_pins[0]	transitions[0x0=>0x1]	284860	1			T8	1		T9	16		T31	2
all_pins[0]	transitions[0x1=>0x0]	24829	1			T9	85		T14	249		T11	52
all_pins[1]	values[0x0]	6193514	1			T1	3		T2	3		T3	3
all_pins[1]	values[0x1]	708237	1			T9	85		T14	249		T11	53
all_pins[1]	transitions[0x0=>0x1]	708223	1			T9	85		T14	249		T11	53
all_pins[1]	transitions[0x1=>0x0]	82	1			T95	1		T96	2		T44	4
all_pins[2]	values[0x0]	6901655	1			T1	3		T2	3		T3	3
all_pins[2]	values[0x1]	96	1			T95	1		T96	2		T44	4
all_pins[2]	transitions[0x0=>0x1]	79	1			T95	1		T96	2		T44	4
all_pins[2]	transitions[0x1=>0x0]	92	1			T11	1		T64	2		T13	3
all_pins[3]	values[0x0]	6901642	1			T1	3		T2	3		T3	3
all_pins[3]	values[0x1]	109	1			T11	1		T64	2		T13	3
all_pins[3]	transitions[0x0=>0x1]	81	1			T11	1		T64	2		T13	3
all_pins[3]	transitions[0x1=>0x0]	124	1			T13	2		T95	1		T96	3
all_pins[4]	values[0x0]	6901599	1			T1	3		T2	3		T3	3
all_pins[4]	values[0x1]	152	1			T13	2		T95	3		T96	3
all_pins[4]	transitions[0x0=>0x1]	126	1			T13	1		T95	3		T96	3
all_pins[4]	transitions[0x1=>0x0]	86	1			T64	3		T13	3		T96	1
all_pins[5]	values[0x0]	6901639	1			T1	3		T2	3		T3	3
all_pins[5]	values[0x1]	112	1			T64	3		T13	4		T96	1
all_pins[5]	transitions[0x0=>0x1]	94	1			T64	3		T13	3		T96	1
all_pins[5]	transitions[0x1=>0x0]	1024755	1			T2	1		T8	1		T9	38
all_pins[6]	values[0x0]	5876978	1			T1	3		T2	2		T3	3
all_pins[6]	values[0x1]	1024773	1			T2	1		T8	1		T9	38
all_pins[6]	transitions[0x0=>0x1]	1002959	1			T8	1		T9	36		T31	1
all_pins[6]	transitions[0x1=>0x0]	371480	1			T9	1163		T14	2269		T11	1695
all_pins[7]	values[0x0]	6508457	1			T1	3		T2	2		T3	3
all_pins[7]	values[0x1]	393294	1			T2	1		T9	1165		T10	1
all_pins[7]	transitions[0x0=>0x1]	323408	1			T9	1109		T14	2053		T11	1629
all_pins[7]	transitions[0x1=>0x0]	1161252	1			T9	408		T31	12		T14	446
all_pins[8]	values[0x0]	5670613	1			T1	3		T2	2		T3	3
all_pins[8]	values[0x1]	1231138	1			T2	1		T9	464		T10	1
all_pins[8]	transitions[0x0=>0x1]	248247	1			T9	464		T31	12		T14	673
all_pins[8]	transitions[0x1=>0x0]	184498	1			T1	1		T3	1		T15	1
all_pins[9]	values[0x0]	5734362	1			T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	1167389	1			T1	1		T2	1		T3	1
all_pins[9]	transitions[0x0=>0x1]	1091519	1			T1	1		T2	1		T3	1
all_pins[9]	transitions[0x1=>0x0]	73987	1			T17	1692		T11	1		T18	1598
all_pins[10]	values[0x0]	6751894	1			T1	3		T2	3		T3	3
all_pins[10]	values[0x1]	149857	1			T17	2491		T11	2		T12	1
all_pins[10]	transitions[0x0=>0x1]	3177	1			T17	84		T11	2		T12	1
all_pins[10]	transitions[0x1=>0x0]	386333	1			T17	3536		T18	4157		T19	5897
all_pins[11]	values[0x0]	6368738	1			T1	3		T2	3		T3	3
all_pins[11]	values[0x1]	533013	1			T17	5943		T18	6204		T19	5897
all_pins[11]	transitions[0x0=>0x1]	532990	1			T17	5943		T18	6204		T19	5897
all_pins[11]	transitions[0x1=>0x0]	67	1			T12	1		T64	4		T13	1
all_pins[12]	values[0x0]	6901661	1			T1	3		T2	3		T3	3
all_pins[12]	values[0x1]	90	1			T12	1		T64	4		T13	2
all_pins[12]	transitions[0x0=>0x1]	72	1			T12	1		T64	4		T13	1
all_pins[12]	transitions[0x1=>0x0]	88	1			T37	1		T11	1		T13	5
all_pins[13]	values[0x0]	6901645	1			T1	3		T2	3		T3	3
all_pins[13]	values[0x1]	106	1			T37	1		T11	1		T13	6
all_pins[13]	transitions[0x0=>0x1]	90	1			T37	1		T11	1		T13	6
all_pins[13]	transitions[0x1=>0x0]	71	1			T12	3		T64	3		T13	4
all_pins[14]	values[0x0]	6901664	1			T1	3		T2	3		T3	3
all_pins[14]	values[0x1]	87	1			T12	3		T64	3		T13	4
all_pins[14]	transitions[0x0=>0x1]	63	1			T12	2		T64	3		T13	3
all_pins[14]	transitions[0x1=>0x0]	968254	1			T8	1		T9	16		T31	2