Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	442	1			T11	4		T12	4		T64	8
all_values[1]	442	1			T11	4		T12	4		T64	8
all_values[2]	442	1			T11	4		T12	4		T64	8
all_values[3]	442	1			T11	4		T12	4		T64	8
all_values[4]	442	1			T11	4		T12	4		T64	8
all_values[5]	442	1			T11	4		T12	4		T64	8
all_values[6]	442	1			T11	4		T12	4		T64	8
all_values[7]	442	1			T11	4		T12	4		T64	8
all_values[8]	442	1			T11	4		T12	4		T64	8
all_values[9]	442	1			T11	4		T12	4		T64	8
all_values[10]	442	1			T11	4		T12	4		T64	8
all_values[11]	442	1			T11	4		T12	4		T64	8
all_values[12]	442	1			T11	4		T12	4		T64	8
all_values[13]	442	1			T11	4		T12	4		T64	8
all_values[14]	442	1			T11	4		T12	4		T64	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3422

1

T11

20

T12

26

T64

45

auto[1]

3208

1

T11

40

T12

34

T64

75

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1069

1

T11

17

T12

18

T64

8

auto[1]

5561

1

T11

43

T12

42

T64

112

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3947

1

T11

40

T12

39

T64

75

auto[1]

2683

1

T11

20

T12

21

T64

45

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	44	1			T64	2		T95	1		T199	1
all_values[0]	auto[0]	auto[0]	auto[1]	87	1			T13	3		T95	1		T96	1
all_values[0]	auto[0]	auto[1]	auto[0]	31	1			T64	2		T13	1		T199	1
all_values[0]	auto[0]	auto[1]	auto[1]	98	1			T11	3		T12	2		T64	2
all_values[0]	auto[1]	auto[0]	auto[1]	94	1			T64	1		T13	1		T95	1
all_values[0]	auto[1]	auto[1]	auto[1]	88	1			T11	1		T12	2		T64	1
all_values[1]	auto[0]	auto[0]	auto[0]	40	1			T11	2		T13	2		T44	2
all_values[1]	auto[0]	auto[0]	auto[1]	95	1			T12	1		T64	3		T13	3
all_values[1]	auto[0]	auto[1]	auto[0]	24	1			T11	2		T200	1		T201	1
all_values[1]	auto[0]	auto[1]	auto[1]	99	1			T12	1		T64	2		T13	3
all_values[1]	auto[1]	auto[0]	auto[1]	113	1			T12	1		T64	1		T13	4
all_values[1]	auto[1]	auto[1]	auto[1]	71	1			T12	1		T64	2		T95	2
all_values[2]	auto[0]	auto[0]	auto[0]	51	1			T12	2		T64	1		T96	2
all_values[2]	auto[0]	auto[0]	auto[1]	98	1			T11	1		T64	1		T13	3
all_values[2]	auto[0]	auto[1]	auto[0]	32	1			T11	2		T12	2		T95	1
all_values[2]	auto[0]	auto[1]	auto[1]	99	1			T64	4		T13	5		T96	1
all_values[2]	auto[1]	auto[0]	auto[1]	83	1			T64	2		T13	3		T95	1
all_values[2]	auto[1]	auto[1]	auto[1]	79	1			T11	1		T13	1		T95	1
all_values[3]	auto[0]	auto[0]	auto[0]	32	1			T13	1		T96	1		T202	1
all_values[3]	auto[0]	auto[0]	auto[1]	90	1			T11	1		T12	1		T64	1
all_values[3]	auto[0]	auto[1]	auto[0]	22	1			T95	2		T39	3		T203	1
all_values[3]	auto[0]	auto[1]	auto[1]	100	1			T11	1		T64	4		T13	4
all_values[3]	auto[1]	auto[0]	auto[1]	115	1			T12	1		T64	1		T13	2
all_values[3]	auto[1]	auto[1]	auto[1]	83	1			T11	2		T12	2		T64	2
all_values[4]	auto[0]	auto[0]	auto[0]	36	1			T11	2		T12	1		T13	2
all_values[4]	auto[0]	auto[0]	auto[1]	98	1			T12	1		T64	2		T13	1
all_values[4]	auto[0]	auto[1]	auto[0]	33	1			T11	2		T12	1		T64	1
all_values[4]	auto[0]	auto[1]	auto[1]	99	1			T64	2		T13	2		T95	2
all_values[4]	auto[1]	auto[0]	auto[1]	88	1			T12	1		T64	3		T13	2
all_values[4]	auto[1]	auto[1]	auto[1]	88	1			T13	3		T95	1		T96	1
all_values[5]	auto[0]	auto[0]	auto[0]	41	1			T11	1		T44	2		T203	2
all_values[5]	auto[0]	auto[0]	auto[1]	93	1			T12	2		T13	3		T95	3
all_values[5]	auto[0]	auto[1]	auto[0]	33	1			T11	3		T44	2		T199	1
all_values[5]	auto[0]	auto[1]	auto[1]	90	1			T64	3		T13	3		T96	1
all_values[5]	auto[1]	auto[0]	auto[1]	94	1			T64	3		T13	3		T95	1
all_values[5]	auto[1]	auto[1]	auto[1]	91	1			T12	2		T64	2		T13	3
all_values[6]	auto[0]	auto[0]	auto[0]	48	1			T12	3		T64	1		T95	2
all_values[6]	auto[0]	auto[0]	auto[1]	97	1			T11	1		T64	1		T13	5
all_values[6]	auto[0]	auto[1]	auto[0]	33	1			T12	1		T64	1		T95	2
all_values[6]	auto[0]	auto[1]	auto[1]	88	1			T11	1		T64	3		T13	1
all_values[6]	auto[1]	auto[0]	auto[1]	102	1			T11	1		T64	1		T13	3
all_values[6]	auto[1]	auto[1]	auto[1]	74	1			T11	1		T64	1		T13	3
all_values[7]	auto[0]	auto[0]	auto[0]	48	1			T44	1		T39	2		T200	1
all_values[7]	auto[0]	auto[0]	auto[1]	90	1			T11	2		T12	2		T64	3
all_values[7]	auto[0]	auto[1]	auto[0]	39	1			T11	1		T200	1		T201	4
all_values[7]	auto[0]	auto[1]	auto[1]	100	1			T64	3		T13	3		T95	2
all_values[7]	auto[1]	auto[0]	auto[1]	68	1			T11	1		T64	2		T13	3
all_values[7]	auto[1]	auto[1]	auto[1]	97	1			T12	2		T13	1		T44	1
all_values[8]	auto[0]	auto[0]	auto[0]	33	1			T13	6		T44	2		T200	1
all_values[8]	auto[0]	auto[0]	auto[1]	81	1			T11	1		T12	2		T64	1
all_values[8]	auto[0]	auto[1]	auto[0]	46	1			T11	1		T12	1		T13	3
all_values[8]	auto[0]	auto[1]	auto[1]	105	1			T64	3		T13	2		T95	1
all_values[8]	auto[1]	auto[0]	auto[1]	94	1			T12	1		T64	1		T96	1
all_values[8]	auto[1]	auto[1]	auto[1]	83	1			T11	2		T64	3		T13	1
all_values[9]	auto[0]	auto[0]	auto[0]	51	1			T13	1		T95	1		T44	3
all_values[9]	auto[0]	auto[0]	auto[1]	95	1			T64	3		T13	4		T96	1
all_values[9]	auto[0]	auto[1]	auto[0]	26	1			T96	2		T39	1		T201	1
all_values[9]	auto[0]	auto[1]	auto[1]	85	1			T11	2		T12	1		T64	3
all_values[9]	auto[1]	auto[0]	auto[1]	96	1			T12	1		T64	1		T13	3
all_values[9]	auto[1]	auto[1]	auto[1]	89	1			T11	2		T12	2		T64	1
all_values[10]	auto[0]	auto[0]	auto[0]	38	1			T13	2		T44	1		T202	1
all_values[10]	auto[0]	auto[0]	auto[1]	107	1			T12	1		T13	5		T44	3
all_values[10]	auto[0]	auto[1]	auto[0]	14	1			T11	1		T199	1		T204	1
all_values[10]	auto[0]	auto[1]	auto[1]	98	1			T11	1		T12	1		T64	5
all_values[10]	auto[1]	auto[0]	auto[1]	105	1			T11	1		T96	2		T44	2
all_values[10]	auto[1]	auto[1]	auto[1]	80	1			T11	1		T12	2		T64	3
all_values[11]	auto[0]	auto[0]	auto[0]	25	1			T13	1		T44	1		T205	1
all_values[11]	auto[0]	auto[0]	auto[1]	100	1			T11	2		T12	1		T64	1
all_values[11]	auto[0]	auto[1]	auto[0]	17	1			T12	2		T39	1		T201	1
all_values[11]	auto[0]	auto[1]	auto[1]	106	1			T64	2		T13	4		T39	2
all_values[11]	auto[1]	auto[0]	auto[1]	107	1			T11	1		T12	1		T64	1
all_values[11]	auto[1]	auto[1]	auto[1]	87	1			T11	1		T64	4		T13	4
all_values[12]	auto[0]	auto[0]	auto[0]	39	1			T13	2		T95	2		T39	2
all_values[12]	auto[0]	auto[0]	auto[1]	81	1			T11	2		T12	2		T13	3
all_values[12]	auto[0]	auto[1]	auto[0]	40	1			T95	2		T96	4		T200	2
all_values[12]	auto[0]	auto[1]	auto[1]	113	1			T11	1		T12	1		T64	3
all_values[12]	auto[1]	auto[0]	auto[1]	93	1			T64	1		T13	2		T44	4
all_values[12]	auto[1]	auto[1]	auto[1]	76	1			T11	1		T12	1		T64	4
all_values[13]	auto[0]	auto[0]	auto[0]	38	1			T13	2		T44	2		T200	1
all_values[13]	auto[0]	auto[0]	auto[1]	94	1			T64	2		T13	4		T95	1
all_values[13]	auto[0]	auto[1]	auto[0]	33	1			T12	4		T44	2		T39	2
all_values[13]	auto[0]	auto[1]	auto[1]	105	1			T11	2		T64	3		T13	1
all_values[13]	auto[1]	auto[0]	auto[1]	80	1			T64	2		T96	2		T39	1
all_values[13]	auto[1]	auto[1]	auto[1]	92	1			T11	2		T64	1		T13	5
all_values[14]	auto[0]	auto[0]	auto[0]	45	1			T39	2		T200	3		T140	1
all_values[14]	auto[0]	auto[0]	auto[1]	87	1			T11	1		T64	3		T13	3
all_values[14]	auto[0]	auto[1]	auto[0]	37	1			T12	1		T200	1		T199	3
all_values[14]	auto[0]	auto[1]	auto[1]	100	1			T11	1		T12	2		T64	4
all_values[14]	auto[1]	auto[0]	auto[1]	88	1			T12	1		T13	2		T95	2
all_values[14]	auto[1]	auto[1]	auto[1]	85	1			T11	2		T64	1		T13	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal