Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

230546

1

T2

124

T3

857

T9

78

ack

18984

1

T2

34

T3

146

T9

10

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	949	1			T3	2		T11	4		T30	1
high	50541	1			T2	34		T3	188		T9	19
med	92885	1			T2	59		T3	336		T9	40
sml	104161	1			T2	64		T3	472		T9	29
all_zero	994	1			T2	1		T3	5		T21	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124307

1

T2

75

T3

520

T9

45

auto[1]

125223

1

T2

83

T3

483

T9

43

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170651

1

T2

121

T3

687

T9

65

auto[1]

78879

1

T2

37

T3

316

T9

23

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238393

1

T2

143

T3

887

T9

88

auto[1]

11137

1

T2

15

T3

116

T10

12

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

235473

1

T2

127

T3

871

T9

78

auto[1]

14057

1

T2

31

T3

132

T9

10

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

237292

1

T2

128

T3

906

T9

78

auto[1]

12238

1

T2

30

T3

97

T9

10

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124307

1

T2

75

T3

520

T9

45

auto[1]

125223

1

T2

83

T3

483

T9

43

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170651

1

T2

121

T3

687

T9

65

auto[1]

78879

1

T2

37

T3

316

T9

23

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238393

1

T2

143

T3

887

T9

88

auto[1]

11137

1

T2

15

T3

116

T10

12

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

235473

1

T2

127

T3

871

T9

78

auto[1]

14057

1

T2

31

T3

132

T9

10

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

237292

1

T2

128

T3

906

T9

78

auto[1]

12238

1

T2

30

T3

97

T9

10

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

7

1

T214

1

T215

1

T216

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

6

1

T64

1

T217

1

T218

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

6

1

T219

1

T220

1

T221

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

671

1

T2

2

T3

6

T11

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

295

1

T2

1

T3

2

T30

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

309

1

T3

2

T10

1

T11

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1076

1

T2

2

T3

9

T11

5

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

573

1

T3

6

T11

2

T30

3

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

561

1

T2

2

T3

6

T11

2

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1091

1

T2

4

T3

10

T10

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

571

1

T3

5

T10

1

T11

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

565

1

T3

5

T10

1

T30

2

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

24

1

T2

1

T30

1

T222

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T177

1

T223

1

T224

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

11

1

T225

1

T63

1

T226

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	72648	1			T2	29		T3	235		T9	20
write_address_byte	14057	1			T2	31		T3	132		T9	10
read_with_ack	3948	1			T3	49		T30	45		T31	19
read_with_nack	7189	1			T2	15		T3	67		T10	12
stop_byte	12238	1			T2	30		T3	97		T9	10
write_address_byte_nak	9157	1			T2	18		T3	105		T10	14
data_byte_nack	230546	1			T2	124		T3	857		T9	78
stop_byte_nack	8904	1			T2	22		T3	77		T9	10
nakok_byte_nack	115731	1			T2	59		T3	417		T9	40
nakok_addr_byte_nack	4582	1			T2	10		T3	52		T10	9