Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48441656	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16569252

1

T1

11

T2

6499

T3

17823

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	57511995	1			T1	14		T2	48297		T3	38699
values[0x0]	3750086	1			T1	9		T2	272		T3	6843
values[0x1]	3748827	1			T1	6		T2	246		T3	6714

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35614735	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

29396173

1

T1

14

T2

19838

T3

26774

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	239548	1			T3	282		T6	37		T7	3
valid_sources[0x01]	233604	1			T2	73		T3	277		T6	35
valid_sources[0x02]	240703	1			T1	1		T2	70		T3	202
valid_sources[0x03]	285412	1			T2	3425		T3	210		T6	30
valid_sources[0x04]	223045	1			T3	223		T6	28		T9	5
valid_sources[0x05]	219763	1			T1	1		T2	59		T3	196
valid_sources[0x06]	219280	1			T2	230		T3	192		T6	25
valid_sources[0x07]	236219	1			T3	237		T6	15		T7	5
valid_sources[0x08]	230935	1			T2	70		T3	202		T6	35
valid_sources[0x09]	216041	1			T1	1		T3	206		T6	46
valid_sources[0x0a]	233913	1			T2	782		T3	159		T6	27
valid_sources[0x0b]	264255	1			T3	217		T6	22		T7	1
valid_sources[0x0c]	249113	1			T3	243		T6	25		T7	3
valid_sources[0x0d]	240420	1			T3	157		T6	32		T7	1
valid_sources[0x0e]	420846	1			T2	78		T3	331		T6	34
valid_sources[0x0f]	220987	1			T2	55		T3	211		T6	35
valid_sources[0x10]	259717	1			T3	190		T6	39		T9	16
valid_sources[0x11]	255775	1			T2	61		T3	150		T6	37
valid_sources[0x12]	214205	1			T3	213		T6	29		T9	3
valid_sources[0x13]	264321	1			T3	102		T6	35		T7	3
valid_sources[0x14]	249881	1			T2	85		T3	122		T6	25
valid_sources[0x15]	210301	1			T3	142		T6	22		T9	4
valid_sources[0x16]	218561	1			T3	211		T6	20		T7	5
valid_sources[0x17]	213840	1			T2	460		T3	242		T6	31
valid_sources[0x18]	242061	1			T1	2		T3	184		T6	45
valid_sources[0x19]	239363	1			T2	53		T3	190		T6	31
valid_sources[0x1a]	252317	1			T1	1		T2	70		T3	139
valid_sources[0x1b]	232244	1			T2	2872		T3	203		T6	31
valid_sources[0x1c]	231805	1			T2	135		T3	230		T6	27
valid_sources[0x1d]	246427	1			T2	62		T3	177		T6	30
valid_sources[0x1e]	217781	1			T3	123		T6	13		T7	2
valid_sources[0x1f]	240094	1			T2	70		T3	187		T6	37
valid_sources[0x20]	240004	1			T3	204		T6	23		T9	16
valid_sources[0x21]	229477	1			T3	213		T6	31		T7	2
valid_sources[0x22]	216274	1			T2	1851		T3	269		T6	17
valid_sources[0x23]	399766	1			T3	187		T6	18		T7	1
valid_sources[0x24]	233565	1			T3	192		T6	26		T7	1
valid_sources[0x25]	218854	1			T2	73		T3	174		T6	13
valid_sources[0x26]	251432	1			T3	279		T6	30		T7	2
valid_sources[0x27]	239730	1			T2	36		T3	202		T6	27
valid_sources[0x28]	258477	1			T1	1		T3	244		T6	33
valid_sources[0x29]	218046	1			T1	1		T2	117		T3	179
valid_sources[0x2a]	254524	1			T1	1		T3	181		T6	30
valid_sources[0x2b]	327024	1			T3	235		T6	26		T7	3
valid_sources[0x2c]	238587	1			T3	173		T6	25		T7	1
valid_sources[0x2d]	238454	1			T2	73		T3	196		T6	19
valid_sources[0x2e]	216961	1			T3	116		T6	19		T9	7
valid_sources[0x2f]	315153	1			T2	134		T3	213		T6	44
valid_sources[0x30]	273065	1			T3	242		T6	10		T7	2
valid_sources[0x31]	215066	1			T3	238		T6	26		T9	6
valid_sources[0x32]	236565	1			T2	66		T3	222		T6	25
valid_sources[0x33]	642979	1			T3	172		T6	37		T7	2
valid_sources[0x34]	221149	1			T3	127		T6	23		T7	1
valid_sources[0x35]	249000	1			T3	175		T6	34		T7	3
valid_sources[0x36]	213216	1			T2	53		T3	212		T6	29
valid_sources[0x37]	255351	1			T2	118		T3	145		T6	31
valid_sources[0x38]	219278	1			T3	162		T6	26		T7	4
valid_sources[0x39]	236919	1			T2	132		T3	174		T6	34
valid_sources[0x3a]	228429	1			T3	176		T6	27		T7	1
valid_sources[0x3b]	226210	1			T3	175		T6	24		T7	2
valid_sources[0x3c]	348101	1			T1	1		T3	157		T6	43
valid_sources[0x3d]	221428	1			T2	72		T3	133		T6	22
valid_sources[0x3e]	375955	1			T3	246		T6	36		T7	1
valid_sources[0x3f]	222407	1			T2	2467		T3	253		T6	23
valid_sources[0x40]	220186	1			T2	135		T3	232		T6	42
valid_sources[0x41]	285284	1			T3	236		T6	23		T9	9
valid_sources[0x42]	219484	1			T3	203		T6	22		T7	2
valid_sources[0x43]	219235	1			T2	124		T3	123		T6	38
valid_sources[0x44]	226178	1			T3	207		T6	37		T7	2
valid_sources[0x45]	215061	1			T2	1143		T3	155		T6	33
valid_sources[0x46]	236479	1			T3	155		T6	22		T9	14
valid_sources[0x47]	250888	1			T3	151		T6	23		T7	3
valid_sources[0x48]	248731	1			T3	186		T6	17		T7	4
valid_sources[0x49]	227514	1			T3	242		T6	22		T9	17
valid_sources[0x4a]	225062	1			T2	210		T3	225		T6	35
valid_sources[0x4b]	213021	1			T3	216		T6	24		T7	3
valid_sources[0x4c]	216621	1			T1	1		T2	62		T3	218
valid_sources[0x4d]	337677	1			T2	73		T3	251		T6	44
valid_sources[0x4e]	232583	1			T3	215		T6	46		T9	12
valid_sources[0x4f]	217033	1			T2	72		T3	135		T6	19
valid_sources[0x50]	222699	1			T3	186		T6	40		T7	3
valid_sources[0x51]	233928	1			T2	143		T3	255		T6	33
valid_sources[0x52]	254648	1			T2	1776		T3	132		T6	38
valid_sources[0x53]	216916	1			T3	120		T6	34		T7	4
valid_sources[0x54]	229307	1			T2	108		T3	228		T6	38
valid_sources[0x55]	227046	1			T2	55		T3	209		T6	21
valid_sources[0x56]	215063	1			T2	796		T3	305		T6	22
valid_sources[0x57]	214776	1			T2	153		T3	164		T6	29
valid_sources[0x58]	233131	1			T2	124		T3	144		T6	14
valid_sources[0x59]	220531	1			T2	62		T3	151		T6	27
valid_sources[0x5a]	232673	1			T2	133		T3	304		T6	32
valid_sources[0x5b]	235420	1			T2	1757		T3	297		T6	21
valid_sources[0x5c]	216353	1			T2	70		T3	265		T6	21
valid_sources[0x5d]	245210	1			T2	73		T3	186		T6	27
valid_sources[0x5e]	215960	1			T3	182		T6	19		T9	13
valid_sources[0x5f]	217529	1			T3	183		T6	34		T7	1
valid_sources[0x60]	221851	1			T3	235		T6	24		T9	6
valid_sources[0x61]	253259	1			T2	134		T3	158		T6	40
valid_sources[0x62]	446662	1			T2	652		T3	291		T6	26
valid_sources[0x63]	213295	1			T2	69		T3	204		T6	32
valid_sources[0x64]	247260	1			T3	229		T6	21		T7	3
valid_sources[0x65]	217751	1			T3	159		T6	26		T7	2
valid_sources[0x66]	395025	1			T2	67		T3	184		T6	35
valid_sources[0x67]	233297	1			T3	282		T6	19		T7	2
valid_sources[0x68]	216188	1			T3	281		T6	24		T7	5
valid_sources[0x69]	223681	1			T3	209		T6	39		T7	2
valid_sources[0x6a]	320705	1			T2	999		T3	209		T6	34
valid_sources[0x6b]	248742	1			T3	237		T6	45		T7	1
valid_sources[0x6c]	239014	1			T2	36		T3	227		T6	21
valid_sources[0x6d]	241259	1			T2	71		T3	327		T6	29
valid_sources[0x6e]	439104	1			T2	371		T3	150		T6	30
valid_sources[0x6f]	221961	1			T2	73		T3	232		T6	27
valid_sources[0x70]	255434	1			T3	258		T6	35		T7	4
valid_sources[0x71]	233482	1			T3	215		T6	19		T7	1
valid_sources[0x72]	242713	1			T3	181		T6	31		T7	1
valid_sources[0x73]	223059	1			T3	231		T6	37		T7	2
valid_sources[0x74]	276379	1			T2	55		T3	190		T6	20
valid_sources[0x75]	254636	1			T1	1		T3	178		T6	46
valid_sources[0x76]	225406	1			T3	195		T6	21		T9	2
valid_sources[0x77]	220096	1			T3	224		T6	33		T7	2
valid_sources[0x78]	225362	1			T2	73		T3	136		T6	30
valid_sources[0x79]	245502	1			T3	199		T6	44		T7	2
valid_sources[0x7a]	212071	1			T3	219		T6	25		T9	13
valid_sources[0x7b]	222954	1			T3	184		T6	50		T7	2
valid_sources[0x7c]	223665	1			T2	526		T3	189		T6	36
valid_sources[0x7d]	232144	1			T1	1		T3	236		T6	29
valid_sources[0x7e]	222932	1			T3	167		T6	32		T9	8
valid_sources[0x7f]	215633	1			T2	138		T3	187		T6	13
valid_sources[0x80]	258287	1			T3	170		T6	21		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

13718048

1

T1

5

T2

6178

T3

12278

values[0x0]

all_enables

biggest_size

1839314

1

T1

5

T2

186

T3

3549

values[0x1]

all_enables

biggest_size

1011890

1

T1

1

T2

135

T3

1996