SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 93.75 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
i2c_env_pkg.b2b_txn_target_cg | 87.50 | 1 | 100 | 1 | 64 | 64 |
i2c_env_pkg.b2b_txn_host_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
87.50 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 1 | 7 | 87.50 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
B2B_txn_cp | 8 | 1 | 7 | 87.50 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
B2B_txn_cp | 8 | 0 | 8 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 8 | 1 | 7 | 87.50 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
b2b_read_different_addr | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
b2b_read_same_addr | 1 | 1 | T232 | 1 | - | - | - | - | ||||
write_after_read_different_addr | 16551 | 1 | T6 | 52 | T8 | 19 | T18 | 29 | ||||
write_after_read_same_addr | 313 | 1 | T233 | 16 | T234 | 29 | T210 | 12 | ||||
read_after_write_different_addr | 16546 | 1 | T6 | 52 | T8 | 19 | T18 | 29 | ||||
read_after_write_same_addr | 313 | 1 | T233 | 16 | T234 | 29 | T210 | 12 | ||||
b2b_write_different_addr | 39338 | 1 | T6 | 18 | T7 | 14 | T18 | 84 | ||||
b2b_write_same_addr | 367586 | 1 | T6 | 1903 | T7 | 171 | T8 | 220 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 8 | 0 | 8 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
b2b_read_different_addr | 4151 | 1 | T2 | 2 | T3 | 23 | T9 | 1 | ||||
b2b_read_same_addr | 821 | 1 | T2 | 1 | T3 | 22 | T30 | 7 | ||||
write_after_read_different_addr | 4171 | 1 | T2 | 10 | T3 | 27 | T9 | 2 | ||||
write_after_read_same_addr | 57 | 1 | T10 | 1 | T31 | 1 | T73 | 1 | ||||
read_after_write_different_addr | 4144 | 1 | T2 | 8 | T3 | 27 | T9 | 2 | ||||
read_after_write_same_addr | 74 | 1 | T2 | 1 | T9 | 1 | T30 | 1 | ||||
b2b_write_different_addr | 4187 | 1 | T2 | 11 | T3 | 29 | T9 | 3 | ||||
b2b_write_same_addr | 867 | 1 | T3 | 17 | T11 | 1 | T30 | 12 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |