Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fifo_level_cg

Group : i2c_env_pkg::i2c_fifo_level_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	94.12	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.rx_fifo_level_cg	88.24	1	100	1	64	64
i2c_env_pkg.fmt_fifo_level_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	8	2	6	75.00

Variables for Group Instance i2c_env_pkg.rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_fifolvl	5	0	5	100.00	100	1	1	0
cp_irq	2	0	2	100.00	100	1	1	2
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fifo_threshold_cross	8	2	6	75.00	100	1	1	0

---

Group Instance : i2c_env_pkg.fmt_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.fmt_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_fifolvl	5	0	5	100.00	100	1	1	0
cp_irq	2	0	2	100.00	100	1	1	2
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fifo_threshold_cross	8	0	8	100.00	100	1	1	0

Summary for Variable cp_fifolvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fifolvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others	31920	1			T1	1		T2	32		T3	107
lvl[1]	223	1			T74	1		T136	3		T235	3
lvl[4]	185	1			T74	3		T235	3		T236	2
lvl[8]	156	1			T74	3		T136	5		T235	3
lvl[16]	147	1			T136	3		T237	2		T236	3

---

Summary for Variable cp_irq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_irq

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28624

1

T1

1

T2

5

T3

107

auto[1]

4007

1

T2

27

T10

22

T11

24

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30097

1

T2

31

T3

106

T6

68

auto[1]

2534

1

T1

1

T2

1

T3

1

---

Summary for Cross cp_fifo_threshold_cross

Samples crossed: cp_fifolvl cp_irq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	2	6	75.00	2
Automatically Generated Cross Bins	8	2	6	75.00	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_fifo_threshold_cross

Uncovered bins

cp_fifolvl	cp_irq	COUNT	AT LEAST	NUMBER	STATUS
[lvl[8] , lvl[16]]	[auto[1]]	--	--	2

Covered bins

cp_fifolvl	cp_irq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lvl[1]	auto[0]	193	1			T74	1		T136	3		T235	3
lvl[1]	auto[1]	30	1			T163	8		T154	22		-	-
lvl[4]	auto[0]	172	1			T74	3		T235	3		T236	2
lvl[4]	auto[1]	13	1			T238	9		T239	4		-	-
lvl[8]	auto[0]	156	1			T74	3		T136	5		T235	3
lvl[16]	auto[0]	147	1			T136	3		T237	2		T236	3

User Defined Cross Bins for cp_fifo_threshold_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
reserved_values	0	Excluded

Summary for Variable cp_fifolvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fifolvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others	30233	1			T1	1		T2	32		T3	107
lvl[1]	1436	1			T74	14		T42	2		T136	15
lvl[4]	335	1			T74	1		T41	2		T42	2
lvl[8]	349	1			T40	2		T74	4		T136	3
lvl[16]	278	1			T74	1		T136	6		T235	6

---

Summary for Variable cp_irq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_irq

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26510

1

T1

1

T2

6

T3

107

auto[1]

6121

1

T2

26

T9

7

T21

6

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29744

1

T2

31

T3

106

T6

68

auto[1]

2887

1

T1

1

T2

1

T3

1

---

Summary for Cross cp_fifo_threshold_cross

Samples crossed: cp_fifolvl cp_irq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_fifo_threshold_cross

Bins

cp_fifolvl	cp_irq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lvl[1]	auto[0]	1119	1			T74	14		T136	15		T235	10
lvl[1]	auto[1]	317	1			T42	2		T240	4		T241	2
lvl[4]	auto[0]	286	1			T74	1		T41	2		T136	3
lvl[4]	auto[1]	49	1			T42	2		T242	2		T243	2
lvl[8]	auto[0]	314	1			T74	4		T136	3		T235	1
lvl[8]	auto[1]	35	1			T40	2		T242	2		T244	2
lvl[16]	auto[0]	275	1			T74	1		T136	6		T235	6
lvl[16]	auto[1]	3	1			T242	1		T245	2		-	-

User Defined Cross Bins for cp_fifo_threshold_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
reserved_values	0	Excluded