Unified Coverage Report :: Module :: i2c_fsm

Module : i2c_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.85	98.56	94.63		75.35	95.74	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_fsm	96.39	98.56	94.63		93.04	95.74	100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.39	98.56	94.63		93.04	95.74	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.39	98.56	94.63		93.04	95.74	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.44	97.00	77.22			94.12		i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : i2c_fsm

	Line No.	Total	Covered	Percent
TOTAL		554	546	98.56
ALWAYS	153	17	17	100.00
CONT_ASSIGN	177	1	1	100.00
ALWAYS	180	3	3	100.00
ALWAYS	193	9	9	100.00
ALWAYS	209	7	7	100.00
ALWAYS	222	6	6	100.00
ALWAYS	233	5	5	100.00
ALWAYS	240	7	7	100.00
ALWAYS	253	5	5	100.00
ALWAYS	267	8	8	100.00
ALWAYS	279	8	7	87.50
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
ALWAYS	301	9	9	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	318	1	1	100.00
ALWAYS	322	7	7	100.00
ALWAYS	333	5	5	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	347	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
ALWAYS	410	6	6	100.00
CONT_ASSIGN	428	1	1	100.00
ALWAYS	433	4	4	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	458	180	174	96.67
CONT_ASSIGN	804	1	1	100.00
CONT_ASSIGN	813	1	1	100.00
CONT_ASSIGN	818	1	1	100.00
ALWAYS	822	239	238	99.58
ALWAYS	1322	3	3	100.00
ALWAYS	1331	5	5	100.00
CONT_ASSIGN	1340	1	1	100.00
CONT_ASSIGN	1341	1	1	100.00
CONT_ASSIGN	1344	1	1	100.00
CONT_ASSIGN	1347	1	1	100.00
CONT_ASSIGN	1351	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
169	1	1
170	1	1
172	1	1
177	1	1
180	1	1
181	1	1
183	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
199	1	1
200	1	1
201	1	1
203	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
216	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
			MISSING_ELSE
233	2	2
234	2	2
235	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
247	1	1
253	1	1
254	1	1
255	1	1
257	1	1
258	1	1
267	1	1
268	1	1
269	1	1
270	1	1
271	1	1
272	1	1
273	1	1
274	1	1
			MISSING_ELSE
279	1	1
280	1	1
281	1	1
282	0	1
283	1	1
284	1	1
285	1	1
286	1	1
			MISSING_ELSE
291	1	1
294	1	1
297	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
308	2	2
309	1	1
311	1	1
316	1	1
317	1	1
318	1	1
322	1	1
323	1	1
324	1	1
325	1	1
326	1	1
327	2	2
			MISSING_ELSE
			MISSING_ELSE
333	1	1
334	1	1
335	1	1
336	2	2
			MISSING_ELSE
			MISSING_ELSE
346	1	1
347	1	1
405	1	1
410	1	1
411	1	1
412	1	1
416	1	1
417	1	1
418	1	1
			MISSING_ELSE
428	1	1
433	1	1
434	1	1
435	1	1
436	1	1
			MISSING_ELSE
450	1	1
454	1	1
458	1	1
459	1	1
460	1	1
461	1	1
462	1	1
463	1	1
464	1	1
465	1	1
466	1	1
467	1	1
468	1	1
469	1	1
470	1	1
471	1	1
472	1	1
473	1	1
474	1	1
475	1	1
480	1	1
481	1	1
482	0	1
483	0	1
485	1	1
486	1	1
491	1	1
492	1	1
493	1	1
494	2	2
			MISSING_ELSE
498	1	1
499	1	1
500	1	1
504	1	1
505	1	1
506	1	1
509	1	1
510	1	1
511	1	1
513	1	1
515	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	2
			MISSING_ELSE
524	2	2
			MISSING_ELSE
528	1	1
529	1	1
530	1	1
534	1	1
535	1	1
536	1	1
540	1	1
541	1	1
542	1	1
543	2	2
			MISSING_ELSE
544	1	1
545	1	2
			MISSING_ELSE
546	2	2
			MISSING_ELSE
550	1	1
551	1	1
552	1	1
556	1	1
557	1	1
558	1	1
562	1	1
563	1	1
564	1	1
565	1	2
			MISSING_ELSE
566	2	2
			MISSING_ELSE
570	1	1
571	1	1
572	1	1
573	1	1
574	1	1
			MISSING_ELSE
579	1	1
580	1	1
584	2	2
585	2	2
586	1	1
590	1	1
591	2	2
592	2	2
593	1	1
594	1	1
595	1	1
596	1	2
			MISSING_ELSE
597	2	2
			MISSING_ELSE
601	1	1
602	2	2
603	2	2
604	1	1
605	1	1
609	1	1
610	1	1
611	1	1
615	1	1
616	1	1
617	1	1
621	1	1
622	1	1
623	1	1
624	1	1
628	1	1
634	1	1
638	1	1
639	2	2
640	1	1
641	1	1
645	1	1
649	1	1
650	1	1
654	1	1
658	1	1
659	1	1
663	1	1
664	1	1
668	1	1
669	1	1
672	1	1
674	1	1
675	1	1
			MISSING_ELSE
680	1	1
684	1	1
685	1	1
689	1	1
692	1	1
696	1	1
699	1	1
703	1	1
706	1	1
707	1	1
709	1	1
			MISSING_ELSE
714	1	1
715	1	1
716	1	1
720	1	1
724	1	1
728	1	1
729	1	1
733	1	1
734	1	1
738	1	1
739	1	1
741	1	1
742	1	1
743	1	1
			MISSING_ELSE
749	1	1
750	1	1
752	1	1
753	1	1
757	1	1
758	1	1
762	1	1
763	1	1
764	1	1
768	1	1
769	1	1
772	1	1
773	1	1
795	1	1
797	1	1
798	1	1
800	1	1
			MISSING_ELSE
804	1	1
813	1	1
818	1	1
822	1	1
823	1	1
824	1	1
825	1	1
826	1	1
827	1	1
828	1	1
829	1	1
830	1	1
831	1	1
832	1	1
833	1	1
834	1	1
835	1	1
836	1	1
838	1	1
841	2	2
842	1	1
843	2	2
			MISSING_ELSE
			MISSING_ELSE
849	1	1
850	1	1
851	1	1
852	1	1
853	1	1
			MISSING_ELSE
858	1	1
859	1	1
860	1	1
861	1	1
			MISSING_ELSE
866	1	1
867	1	1
868	1	1
869	1	1
			MISSING_ELSE
874	1	1
875	1	1
876	1	1
877	1	1
878	1	1
879	1	1
881	1	1
882	1	1
			MISSING_ELSE
889	1	1
890	1	1
891	1	1
892	1	1
893	1	1
			MISSING_ELSE
898	1	1
899	1	1
900	1	1
901	1	1
902	1	1
903	1	1
904	1	1
905	1	1
907	1	1
908	1	1
			MISSING_ELSE
915	1	1
916	1	1
917	1	1
918	1	1
			MISSING_ELSE
923	1	1
924	1	1
925	1	1
926	1	1
			MISSING_ELSE
931	1	1
932	1	1
933	1	1
934	1	1
935	1	1
937	1	1
938	1	1
939	1	1
			MISSING_ELSE
945	1	1
946	1	1
947	1	1
948	1	1
			MISSING_ELSE
953	1	1
954	1	1
955	1	1
956	1	1
957	1	1
			MISSING_ELSE
962	1	1
963	1	1
964	1	1
965	1	1
966	1	1
967	1	1
968	1	1
970	1	1
971	1	1
			MISSING_ELSE
978	1	1
979	1	1
980	1	1
981	1	1
982	1	1
			MISSING_ELSE
987	1	1
988	1	1
989	1	1
990	1	1
991	1	1
			MISSING_ELSE
996	1	1
997	1	1
998	1	1
999	1	1
1000	1	1
1001	1	1
1002	1	1
1003	1	1
1005	1	1
1006	1	1
1007	1	1
1010	1	1
1011	1	1
1012	1	1
1013	1	1
			MISSING_ELSE
1020	1	1
1021	1	1
1022	1	1
1023	1	1
			MISSING_ELSE
1028	1	1
1029	1	1
1030	1	1
1031	1	1
1032	1	1
			MISSING_ELSE
1037	1	1
1038	1	1
1039	1	1
1040	1	1
1041	1	1
1042	1	1
1043	1	1
1045	1	1
1046	1	1
1047	1	1
			MISSING_ELSE
1054	1	1
1055	1	1
1056	1	1
1057	1	1
1058	1	1
1059	1	1
1060	1	1
1061	1	1
1062	1	1
1064	1	1
1065	1	1
1066	1	1
1067	1	1
1073	1	1
1074	1	1
1075	1	1
1076	1	1
1077	1	1
1078	1	1
1079	1	1
1080	1	1
1082	1	1
1083	1	1
1084	1	1
1090	1	1
1092	1	1
1093	1	1
			MISSING_ELSE
1099	1	1
1100	1	1
1101	1	1
1102	1	1
1103	1	1
1104	1	1
			MISSING_ELSE
1110	1	1
1111	1	1
			MISSING_ELSE
1116	2	2
			MISSING_ELSE
1120	1	1
1121	1	1
1122	1	1
1123	1	1
			MISSING_ELSE
1128	1	1
1132	1	1
1133	1	1
1134	1	1
1135	1	1
1136	1	1
1137	1	1
			==> MISSING_ELSE
			MISSING_ELSE
1143	1	1
1144	1	1
1146	1	1
1147	1	1
1148	1	1
1153	2	2
			MISSING_ELSE
1157	1	1
1158	1	1
1159	1	1
1160	1	1
			MISSING_ELSE
1165	1	1
1166	1	1
1167	1	1
1169	1	1
1170	1	1
1171	1	1
			MISSING_ELSE
1178	1	1
1179	1	1
			MISSING_ELSE
1186	1	1
1188	1	1
1189	1	1
1192	1	1
			MISSING_ELSE
1201	1	1
1206	1	1
1207	1	1
1208	1	1
1209	1	1
			MISSING_ELSE
1215	1	1
1216	1	1
			MISSING_ELSE
1221	2	2
			MISSING_ELSE
1225	1	1
1226	1	1
1227	1	1
1228	1	1
			MISSING_ELSE
1233	1	1
1236	1	1
			MISSING_ELSE
1242	1	1
1248	1	1
			MISSING_ELSE
1254	1	1
1255	1	1
1262	1	1
1263	1	1
1264	1	1
1267	1	1
			MISSING_ELSE
1271	1	1
1272	1	1
			MISSING_ELSE
1279	2	2
			MISSING_ELSE
1303	1	1
1312	0	1
1313	1	1
1314	1	1
1315	1	1
1316	1	1
			MISSING_ELSE
1322	1	1
1323	1	1
1325	1	1
1331	1	1
1332	1	1
1333	1	1
1335	1	1
1336	1	1
1340	1	1
1341	1	1
1344	1	1
1347	1	1
1351	1	1

---

Cond Coverage for Module : i2c_fsm

	Total	Covered	Percent
Conditions	242	229	94.63
Logical	242	229	94.63
Non-Logical	0	0
Event	0	0

 LINE       169
 EXPRESSION ((stretch_idle_cnt == '0) || target_enable_i)
             ------------1-----------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T9
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3

 LINE       169
 SUB-EXPRESSION (stretch_idle_cnt == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (stretch_en && scl_d && ((!scl_i)))
             -----1----    --2--    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T2,T3,T9
1	1	1	Covered	T2,T3,T9

 LINE       197
 EXPRESSION (((!target_idle_o)) && event_host_timeout_o)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T8
1	1	Covered	T15,T22,T23

 LINE       200
 EXPRESSION (((!target_idle_o)) && scl_i)
             ---------1--------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       234
 EXPRESSION (fmt_byte_i == '0)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T24,T25,T26

 LINE       269
 EXPRESSION (trans_started && ((!host_enable_i)))
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T27,T28,T29

 LINE       281
 EXPRESSION (pend_restart && ((!host_enable_i)))
             ------1-----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T30,T31
1	1	Not Covered

 LINE       291
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i)))))
             -------1-------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       291
 SUB-EXPRESSION ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i))))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       291
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       291
 SUB-EXPRESSION (sda_i_q && ((!sda_i)))
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       294
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i)))
             -------1-------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       294
 SUB-EXPRESSION ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       294
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       294
 SUB-EXPRESSION (((!sda_i_q)) && sda_i)
                 ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       297
 EXPRESSION (bit_idx == 4'd8)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       305
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       308
 EXPRESSION (input_byte_clr || bit_ack)
             -------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T6,T7,T8

 LINE       316
 EXPRESSION ((input_byte[7:1] & target_mask0_i) == target_address0_i)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       317
 EXPRESSION ((input_byte[7:1] & target_mask1_i) == target_address1_i)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       318
 EXPRESSION (address0_match || address1_match)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8

 LINE       326
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       412
 EXPRESSION (((!en_sda_interf_det)) && ((|sda_rise_cnt)))
             -----------1----------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T9

 LINE       417
 EXPRESSION (en_sda_interf_det && (sda_rise_cnt < sda_rise_latency))
             --------1--------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T2,T3,T9

 LINE       428
 EXPRESSION ((host_idle_o & host_enable_i & ((!sda_i))) | ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i))))
             ---------------------1--------------------   ----------------------------2----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T2,T3

 LINE       428
 SUB-EXPRESSION (host_idle_o & host_enable_i & ((!sda_i)))
                 -----1-----   ------2------   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T9
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       428
 SUB-EXPRESSION ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i)))
                 -----------------1----------------   --2--   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T9
1	1	0	Covered	T2,T3,T9
1	1	1	Covered	T2,T3,T9

 LINE       428
 SUB-EXPRESSION (sda_rise_cnt == sda_rise_latency)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T9

 LINE       435
 EXPRESSION (bit_ack && address_match)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T2,T3,T6

 LINE       454
 EXPRESSION (((!target_idle)) & rw_bit_q & stop_det & ((!expect_stop)))
             --------1-------   ----2---   ----3---   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T7,T32,T33
1	0	1	1	Covered	T6,T7,T8
1	1	0	1	Covered	T6,T7,T8
1	1	1	0	Covered	T6,T7,T8
1	1	1	1	Covered	T6,T34,T23

 LINE       481
 EXPRESSION (host_enable_i && trans_started)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       523
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T2,T3,T9
1	1	Not Covered

 LINE       524
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T30

 LINE       543
 EXPRESSION (((!scl_i_q)) && scl_i && sda_i && ((!fmt_flag_nak_ok_i)))
             ------1-----    --2--    --3--    -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T35,T27,T36
1	0	1	1	Covered	T2,T3,T9
1	1	0	1	Covered	T2,T3,T9
1	1	1	0	Covered	T37,T38,T39
1	1	1	1	Covered	T35,T27,T36

 LINE       545
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T2,T3,T9
1	1	Not Covered

 LINE       546
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       565
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
1	1	Not Covered

 LINE       566
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       572
 EXPRESSION ((bit_index == '0) && (tcount_q == 20'b1))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
1	1	Covered	T2,T3,T10

 LINE       572
 SUB-EXPRESSION (bit_index == '0)
                --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       572
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       585
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       592
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       596
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
1	1	Not Covered

 LINE       597
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T3,T30,T31

 LINE       603
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       634
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T42
1	0	Covered	T3,T30,T31
1	1	Covered	T2,T3,T9

 LINE       672
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       741
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       795
 EXPRESSION (start_det || stop_det)
             ----1----    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8

 LINE       798
 EXPRESSION (start_det ? ({AcqRestart, input_byte}) : ({AcqStop, input_byte}))
             ----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       813
 EXPRESSION (((~tx_fifo_rvalid_i)) | (acq_fifo_depth_i > 7'(1'b1)))
             ----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3

 LINE       841
 EXPRESSION (((!host_enable_i)) && ((!target_enable_i)))
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T3

 LINE       849
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       858
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       866
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T9,T21
1	Covered	T2,T3,T9

 LINE       875
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       890
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       899
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       903
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       915
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       923
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       931
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       945
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       953
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       962
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       965
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       979
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       988
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       997
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       999
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       1020
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       1028
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       1038
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       1059
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T42
1	0	Covered	T3,T30,T31
1	1	Covered	T2,T3,T9

 LINE       1077
 EXPRESSION (fmt_fifo_depth_i == 7'b1)
            -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       1090
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T43,T44
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       1099
 EXPRESSION (bit_ack && address_match)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T7,T32,T33
1	1	Covered	T6,T7,T8

 LINE       1103
 EXPRESSION (bit_ack && ((!address_match)))
             ---1---    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T7,T32,T33

 LINE       1110
 EXPRESSION ((tcount_q == 20'b1) && ((!scl_i)))
             ---------1---------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T6,T7,T8

 LINE       1110
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       1128
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       1165
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       1215
 EXPRESSION ((tcount_q == 20'b1) && ((!scl_i)))
             ---------1---------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T6,T7,T8

 LINE       1215
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       1233
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       1236
 EXPRESSION (acq_fifo_wready ? AcquireByte : StretchAcqFull)
             -------1-------

-1-	Status	Tests
0	Covered	T6,T20,T45
1	Covered	T6,T7,T8

 LINE       1248
 EXPRESSION (rw_bit_q ? StretchTx : AcquireByte)
             ----1---

-1-	Status	Tests
0	Covered	T6,T20,T45
1	Covered	T46,T47,T48

 LINE       1271
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       1303
 EXPRESSION (((!target_idle)) && ((!target_enable_i)))
             --------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Not Covered

 LINE       1344
 EXPRESSION (((!target_idle_o)) & (stretch_idle_cnt > host_timeout_i))
             ---------1--------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T6,T7,T8
1	1	Covered	T15,T22,T23

 LINE       1347
 EXPRESSION (stretch_en && (stretch_idle_cnt[30:0] > stretch_timeout_i) && timeout_enable_i)
             -----1----    ----------------------2---------------------    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T7,T8
1	0	1	Covered	T2,T3,T9
1	1	0	Covered	T3,T9,T21
1	1	1	Covered	T2,T3,T9

---

FSM Coverage for Module : i2c_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	43	43	100.00	(Not included in score)
Transitions	142	107	75.35
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AcquireAckHold	1226	Covered	T6,T7,T8
AcquireAckPulse	1221	Covered	T6,T7,T8
AcquireAckSetup	1216	Covered	T6,T7,T8
AcquireAckWait	1207	Covered	T6,T7,T8
AcquireByte	1137	Covered	T6,T7,T8
AcquireStart	1314	Covered	T6,T7,T8
Active	843	Covered	T2,T3,T9
AddrAckHold	1121	Covered	T6,T7,T8
AddrAckPulse	1116	Covered	T6,T7,T8
AddrAckSetup	1111	Covered	T6,T7,T8
AddrAckWait	1100	Covered	T6,T7,T8
AddrRead	1092	Covered	T6,T7,T8
ClockLow	867	Covered	T2,T3,T9
ClockLowAck	904	Covered	T2,T3,T9
ClockPulse	881	Covered	T2,T3,T9
ClockPulseAck	916	Covered	T2,T3,T9
ClockStart	859	Covered	T2,T3,T9
ClockStop	933	Covered	T2,T3,T9
HoldBit	891	Covered	T2,T3,T9
HoldDevAck	924	Covered	T2,T3,T9
HoldStart	850	Covered	T2,T3,T9
HoldStop	1029	Covered	T2,T3,T9
HostClockLowAck	966	Covered	T2,T3,T10
HostClockPulseAck	980	Covered	T2,T3,T10
HostHoldBitAck	989	Covered	T2,T3,T10
Idle	841	Covered	T1,T2,T3
PopFmtFifo	937	Covered	T2,T3,T9
ReadClockLow	970	Covered	T2,T3,T10
ReadClockPulse	946	Covered	T2,T3,T10
ReadHoldBit	954	Covered	T2,T3,T10
SetupStart	878	Covered	T2,T3,T9
SetupStop	1021	Covered	T2,T3,T9
StretchAcqFull	1236	Covered	T6,T20,T45
StretchAddr	1133	Covered	T6,T20,T45
StretchTx	1144	Covered	T6,T7,T8
StretchTxSetup	1262	Covered	T6,T7,T8
TransmitAck	1167	Covered	T6,T7,T8
TransmitAckPulse	1179	Covered	T6,T7,T8
TransmitHold	1158	Covered	T6,T7,T8
TransmitPulse	1153	Covered	T6,T7,T8
TransmitSetup	1146	Covered	T6,T7,T8
TransmitWait	1135	Covered	T6,T7,T8
WaitForStop	1192	Covered	T6,T7,T8

transitions	Line No.	Covered	Tests
AcquireAckHold->AcquireByte	1236	Covered	T6,T7,T8
AcquireAckHold->AcquireStart	1314	Covered	T43,T44
AcquireAckHold->Idle	1312	Covered	T43,T44
AcquireAckHold->StretchAcqFull	1236	Covered	T6,T20,T45
AcquireAckPulse->AcquireAckHold	1226	Covered	T6,T7,T8
AcquireAckPulse->AcquireStart	1314	Covered	T43,T44
AcquireAckPulse->Idle	1312	Covered	T43,T44
AcquireAckSetup->AcquireAckPulse	1221	Covered	T6,T7,T8
AcquireAckSetup->AcquireStart	1314	Covered	T43,T44
AcquireAckSetup->Idle	1312	Covered	T43,T44
AcquireAckWait->AcquireAckSetup	1216	Covered	T6,T7,T8
AcquireAckWait->AcquireStart	1314	Covered	T43,T44
AcquireAckWait->Idle	1312	Covered	T43,T44
AcquireByte->AcquireAckWait	1207	Covered	T6,T7,T8
AcquireByte->AcquireStart	1314	Covered	T6,T7,T8
AcquireByte->Idle	1312	Covered	T6,T7,T8
AcquireStart->AddrRead	1092	Covered	T6,T7,T8
AcquireStart->Idle	1312	Covered	T43,T44
Active->AcquireStart	1314	Not Covered
Active->ClockLow	1064	Covered	T2,T3,T9
Active->Idle	1312	Not Covered
Active->ReadClockLow	1056	Covered	T2,T3,T10
Active->SetupStart	1060	Covered	T2,T3,T9
AddrAckHold->AcquireByte	1137	Covered	T6,T7,T8
AddrAckHold->AcquireStart	1314	Covered	T43,T44
AddrAckHold->Idle	1312	Covered	T43,T44
AddrAckHold->StretchAddr	1133	Covered	T6,T20,T45
AddrAckHold->TransmitWait	1135	Covered	T6,T7,T8
AddrAckPulse->AcquireStart	1314	Covered	T43,T44
AddrAckPulse->AddrAckHold	1121	Covered	T6,T7,T8
AddrAckPulse->Idle	1312	Covered	T43,T44
AddrAckSetup->AcquireStart	1314	Covered	T43,T44
AddrAckSetup->AddrAckPulse	1116	Covered	T6,T7,T8
AddrAckSetup->Idle	1312	Covered	T43,T44
AddrAckWait->AcquireStart	1314	Covered	T43,T44
AddrAckWait->AddrAckSetup	1111	Covered	T6,T7,T8
AddrAckWait->Idle	1312	Covered	T43,T44
AddrRead->AcquireStart	1314	Covered	T49,T50,T51
AddrRead->AddrAckWait	1100	Covered	T6,T7,T8
AddrRead->Idle	1104	Covered	T7,T52,T32
ClockLow->AcquireStart	1314	Not Covered
ClockLow->ClockPulse	881	Covered	T2,T3,T9
ClockLow->Idle	1312	Covered	T35,T53,T54
ClockLow->SetupStart	878	Covered	T3,T30,T31
ClockLowAck->AcquireStart	1314	Not Covered
ClockLowAck->ClockPulseAck	916	Covered	T2,T3,T9
ClockLowAck->Idle	1312	Not Covered
ClockPulse->AcquireStart	1314	Not Covered
ClockPulse->HoldBit	891	Covered	T2,T3,T9
ClockPulse->Idle	1312	Covered	T35,T53,T54
ClockPulseAck->AcquireStart	1314	Not Covered
ClockPulseAck->HoldDevAck	924	Covered	T2,T3,T9
ClockPulseAck->Idle	1312	Covered	T35,T53,T55
ClockStart->AcquireStart	1314	Not Covered
ClockStart->ClockLow	867	Covered	T2,T3,T9
ClockStart->Idle	1312	Not Covered
ClockStop->AcquireStart	1314	Not Covered
ClockStop->Idle	1312	Not Covered
ClockStop->SetupStop	1021	Covered	T2,T3,T9
HoldBit->AcquireStart	1314	Not Covered
HoldBit->ClockLow	907	Covered	T2,T3,T9
HoldBit->ClockLowAck	904	Covered	T2,T3,T9
HoldBit->Idle	1312	Not Covered
HoldDevAck->AcquireStart	1314	Not Covered
HoldDevAck->ClockStop	933	Covered	T2,T3,T9
HoldDevAck->Idle	1312	Not Covered
HoldDevAck->PopFmtFifo	937	Covered	T2,T3,T9
HoldStart->AcquireStart	1314	Not Covered
HoldStart->ClockStart	859	Covered	T2,T3,T9
HoldStart->Idle	1312	Not Covered
HoldStop->AcquireStart	1314	Not Covered
HoldStop->Idle	1041	Covered	T14,T56,T27
HoldStop->PopFmtFifo	1045	Covered	T2,T3,T9
HostClockLowAck->AcquireStart	1314	Not Covered
HostClockLowAck->HostClockPulseAck	980	Covered	T2,T3,T10
HostClockLowAck->Idle	1312	Not Covered
HostClockPulseAck->AcquireStart	1314	Not Covered
HostClockPulseAck->HostHoldBitAck	989	Covered	T2,T3,T10
HostClockPulseAck->Idle	1312	Not Covered
HostHoldBitAck->AcquireStart	1314	Not Covered
HostHoldBitAck->ClockStop	1001	Covered	T2,T3,T10
HostHoldBitAck->Idle	1312	Not Covered
HostHoldBitAck->PopFmtFifo	1005	Covered	T3,T30,T31
HostHoldBitAck->ReadClockLow	1010	Covered	T2,T3,T10
Idle->AcquireStart	1314	Covered	T6,T7,T8
Idle->Active	843	Covered	T2,T3,T9
PopFmtFifo->AcquireStart	1314	Not Covered
PopFmtFifo->Active	1082	Covered	T2,T3,T9
PopFmtFifo->ClockStop	1074	Covered	T14,T56,T27
PopFmtFifo->Idle	1078	Covered	T2,T3,T9
ReadClockLow->AcquireStart	1314	Not Covered
ReadClockLow->Idle	1312	Not Covered
ReadClockLow->ReadClockPulse	946	Covered	T2,T3,T10
ReadClockPulse->AcquireStart	1314	Not Covered
ReadClockPulse->Idle	1312	Not Covered
ReadClockPulse->ReadHoldBit	954	Covered	T2,T3,T10
ReadHoldBit->AcquireStart	1314	Not Covered
ReadHoldBit->HostClockLowAck	966	Covered	T2,T3,T10
ReadHoldBit->Idle	1312	Not Covered
ReadHoldBit->ReadClockLow	970	Covered	T2,T3,T10
SetupStart->AcquireStart	1314	Not Covered
SetupStart->HoldStart	850	Covered	T2,T3,T9
SetupStart->Idle	1312	Not Covered
SetupStop->AcquireStart	1314	Not Covered
SetupStop->HoldStop	1029	Covered	T2,T3,T9
SetupStop->Idle	1312	Not Covered
StretchAcqFull->AcquireByte	1279	Covered	T6,T20,T45
StretchAcqFull->AcquireStart	1314	Covered	T43,T44
StretchAcqFull->Idle	1312	Covered	T43,T44
StretchAddr->AcquireByte	1248	Covered	T6,T20,T45
StretchAddr->AcquireStart	1314	Covered	T43,T44
StretchAddr->Idle	1312	Covered	T43,T44
StretchAddr->StretchTx	1248	Covered	T46,T47,T48
StretchTx->AcquireStart	1314	Covered	T43,T44
StretchTx->Idle	1312	Covered	T43,T44
StretchTx->StretchTxSetup	1262	Covered	T6,T7,T8
StretchTxSetup->AcquireStart	1314	Covered	T43,T44
StretchTxSetup->Idle	1312	Covered	T43,T44
StretchTxSetup->TransmitSetup	1272	Covered	T6,T7,T8
TransmitAck->AcquireStart	1314	Covered	T43,T44
TransmitAck->Idle	1312	Covered	T43,T44
TransmitAck->TransmitAckPulse	1179	Covered	T6,T7,T8
TransmitAckPulse->AcquireStart	1314	Covered	T57,T58,T43
TransmitAckPulse->Idle	1312	Covered	T43,T44
TransmitAckPulse->TransmitWait	1189	Covered	T6,T7,T8
TransmitAckPulse->WaitForStop	1192	Covered	T6,T7,T8
TransmitHold->AcquireStart	1314	Covered	T43,T44
TransmitHold->Idle	1312	Covered	T43,T44
TransmitHold->TransmitAck	1167	Covered	T6,T7,T8
TransmitHold->TransmitSetup	1171	Covered	T6,T7,T8
TransmitPulse->AcquireStart	1314	Covered	T6,T34,T23
TransmitPulse->Idle	1312	Covered	T6,T34,T23
TransmitPulse->TransmitHold	1158	Covered	T6,T7,T8
TransmitSetup->AcquireStart	1314	Covered	T43,T44
TransmitSetup->Idle	1312	Covered	T43,T44
TransmitSetup->TransmitPulse	1153	Covered	T6,T7,T8
TransmitWait->AcquireStart	1314	Covered	T43,T44
TransmitWait->Idle	1312	Covered	T43,T44
TransmitWait->StretchTx	1144	Covered	T6,T7,T8
TransmitWait->TransmitSetup	1146	Covered	T6,T7,T8
WaitForStop->AcquireStart	1314	Covered	T6,T7,T8
WaitForStop->Idle	1312	Covered	T6,T7,T8

---

Branch Coverage for Module : i2c_fsm

	Line No.	Total	Covered	Percent
Branches		258	247	95.74
IF	154	14	13	92.86
IF	180	2	2	100.00
IF	193	5	5	100.00
IF	209	4	4	100.00
IF	222	4	4	100.00
IF	233	3	3	100.00
IF	240	4	4	100.00
IF	253	2	2	100.00
IF	267	5	5	100.00
IF	279	5	4	80.00
IF	301	5	5	100.00
IF	322	5	5	100.00
IF	333	4	4	100.00
IF	410	4	4	100.00
IF	433	3	3	100.00
CASE	475	73	67	91.78
IF	795	3	3	100.00
CASE	838	105	103	98.10
IF	1303	4	3	75.00
IF	1322	2	2	100.00
IF	1331	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	154	if (load_tcount)
-2-:	155	case (tcount_sel)
-3-:	169	if (((stretch_idle_cnt == '0) || target_enable_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	tSetupStart	-	Covered	T2,T3,T9
1	tHoldStart	-	Covered	T2,T3,T9
1	tSetupData	-	Covered	T6,T7,T8
1	tClockStart	-	Covered	T2,T3,T6
1	tClockLow	-	Covered	T2,T3,T9
1	tClockPulse	-	Covered	T2,T3,T9
1	tHoldBit	-	Covered	T2,T3,T9
1	tClockStop	-	Covered	T2,T3,T9
1	tSetupStop	-	Covered	T2,T3,T9
1	tHoldStop	-	Covered	T2,T3,T9
1	tNoDelay	-	Covered	T2,T3,T9
1	default	-	Not Covered
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T2,T3,T9

	LineNo.	Expression
-1-:	180	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	193	if ((!rst_ni))
-2-:	195	if (((stretch_en && scl_d) && (!scl_i)))
-3-:	197	if (((!target_idle_o) && event_host_timeout_o))
-4-:	200	if (((!target_idle_o) && scl_i))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T3,T9
0	0	1	-	Covered	T15,T22,T23
0	0	0	1	Covered	T6,T7,T8
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	209	if ((!rst_ni))
-2-:	211	if (bit_clr)
-3-:	213	if (bit_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T9
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	222	if ((!rst_ni))
-2-:	224	if (read_byte_clr)
-3-:	226	if (shift_data_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T10
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	233	if ((!fmt_flag_read_bytes_i))
-2-:	234	if ((fmt_byte_i == '0))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T24,T25,T26
0	0	Covered	T2,T3,T10

	LineNo.	Expression
-1-:	240	if ((!rst_ni))
-2-:	242	if (byte_clr)
-3-:	244	if (byte_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T10
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	267	if ((!rst_ni))
-2-:	269	if ((trans_started && (!host_enable_i)))
-3-:	271	if (log_start)
-4-:	273	if (log_stop)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T27,T28,T29
0	0	1	-	Covered	T2,T3,T9
0	0	0	1	Covered	T2,T3,T9
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	279	if ((!rst_ni))
-2-:	281	if ((pend_restart && (!host_enable_i)))
-3-:	283	if (req_restart)
-4-:	285	if (log_start)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Covered	T3,T30,T31
0	0	0	1	Covered	T2,T3,T9
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	301	if ((!rst_ni))
-2-:	303	if (start_det)
-3-:	305	if ((scl_i_q && (!scl_i)))
-4-:	308	if ((input_byte_clr || bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T6,T7,T8
0	0	1	1	Covered	T2,T3,T6
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	322	if ((!rst_ni))
-2-:	324	if (input_byte_clr)
-3-:	326	if (((!scl_i_q) && scl_i))
-4-:	327	if ((!bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T6,T7,T8
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T2,T3,T6
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	333	if ((!rst_ni))
-2-:	335	if (((!scl_i_q) && scl_i))
-3-:	336	if (bit_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T2,T3,T6
0	1	0	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	410	if ((!rst_ni))
-2-:	412	if (((!en_sda_interf_det) && (|sda_rise_cnt)))
-3-:	417	if ((en_sda_interf_det && (sda_rise_cnt < sda_rise_latency)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T9
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	433	if ((!rst_ni))
-2-:	435	if ((bit_ack && address_match))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	case (state_q)
-2-:	481	if ((host_enable_i && trans_started))
-3-:	494	if (log_start)
-4-:	510	if (pend_restart)
-5-:	523	if ((scl_i_q && (!scl_i)))
-6-:	524	if ((sda_i_q != sda_i))
-7-:	543	if (((((!scl_i_q) && scl_i) && sda_i) && (!fmt_flag_nak_ok_i)))
-8-:	545	if ((scl_i_q && (!scl_i)))
-9-:	546	if ((sda_i_q != sda_i))
-10-:	565	if ((scl_i_q && (!scl_i)))
-11-:	566	if ((sda_i_q != sda_i))
-12-:	572	if (((bit_index == '0) && (tcount_q == 20'b1)))
-13-:	584	if (fmt_flag_read_continue_i)
-14-:	585	if ((byte_index == 9'b1))
-15-:	591	if (fmt_flag_read_continue_i)
-16-:	592	if ((byte_index == 9'b1))
-17-:	596	if ((scl_i_q && (!scl_i)))
-18-:	597	if ((sda_i_q != sda_i))
-19-:	602	if (fmt_flag_read_continue_i)
-20-:	603	if ((byte_index == 9'b1))
-21-:	639	if (fmt_flag_stop_after_i)
-22-:	672	if ((tcount_q == 20'b1))
-23-:	707	if ((!scl_i))
-24-:	741	if ((tcount_q == 20'b1))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
Idle	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SetupStart	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
SetupStart	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
HoldStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
ClockStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
ClockLow	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T30,T31
ClockLow	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
ClockPulse	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClockPulse	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
ClockPulse	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T30
ClockPulse	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
ClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
ClockPulseAck	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T27,T36
ClockPulseAck	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
ClockPulseAck	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClockPulseAck	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
ClockPulseAck	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
ClockPulseAck	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
ReadClockLow	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
ReadClockPulse	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadClockPulse	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
ReadClockPulse	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
ReadClockPulse	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T30,T31
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T3,T30,T31
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T3,T10
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T30,T31
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T3,T10
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T3,T30,T31
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T2,T3,T10
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	Covered	T2,T3,T10
ClockStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T2,T3,T9
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T2,T3,T9
AcquireStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrRead	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T6,T7,T8
AddrAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T6,T7,T8
TransmitWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
TransmitSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
TransmitPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
TransmitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T6,T7,T8
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T6,T7,T8
WaitForStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T7,T8
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T6,T7,T8
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T20,T45
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
StretchTxSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T20,T45
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	795	if ((start_det || stop_det))
-2-:	798	(start_det) ? 

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	838	case (state_q)
-2-:	841	if (((!host_enable_i) && (!target_enable_i)))
-3-:	842	if (host_enable_i)
-4-:	843	if (fmt_fifo_rvalid_i)
-5-:	849	if ((tcount_q == 20'b1))
-6-:	858	if ((tcount_q == 20'b1))
-7-:	866	if ((tcount_q == 20'b1))
-8-:	875	if ((tcount_q == 20'b1))
-9-:	877	if (pend_restart)
-10-:	890	if ((tcount_q == 20'b1))
-11-:	899	if ((tcount_q == 20'b1))
-12-:	903	if ((bit_index == '0))
-13-:	915	if ((tcount_q == 20'b1))
-14-:	923	if ((tcount_q == 20'b1))
-15-:	931	if ((tcount_q == 20'b1))
-16-:	932	if (fmt_flag_stop_after_i)
-17-:	945	if ((tcount_q == 20'b1))
-18-:	953	if ((tcount_q == 20'b1))
-19-:	962	if ((tcount_q == 20'b1))
-20-:	965	if ((bit_index == '0))
-21-:	979	if ((tcount_q == 20'b1))
-22-:	988	if ((tcount_q == 20'b1))
-23-:	997	if ((tcount_q == 20'b1))
-24-:	999	if ((byte_index == 9'b1))
-25-:	1000	if (fmt_flag_stop_after_i)
-26-:	1020	if ((tcount_q == 20'b1))
-27-:	1028	if ((tcount_q == 20'b1))
-28-:	1038	if ((tcount_q == 20'b1))
-29-:	1040	if ((!host_enable_i))
-30-:	1054	if (fmt_flag_read_bytes_i)
-31-:	1059	if ((fmt_flag_start_before_i && (!trans_started)))
-32-:	1073	if ((!host_enable_i))
-33-:	1077	if ((fmt_fifo_depth_i == 7'b1))
-34-:	1090	if ((scl_i_q && (!scl_i)))
-35-:	1099	if ((bit_ack && address_match))
-36-:	1103	if ((bit_ack && (!address_match)))
-37-:	1110	if (((tcount_q == 20'b1) && (!scl_i)))
-38-:	1116	if (scl_i)
-39-:	1120	if ((!scl_i))
-40-:	1128	if ((tcount_q == 20'b1))
-41-:	1132	if (stretch_addr)
-42-:	1134	if (rw_bit_q)
-43-:	1136	if ((!rw_bit_q))
-44-:	1143	if (stretch_tx)
-45-:	1153	if (scl_i)
-46-:	1157	if ((!scl_i))
-47-:	1165	if ((tcount_q == 20'b1))
-48-:	1166	if (bit_ack)
-49-:	1178	if (scl_i)
-50-:	1186	if ((!scl_i))
-51-:	1188	if (host_ack)
-52-:	1206	if (bit_ack)
-53-:	1215	if (((tcount_q == 20'b1) && (!scl_i)))
-54-:	1221	if (scl_i)
-55-:	1225	if ((!scl_i))
-56-:	1233	if ((tcount_q == 20'b1))
-57-:	1236	(acq_fifo_wready) ? 
-58-:	1242	if ((!stretch_addr))
-59-:	1248	(rw_bit_q) ? 
-60-:	1255	if ((!stretch_tx))
-61-:	1271	if ((tcount_q == 20'b1))
-62-:	1279	if (acq_fifo_wready)

Branches:

Branch	Status	Tests
(1.Idle )->(2)	Covered	T1,T2,T3
(1.Idle )->(!2)->(3)->(4)	Covered	T2,T3,T9
(1.Idle )->(!2)->(3)->(!4)	Covered	T1,T2,T3
(1.Idle )->(!2)->(!3)	Covered	T6,T7,T8
(1.SetupStart )->(5)	Covered	T2,T3,T9
(1.SetupStart )->(!5)	Covered	T2,T3,T9
(1.HoldStart )->(6)	Covered	T2,T3,T9
(1.HoldStart )->(!6)	Covered	T2,T3,T9
(1.ClockStart )->(7)	Covered	T2,T3,T9
(1.ClockStart )->(!7)	Covered	T2,T9,T21
(1.ClockLow )->(8)->(9)	Covered	T3,T30,T31
(1.ClockLow )->(8)->(!9)	Covered	T2,T3,T9
(1.ClockLow )->(!8)	Covered	T2,T3,T9
(1.ClockPulse )->(10)	Covered	T2,T3,T9
(1.ClockPulse )->(!10)	Covered	T2,T3,T9
(1.HoldBit )->(11)->(12)	Covered	T2,T3,T9
(1.HoldBit )->(11)->(!12)	Covered	T2,T3,T9
(1.HoldBit )->(!11)	Covered	T2,T3,T9
(1.ClockLowAck )->(13)	Covered	T2,T3,T9
(1.ClockLowAck )->(!13)	Covered	T2,T3,T9
(1.ClockPulseAck )->(14)	Covered	T2,T3,T9
(1.ClockPulseAck )->(!14)	Covered	T2,T3,T9
(1.HoldDevAck )->(15)->(16)	Covered	T2,T3,T9
(1.HoldDevAck )->(15)->(!16)	Covered	T2,T3,T9
(1.HoldDevAck )->(!15)	Covered	T2,T3,T9
(1.ReadClockLow )->(17)	Covered	T2,T3,T10
(1.ReadClockLow )->(!17)	Covered	T2,T3,T10
(1.ReadClockPulse )->(18)	Covered	T2,T3,T10
(1.ReadClockPulse )->(!18)	Covered	T2,T3,T10
(1.ReadHoldBit )->(19)->(20)	Covered	T2,T3,T10
(1.ReadHoldBit )->(19)->(!20)	Covered	T2,T3,T10
(1.ReadHoldBit )->(!19)	Covered	T2,T3,T10
(1.HostClockLowAck )->(21)	Covered	T2,T3,T10
(1.HostClockLowAck )->(!21)	Covered	T2,T3,T10
(1.HostClockPulseAck )->(22)	Covered	T2,T3,T10
(1.HostClockPulseAck )->(!22)	Covered	T2,T3,T10
(1.HostHoldBitAck )->(23)->(24)->(25)	Covered	T2,T3,T10
(1.HostHoldBitAck )->(23)->(24)->(!25)	Covered	T3,T30,T31
(1.HostHoldBitAck )->(23)->(!24)	Covered	T2,T3,T10
(1.HostHoldBitAck )->(!23)	Covered	T2,T3,T10
(1.ClockStop )->(26)	Covered	T2,T3,T9
(1.ClockStop )->(!26)	Covered	T2,T3,T9
(1.SetupStop )->(27)	Covered	T2,T3,T9
(1.SetupStop )->(!27)	Covered	T2,T3,T9
(1.HoldStop )->(28)->(29)	Covered	T14,T56,T27
(1.HoldStop )->(28)->(!29)	Covered	T2,T3,T9
(1.HoldStop )->(!28)	Covered	T2,T3,T9
(1.Active )->(30)	Covered	T2,T3,T10
(1.Active )->(!30)->(31)	Covered	T2,T3,T9
(1.Active )->(!30)->(!31)	Covered	T2,T3,T9
(1.PopFmtFifo )->(32)	Covered	T14,T56,T27
(1.PopFmtFifo )->(!32)->(33)	Covered	T2,T3,T9
(1.PopFmtFifo )->(!32)->(!33)	Covered	T2,T3,T9
(1.AcquireStart )->(34)	Covered	T6,T7,T8
(1.AcquireStart )->(!34)	Covered	T6,T7,T8
(1.AddrRead )->(35)	Covered	T6,T7,T8
(1.AddrRead )->(!35)->(36)	Covered	T7,T32,T33
(1.AddrRead )->(!35)->(!36)	Covered	T6,T7,T8
(1.AddrAckWait )->(37)	Covered	T6,T7,T8
(1.AddrAckWait )->(!37)	Covered	T6,T7,T8
(1.AddrAckSetup )->(38)	Covered	T6,T7,T8
(1.AddrAckSetup )->(!38)	Covered	T6,T7,T8
(1.AddrAckPulse )->(39)	Covered	T6,T7,T8
(1.AddrAckPulse )->(!39)	Covered	T6,T7,T8
(1.AddrAckHold )->(40)->(41)	Covered	T6,T20,T45
(1.AddrAckHold )->(40)->(!41)->(42)	Covered	T6,T7,T8
(1.AddrAckHold )->(40)->(!41)->(!42)->(43)	Covered	T6,T7,T8
(1.AddrAckHold )->(40)->(!41)->(!42)->(!43)	Not Covered
(1.AddrAckHold )->(!40)	Covered	T6,T7,T8
(1.TransmitWait )->(44)	Covered	T6,T7,T8
(1.TransmitWait )->(!44)	Covered	T6,T7,T8
(1.TransmitSetup )->(45)	Covered	T6,T7,T8
(1.TransmitSetup )->(!45)	Covered	T6,T7,T8
(1.TransmitPulse )->(46)	Covered	T6,T7,T8
(1.TransmitPulse )->(!46)	Covered	T6,T7,T8
(1.TransmitHold )->(47)->(48)	Covered	T6,T7,T8
(1.TransmitHold )->(47)->(!48)	Covered	T6,T7,T8
(1.TransmitHold )->(!47)	Covered	T6,T7,T8
(1.TransmitAck )->(49)	Covered	T6,T7,T8
(1.TransmitAck )->(!49)	Covered	T6,T7,T8
(1.TransmitAckPulse )->(50)->(51)	Covered	T6,T7,T8
(1.TransmitAckPulse )->(50)->(!51)	Covered	T6,T7,T8
(1.TransmitAckPulse )->(!50)	Covered	T6,T7,T8
(1.WaitForStop )	Covered	T6,T7,T8
(1.AcquireByte )->(52)	Covered	T6,T7,T8
(1.AcquireByte )->(!52)	Covered	T6,T7,T8
(1.AcquireAckWait )->(53)	Covered	T6,T7,T8
(1.AcquireAckWait )->(!53)	Covered	T6,T7,T8
(1.AcquireAckSetup )->(54)	Covered	T6,T7,T8
(1.AcquireAckSetup )->(!54)	Covered	T6,T7,T8
(1.AcquireAckPulse )->(55)	Covered	T6,T7,T8
(1.AcquireAckPulse )->(!55)	Covered	T6,T7,T8
(1.AcquireAckHold )->(56)->(57)	Covered	T6,T7,T8
(1.AcquireAckHold )->(56)->(!57)	Covered	T6,T20,T45
(1.AcquireAckHold )->(!56)	Covered	T6,T7,T8
(1.StretchAddr )->(58)->(59)	Covered	T46,T47,T48
(1.StretchAddr )->(58)->(!59)	Covered	T6,T20,T45
(1.StretchAddr )->(!58)	Covered	T6,T20,T45
(1.StretchTx )->(60)	Covered	T6,T7,T8
(1.StretchTx )->(!60)	Covered	T6,T7,T8
(1.StretchTxSetup )->(61)	Covered	T6,T7,T8
(1.StretchTxSetup )->(!61)	Covered	T6,T7,T8
(1.StretchAcqFull )->(62)	Covered	T6,T20,T45
(1.StretchAcqFull )->(!62)	Covered	T6,T20,T45
(1.default)	Not Covered

	LineNo.	Expression
-1-:	1303	if (((!target_idle) && (!target_enable_i)))
-2-:	1313	if (start_det)
-3-:	1315	if (stop_det)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T6,T7,T8
0	0	1	Covered	T6,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1322	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1331	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AcqDepthRdCheck_A	519564966	4049790	0	0
SclInputGlitch_A	498147910	11028579	0	0
SclOutputGlitch_A	519564966	5659414	0	0
SclSdaChangeNotSimultaneous_A	519564966	519382236	0	0

AcqDepthRdCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519564966	4049790	0	0
T6	172101	4334	0	0
T7	104575	52	0	0
T8	68004	442	0	0
T9	21395	0	0	0
T10	47643	0	0	0
T11	467049	0	0	0
T15	0	36042	0	0
T18	248389	8573	0	0
T19	0	23180	0	0
T20	289854	0	0	0
T21	25418	0	0	0
T22	0	706	0	0
T45	558402	0	0	0
T59	0	276	0	0
T60	0	569	0	0
T61	0	213	0	0

SclInputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498147910	11028579	0	0
T1	1018	2	0	0
T2	98933	3382	0	0
T3	324859	20702	0	0
T6	172101	23375	0	0
T7	104575	3229	0	0
T8	68004	2764	0	0
T9	21395	802	0	0
T10	47643	1722	0	0
T20	289854	3332	0	0
T21	25418	910	0	0

SclOutputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519564966	5659414	0	0
T2	98933	3382	0	0
T3	324859	20702	0	0
T6	172101	701	0	0
T7	104575	7	0	0
T8	68004	19	0	0
T9	21395	802	0	0
T10	47643	1722	0	0
T18	248389	68	0	0
T20	289854	310	0	0
T21	25418	910	0	0

SclSdaChangeNotSimultaneous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519564966	519382236	0	0
T1	1018	932	0	0
T2	98933	98877	0	0
T3	324859	324795	0	0
T6	172101	172085	0	0
T7	104575	104488	0	0
T8	68004	67923	0	0
T9	21395	21296	0	0
T10	47643	47572	0	0
T20	289854	289846	0	0
T21	25418	25345	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_fsm

	Line No.	Total	Covered	Percent
TOTAL		554	546	98.56
ALWAYS	153	17	17	100.00
CONT_ASSIGN	177	1	1	100.00
ALWAYS	180	3	3	100.00
ALWAYS	193	9	9	100.00
ALWAYS	209	7	7	100.00
ALWAYS	222	6	6	100.00
ALWAYS	233	5	5	100.00
ALWAYS	240	7	7	100.00
ALWAYS	253	5	5	100.00
ALWAYS	267	8	8	100.00
ALWAYS	279	8	7	87.50
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
ALWAYS	301	9	9	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	318	1	1	100.00
ALWAYS	322	7	7	100.00
ALWAYS	333	5	5	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	347	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
ALWAYS	410	6	6	100.00
CONT_ASSIGN	428	1	1	100.00
ALWAYS	433	4	4	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	458	180	174	96.67
CONT_ASSIGN	804	1	1	100.00
CONT_ASSIGN	813	1	1	100.00
CONT_ASSIGN	818	1	1	100.00
ALWAYS	822	239	238	99.58
ALWAYS	1322	3	3	100.00
ALWAYS	1331	5	5	100.00
CONT_ASSIGN	1340	1	1	100.00
CONT_ASSIGN	1341	1	1	100.00
CONT_ASSIGN	1344	1	1	100.00
CONT_ASSIGN	1347	1	1	100.00
CONT_ASSIGN	1351	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
169	1	1
170	1	1
172	1	1
177	1	1
180	1	1
181	1	1
183	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
199	1	1
200	1	1
201	1	1
203	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
216	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
			MISSING_ELSE
233	2	2
234	2	2
235	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
247	1	1
253	1	1
254	1	1
255	1	1
257	1	1
258	1	1
267	1	1
268	1	1
269	1	1
270	1	1
271	1	1
272	1	1
273	1	1
274	1	1
			MISSING_ELSE
279	1	1
280	1	1
281	1	1
282	0	1
283	1	1
284	1	1
285	1	1
286	1	1
			MISSING_ELSE
291	1	1
294	1	1
297	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
308	2	2
309	1	1
311	1	1
316	1	1
317	1	1
318	1	1
322	1	1
323	1	1
324	1	1
325	1	1
326	1	1
327	2	2
			MISSING_ELSE
			MISSING_ELSE
333	1	1
334	1	1
335	1	1
336	2	2
			MISSING_ELSE
			MISSING_ELSE
346	1	1
347	1	1
405	1	1
410	1	1
411	1	1
412	1	1
416	1	1
417	1	1
418	1	1
			MISSING_ELSE
428	1	1
433	1	1
434	1	1
435	1	1
436	1	1
			MISSING_ELSE
450	1	1
454	1	1
458	1	1
459	1	1
460	1	1
461	1	1
462	1	1
463	1	1
464	1	1
465	1	1
466	1	1
467	1	1
468	1	1
469	1	1
470	1	1
471	1	1
472	1	1
473	1	1
474	1	1
475	1	1
480	1	1
481	1	1
482	0	1
483	0	1
485	1	1
486	1	1
491	1	1
492	1	1
493	1	1
494	2	2
			MISSING_ELSE
498	1	1
499	1	1
500	1	1
504	1	1
505	1	1
506	1	1
509	1	1
510	1	1
511	1	1
513	1	1
515	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	2
			MISSING_ELSE
524	2	2
			MISSING_ELSE
528	1	1
529	1	1
530	1	1
534	1	1
535	1	1
536	1	1
540	1	1
541	1	1
542	1	1
543	2	2
			MISSING_ELSE
544	1	1
545	1	2
			MISSING_ELSE
546	2	2
			MISSING_ELSE
550	1	1
551	1	1
552	1	1
556	1	1
557	1	1
558	1	1
562	1	1
563	1	1
564	1	1
565	1	2
			MISSING_ELSE
566	2	2
			MISSING_ELSE
570	1	1
571	1	1
572	1	1
573	1	1
574	1	1
			MISSING_ELSE
579	1	1
580	1	1
584	2	2
585	2	2
586	1	1
590	1	1
591	2	2
592	2	2
593	1	1
594	1	1
595	1	1
596	1	2
			MISSING_ELSE
597	2	2
			MISSING_ELSE
601	1	1
602	2	2
603	2	2
604	1	1
605	1	1
609	1	1
610	1	1
611	1	1
615	1	1
616	1	1
617	1	1
621	1	1
622	1	1
623	1	1
624	1	1
628	1	1
634	1	1
638	1	1
639	2	2
640	1	1
641	1	1
645	1	1
649	1	1
650	1	1
654	1	1
658	1	1
659	1	1
663	1	1
664	1	1
668	1	1
669	1	1
672	1	1
674	1	1
675	1	1
			MISSING_ELSE
680	1	1
684	1	1
685	1	1
689	1	1
692	1	1
696	1	1
699	1	1
703	1	1
706	1	1
707	1	1
709	1	1
			MISSING_ELSE
714	1	1
715	1	1
716	1	1
720	1	1
724	1	1
728	1	1
729	1	1
733	1	1
734	1	1
738	1	1
739	1	1
741	1	1
742	1	1
743	1	1
			MISSING_ELSE
749	1	1
750	1	1
752	1	1
753	1	1
757	1	1
758	1	1
762	1	1
763	1	1
764	1	1
768	1	1
769	1	1
772	1	1
773	1	1
795	1	1
797	1	1
798	1	1
800	1	1
			MISSING_ELSE
804	1	1
813	1	1
818	1	1
822	1	1
823	1	1
824	1	1
825	1	1
826	1	1
827	1	1
828	1	1
829	1	1
830	1	1
831	1	1
832	1	1
833	1	1
834	1	1
835	1	1
836	1	1
838	1	1
841	2	2
842	1	1
843	2	2
			MISSING_ELSE
			MISSING_ELSE
849	1	1
850	1	1
851	1	1
852	1	1
853	1	1
			MISSING_ELSE
858	1	1
859	1	1
860	1	1
861	1	1
			MISSING_ELSE
866	1	1
867	1	1
868	1	1
869	1	1
			MISSING_ELSE
874	1	1
875	1	1
876	1	1
877	1	1
878	1	1
879	1	1
881	1	1
882	1	1
			MISSING_ELSE
889	1	1
890	1	1
891	1	1
892	1	1
893	1	1
			MISSING_ELSE
898	1	1
899	1	1
900	1	1
901	1	1
902	1	1
903	1	1
904	1	1
905	1	1
907	1	1
908	1	1
			MISSING_ELSE
915	1	1
916	1	1
917	1	1
918	1	1
			MISSING_ELSE
923	1	1
924	1	1
925	1	1
926	1	1
			MISSING_ELSE
931	1	1
932	1	1
933	1	1
934	1	1
935	1	1
937	1	1
938	1	1
939	1	1
			MISSING_ELSE
945	1	1
946	1	1
947	1	1
948	1	1
			MISSING_ELSE
953	1	1
954	1	1
955	1	1
956	1	1
957	1	1
			MISSING_ELSE
962	1	1
963	1	1
964	1	1
965	1	1
966	1	1
967	1	1
968	1	1
970	1	1
971	1	1
			MISSING_ELSE
978	1	1
979	1	1
980	1	1
981	1	1
982	1	1
			MISSING_ELSE
987	1	1
988	1	1
989	1	1
990	1	1
991	1	1
			MISSING_ELSE
996	1	1
997	1	1
998	1	1
999	1	1
1000	1	1
1001	1	1
1002	1	1
1003	1	1
1005	1	1
1006	1	1
1007	1	1
1010	1	1
1011	1	1
1012	1	1
1013	1	1
			MISSING_ELSE
1020	1	1
1021	1	1
1022	1	1
1023	1	1
			MISSING_ELSE
1028	1	1
1029	1	1
1030	1	1
1031	1	1
1032	1	1
			MISSING_ELSE
1037	1	1
1038	1	1
1039	1	1
1040	1	1
1041	1	1
1042	1	1
1043	1	1
1045	1	1
1046	1	1
1047	1	1
			MISSING_ELSE
1054	1	1
1055	1	1
1056	1	1
1057	1	1
1058	1	1
1059	1	1
1060	1	1
1061	1	1
1062	1	1
1064	1	1
1065	1	1
1066	1	1
1067	1	1
1073	1	1
1074	1	1
1075	1	1
1076	1	1
1077	1	1
1078	1	1
1079	1	1
1080	1	1
1082	1	1
1083	1	1
1084	1	1
1090	1	1
1092	1	1
1093	1	1
			MISSING_ELSE
1099	1	1
1100	1	1
1101	1	1
1102	1	1
1103	1	1
1104	1	1
			MISSING_ELSE
1110	1	1
1111	1	1
			MISSING_ELSE
1116	2	2
			MISSING_ELSE
1120	1	1
1121	1	1
1122	1	1
1123	1	1
			MISSING_ELSE
1128	1	1
1132	1	1
1133	1	1
1134	1	1
1135	1	1
1136	1	1
1137	1	1
			==> MISSING_ELSE
			MISSING_ELSE
1143	1	1
1144	1	1
1146	1	1
1147	1	1
1148	1	1
1153	2	2
			MISSING_ELSE
1157	1	1
1158	1	1
1159	1	1
1160	1	1
			MISSING_ELSE
1165	1	1
1166	1	1
1167	1	1
1169	1	1
1170	1	1
1171	1	1
			MISSING_ELSE
1178	1	1
1179	1	1
			MISSING_ELSE
1186	1	1
1188	1	1
1189	1	1
1192	1	1
			MISSING_ELSE
1201	1	1
1206	1	1
1207	1	1
1208	1	1
1209	1	1
			MISSING_ELSE
1215	1	1
1216	1	1
			MISSING_ELSE
1221	2	2
			MISSING_ELSE
1225	1	1
1226	1	1
1227	1	1
1228	1	1
			MISSING_ELSE
1233	1	1
1236	1	1
			MISSING_ELSE
1242	1	1
1248	1	1
			MISSING_ELSE
1254	1	1
1255	1	1
1262	1	1
1263	1	1
1264	1	1
1267	1	1
			MISSING_ELSE
1271	1	1
1272	1	1
			MISSING_ELSE
1279	2	2
			MISSING_ELSE
1303	1	1
1312	0	1
1313	1	1
1314	1	1
1315	1	1
1316	1	1
			MISSING_ELSE
1322	1	1
1323	1	1
1325	1	1
1331	1	1
1332	1	1
1333	1	1
1335	1	1
1336	1	1
1340	1	1
1341	1	1
1344	1	1
1347	1	1
1351	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_fsm

	Total	Covered	Percent
Conditions	242	229	94.63
Logical	242	229	94.63
Non-Logical	0	0
Event	0	0

 LINE       169
 EXPRESSION ((stretch_idle_cnt == '0) || target_enable_i)
             ------------1-----------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T9
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3

 LINE       169
 SUB-EXPRESSION (stretch_idle_cnt == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (stretch_en && scl_d && ((!scl_i)))
             -----1----    --2--    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T2,T3,T9
1	1	1	Covered	T2,T3,T9

 LINE       197
 EXPRESSION (((!target_idle_o)) && event_host_timeout_o)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T8
1	1	Covered	T15,T22,T23

 LINE       200
 EXPRESSION (((!target_idle_o)) && scl_i)
             ---------1--------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       234
 EXPRESSION (fmt_byte_i == '0)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T24,T25,T26

 LINE       269
 EXPRESSION (trans_started && ((!host_enable_i)))
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T27,T28,T29

 LINE       281
 EXPRESSION (pend_restart && ((!host_enable_i)))
             ------1-----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T30,T31
1	1	Not Covered

 LINE       291
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i)))))
             -------1-------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       291
 SUB-EXPRESSION ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i))))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       291
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       291
 SUB-EXPRESSION (sda_i_q && ((!sda_i)))
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       294
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i)))
             -------1-------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       294
 SUB-EXPRESSION ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       294
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       294
 SUB-EXPRESSION (((!sda_i_q)) && sda_i)
                 ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       297
 EXPRESSION (bit_idx == 4'd8)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       305
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       308
 EXPRESSION (input_byte_clr || bit_ack)
             -------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T6,T7,T8

 LINE       316
 EXPRESSION ((input_byte[7:1] & target_mask0_i) == target_address0_i)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       317
 EXPRESSION ((input_byte[7:1] & target_mask1_i) == target_address1_i)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       318
 EXPRESSION (address0_match || address1_match)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8

 LINE       326
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       412
 EXPRESSION (((!en_sda_interf_det)) && ((|sda_rise_cnt)))
             -----------1----------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T9

 LINE       417
 EXPRESSION (en_sda_interf_det && (sda_rise_cnt < sda_rise_latency))
             --------1--------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T2,T3,T9

 LINE       428
 EXPRESSION ((host_idle_o & host_enable_i & ((!sda_i))) | ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i))))
             ---------------------1--------------------   ----------------------------2----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T2,T3

 LINE       428
 SUB-EXPRESSION (host_idle_o & host_enable_i & ((!sda_i)))
                 -----1-----   ------2------   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T9
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       428
 SUB-EXPRESSION ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i)))
                 -----------------1----------------   --2--   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T9
1	1	0	Covered	T2,T3,T9
1	1	1	Covered	T2,T3,T9

 LINE       428
 SUB-EXPRESSION (sda_rise_cnt == sda_rise_latency)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T9

 LINE       435
 EXPRESSION (bit_ack && address_match)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T2,T3,T6

 LINE       454
 EXPRESSION (((!target_idle)) & rw_bit_q & stop_det & ((!expect_stop)))
             --------1-------   ----2---   ----3---   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T7,T32,T33
1	0	1	1	Covered	T6,T7,T8
1	1	0	1	Covered	T6,T7,T8
1	1	1	0	Covered	T6,T7,T8
1	1	1	1	Covered	T6,T34,T23

 LINE       481
 EXPRESSION (host_enable_i && trans_started)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       523
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T2,T3,T9
1	1	Not Covered

 LINE       524
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T30

 LINE       543
 EXPRESSION (((!scl_i_q)) && scl_i && sda_i && ((!fmt_flag_nak_ok_i)))
             ------1-----    --2--    --3--    -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T35,T27,T36
1	0	1	1	Covered	T2,T3,T9
1	1	0	1	Covered	T2,T3,T9
1	1	1	0	Covered	T37,T38,T39
1	1	1	1	Covered	T35,T27,T36

 LINE       545
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T2,T3,T9
1	1	Not Covered

 LINE       546
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       565
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
1	1	Not Covered

 LINE       566
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       572
 EXPRESSION ((bit_index == '0) && (tcount_q == 20'b1))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
1	1	Covered	T2,T3,T10

 LINE       572
 SUB-EXPRESSION (bit_index == '0)
                --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       572
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       585
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       592
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       596
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
1	1	Not Covered

 LINE       597
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T3,T30,T31

 LINE       603
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       634
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T42
1	0	Covered	T3,T30,T31
1	1	Covered	T2,T3,T9

 LINE       672
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       741
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       795
 EXPRESSION (start_det || stop_det)
             ----1----    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8

 LINE       798
 EXPRESSION (start_det ? ({AcqRestart, input_byte}) : ({AcqStop, input_byte}))
             ----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       813
 EXPRESSION (((~tx_fifo_rvalid_i)) | (acq_fifo_depth_i > 7'(1'b1)))
             ----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3

 LINE       841
 EXPRESSION (((!host_enable_i)) && ((!target_enable_i)))
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T3

 LINE       849
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       858
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       866
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T9,T21
1	Covered	T2,T3,T9

 LINE       875
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       890
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       899
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       903
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       915
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       923
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       931
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       945
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       953
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       962
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       965
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       979
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       988
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       997
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       999
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       1020
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       1028
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       1038
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       1059
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T42
1	0	Covered	T3,T30,T31
1	1	Covered	T2,T3,T9

 LINE       1077
 EXPRESSION (fmt_fifo_depth_i == 7'b1)
            -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       1090
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T43,T44
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       1099
 EXPRESSION (bit_ack && address_match)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T7,T32,T33
1	1	Covered	T6,T7,T8

 LINE       1103
 EXPRESSION (bit_ack && ((!address_match)))
             ---1---    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T7,T32,T33

 LINE       1110
 EXPRESSION ((tcount_q == 20'b1) && ((!scl_i)))
             ---------1---------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T6,T7,T8

 LINE       1110
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       1128
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       1165
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       1215
 EXPRESSION ((tcount_q == 20'b1) && ((!scl_i)))
             ---------1---------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T6,T7,T8

 LINE       1215
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       1233
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       1236
 EXPRESSION (acq_fifo_wready ? AcquireByte : StretchAcqFull)
             -------1-------

-1-	Status	Tests
0	Covered	T6,T20,T45
1	Covered	T6,T7,T8

 LINE       1248
 EXPRESSION (rw_bit_q ? StretchTx : AcquireByte)
             ----1---

-1-	Status	Tests
0	Covered	T6,T20,T45
1	Covered	T46,T47,T48

 LINE       1271
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       1303
 EXPRESSION (((!target_idle)) && ((!target_enable_i)))
             --------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Not Covered

 LINE       1344
 EXPRESSION (((!target_idle_o)) & (stretch_idle_cnt > host_timeout_i))
             ---------1--------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T6,T7,T8
1	1	Covered	T15,T22,T23

 LINE       1347
 EXPRESSION (stretch_en && (stretch_idle_cnt[30:0] > stretch_timeout_i) && timeout_enable_i)
             -----1----    ----------------------2---------------------    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T7,T8
1	0	1	Covered	T2,T3,T9
1	1	0	Covered	T3,T9,T21
1	1	1	Covered	T2,T3,T9

---

FSM Coverage for Instance : tb.dut.i2c_core.u_i2c_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	43	43	100.00	(Not included in score)
Transitions	115	107	93.04
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AcquireAckHold	1226	Covered	T6,T7,T8
AcquireAckPulse	1221	Covered	T6,T7,T8
AcquireAckSetup	1216	Covered	T6,T7,T8
AcquireAckWait	1207	Covered	T6,T7,T8
AcquireByte	1137	Covered	T6,T7,T8
AcquireStart	1314	Covered	T6,T7,T8
Active	843	Covered	T2,T3,T9
AddrAckHold	1121	Covered	T6,T7,T8
AddrAckPulse	1116	Covered	T6,T7,T8
AddrAckSetup	1111	Covered	T6,T7,T8
AddrAckWait	1100	Covered	T6,T7,T8
AddrRead	1092	Covered	T6,T7,T8
ClockLow	867	Covered	T2,T3,T9
ClockLowAck	904	Covered	T2,T3,T9
ClockPulse	881	Covered	T2,T3,T9
ClockPulseAck	916	Covered	T2,T3,T9
ClockStart	859	Covered	T2,T3,T9
ClockStop	933	Covered	T2,T3,T9
HoldBit	891	Covered	T2,T3,T9
HoldDevAck	924	Covered	T2,T3,T9
HoldStart	850	Covered	T2,T3,T9
HoldStop	1029	Covered	T2,T3,T9
HostClockLowAck	966	Covered	T2,T3,T10
HostClockPulseAck	980	Covered	T2,T3,T10
HostHoldBitAck	989	Covered	T2,T3,T10
Idle	841	Covered	T1,T2,T3
PopFmtFifo	937	Covered	T2,T3,T9
ReadClockLow	970	Covered	T2,T3,T10
ReadClockPulse	946	Covered	T2,T3,T10
ReadHoldBit	954	Covered	T2,T3,T10
SetupStart	878	Covered	T2,T3,T9
SetupStop	1021	Covered	T2,T3,T9
StretchAcqFull	1236	Covered	T6,T20,T45
StretchAddr	1133	Covered	T6,T20,T45
StretchTx	1144	Covered	T6,T7,T8
StretchTxSetup	1262	Covered	T6,T7,T8
TransmitAck	1167	Covered	T6,T7,T8
TransmitAckPulse	1179	Covered	T6,T7,T8
TransmitHold	1158	Covered	T6,T7,T8
TransmitPulse	1153	Covered	T6,T7,T8
TransmitSetup	1146	Covered	T6,T7,T8
TransmitWait	1135	Covered	T6,T7,T8
WaitForStop	1192	Covered	T6,T7,T8

transitions	Line No.	Covered	Tests
AcquireAckHold->AcquireByte	1236	Covered	T6,T7,T8
AcquireAckHold->AcquireStart	1314	Covered	T43,T44
AcquireAckHold->Idle	1312	Covered	T43,T44
AcquireAckHold->StretchAcqFull	1236	Covered	T6,T20,T45
AcquireAckPulse->AcquireAckHold	1226	Covered	T6,T7,T8
AcquireAckPulse->AcquireStart	1314	Covered	T43,T44
AcquireAckPulse->Idle	1312	Covered	T43,T44
AcquireAckSetup->AcquireAckPulse	1221	Covered	T6,T7,T8
AcquireAckSetup->AcquireStart	1314	Covered	T43,T44
AcquireAckSetup->Idle	1312	Covered	T43,T44
AcquireAckWait->AcquireAckSetup	1216	Covered	T6,T7,T8
AcquireAckWait->AcquireStart	1314	Covered	T43,T44
AcquireAckWait->Idle	1312	Covered	T43,T44
AcquireByte->AcquireAckWait	1207	Covered	T6,T7,T8
AcquireByte->AcquireStart	1314	Covered	T6,T7,T8
AcquireByte->Idle	1312	Covered	T6,T7,T8
AcquireStart->AddrRead	1092	Covered	T6,T7,T8
AcquireStart->Idle	1312	Covered	T43,T44
Active->AcquireStart	1314	Excluded
Active->ClockLow	1064	Covered	T2,T3,T9
Active->Idle	1312	Excluded
Active->ReadClockLow	1056	Covered	T2,T3,T10
Active->SetupStart	1060	Covered	T2,T3,T9
AddrAckHold->AcquireByte	1137	Covered	T6,T7,T8
AddrAckHold->AcquireStart	1314	Covered	T43,T44
AddrAckHold->Idle	1312	Covered	T43,T44
AddrAckHold->StretchAddr	1133	Covered	T6,T20,T45
AddrAckHold->TransmitWait	1135	Covered	T6,T7,T8
AddrAckPulse->AcquireStart	1314	Covered	T43,T44
AddrAckPulse->AddrAckHold	1121	Covered	T6,T7,T8
AddrAckPulse->Idle	1312	Covered	T43,T44
AddrAckSetup->AcquireStart	1314	Covered	T43,T44
AddrAckSetup->AddrAckPulse	1116	Covered	T6,T7,T8
AddrAckSetup->Idle	1312	Covered	T43,T44
AddrAckWait->AcquireStart	1314	Covered	T43,T44
AddrAckWait->AddrAckSetup	1111	Covered	T6,T7,T8
AddrAckWait->Idle	1312	Covered	T43,T44
AddrRead->AcquireStart	1314	Covered	T49,T50,T51
AddrRead->AddrAckWait	1100	Covered	T6,T7,T8
AddrRead->Idle	1104	Covered	T7,T52,T32
ClockLow->AcquireStart	1314	Excluded
ClockLow->ClockPulse	881	Covered	T2,T3,T9
ClockLow->Idle	1312	Covered	T35,T53,T54
ClockLow->SetupStart	878	Covered	T3,T30,T31
ClockLowAck->AcquireStart	1314	Excluded
ClockLowAck->ClockPulseAck	916	Covered	T2,T3,T9
ClockLowAck->Idle	1312	Not Covered
ClockPulse->AcquireStart	1314	Excluded
ClockPulse->HoldBit	891	Covered	T2,T3,T9
ClockPulse->Idle	1312	Covered	T35,T53,T54
ClockPulseAck->AcquireStart	1314	Excluded
ClockPulseAck->HoldDevAck	924	Covered	T2,T3,T9
ClockPulseAck->Idle	1312	Covered	T35,T53,T55
ClockStart->AcquireStart	1314	Excluded
ClockStart->ClockLow	867	Covered	T2,T3,T9
ClockStart->Idle	1312	Excluded
ClockStop->AcquireStart	1314	Excluded
ClockStop->Idle	1312	Excluded
ClockStop->SetupStop	1021	Covered	T2,T3,T9
HoldBit->AcquireStart	1314	Excluded
HoldBit->ClockLow	907	Covered	T2,T3,T9
HoldBit->ClockLowAck	904	Covered	T2,T3,T9
HoldBit->Idle	1312	Not Covered
HoldDevAck->AcquireStart	1314	Excluded
HoldDevAck->ClockStop	933	Covered	T2,T3,T9
HoldDevAck->Idle	1312	Not Covered
HoldDevAck->PopFmtFifo	937	Covered	T2,T3,T9
HoldStart->AcquireStart	1314	Excluded
HoldStart->ClockStart	859	Covered	T2,T3,T9
HoldStart->Idle	1312	Excluded
HoldStop->AcquireStart	1314	Excluded
HoldStop->Idle	1041	Covered	T14,T56,T27
HoldStop->PopFmtFifo	1045	Covered	T2,T3,T9
HostClockLowAck->AcquireStart	1314	Excluded
HostClockLowAck->HostClockPulseAck	980	Covered	T2,T3,T10
HostClockLowAck->Idle	1312	Excluded
HostClockPulseAck->AcquireStart	1314	Excluded
HostClockPulseAck->HostHoldBitAck	989	Covered	T2,T3,T10
HostClockPulseAck->Idle	1312	Not Covered
HostHoldBitAck->AcquireStart	1314	Excluded
HostHoldBitAck->ClockStop	1001	Covered	T2,T3,T10
HostHoldBitAck->Idle	1312	Not Covered
HostHoldBitAck->PopFmtFifo	1005	Covered	T3,T30,T31
HostHoldBitAck->ReadClockLow	1010	Covered	T2,T3,T10
Idle->AcquireStart	1314	Covered	T6,T7,T8
Idle->Active	843	Covered	T2,T3,T9
PopFmtFifo->AcquireStart	1314	Excluded
PopFmtFifo->Active	1082	Covered	T2,T3,T9
PopFmtFifo->ClockStop	1074	Covered	T14,T56,T27
PopFmtFifo->Idle	1078	Covered	T2,T3,T9
ReadClockLow->AcquireStart	1314	Excluded
ReadClockLow->Idle	1312	Not Covered
ReadClockLow->ReadClockPulse	946	Covered	T2,T3,T10
ReadClockPulse->AcquireStart	1314	Excluded
ReadClockPulse->Idle	1312	Not Covered
ReadClockPulse->ReadHoldBit	954	Covered	T2,T3,T10
ReadHoldBit->AcquireStart	1314	Excluded
ReadHoldBit->HostClockLowAck	966	Covered	T2,T3,T10
ReadHoldBit->Idle	1312	Not Covered
ReadHoldBit->ReadClockLow	970	Covered	T2,T3,T10
SetupStart->AcquireStart	1314	Excluded
SetupStart->HoldStart	850	Covered	T2,T3,T9
SetupStart->Idle	1312	Excluded
SetupStop->AcquireStart	1314	Excluded
SetupStop->HoldStop	1029	Covered	T2,T3,T9
SetupStop->Idle	1312	Excluded
StretchAcqFull->AcquireByte	1279	Covered	T6,T20,T45
StretchAcqFull->AcquireStart	1314	Covered	T43,T44
StretchAcqFull->Idle	1312	Covered	T43,T44
StretchAddr->AcquireByte	1248	Covered	T6,T20,T45
StretchAddr->AcquireStart	1314	Covered	T43,T44
StretchAddr->Idle	1312	Covered	T43,T44
StretchAddr->StretchTx	1248	Covered	T46,T47,T48
StretchTx->AcquireStart	1314	Covered	T43,T44
StretchTx->Idle	1312	Covered	T43,T44
StretchTx->StretchTxSetup	1262	Covered	T6,T7,T8
StretchTxSetup->AcquireStart	1314	Covered	T43,T44
StretchTxSetup->Idle	1312	Covered	T43,T44
StretchTxSetup->TransmitSetup	1272	Covered	T6,T7,T8
TransmitAck->AcquireStart	1314	Covered	T43,T44
TransmitAck->Idle	1312	Covered	T43,T44
TransmitAck->TransmitAckPulse	1179	Covered	T6,T7,T8
TransmitAckPulse->AcquireStart	1314	Covered	T57,T58,T43
TransmitAckPulse->Idle	1312	Covered	T43,T44
TransmitAckPulse->TransmitWait	1189	Covered	T6,T7,T8
TransmitAckPulse->WaitForStop	1192	Covered	T6,T7,T8
TransmitHold->AcquireStart	1314	Covered	T43,T44
TransmitHold->Idle	1312	Covered	T43,T44
TransmitHold->TransmitAck	1167	Covered	T6,T7,T8
TransmitHold->TransmitSetup	1171	Covered	T6,T7,T8
TransmitPulse->AcquireStart	1314	Covered	T6,T34,T23
TransmitPulse->Idle	1312	Covered	T6,T34,T23
TransmitPulse->TransmitHold	1158	Covered	T6,T7,T8
TransmitSetup->AcquireStart	1314	Covered	T43,T44
TransmitSetup->Idle	1312	Covered	T43,T44
TransmitSetup->TransmitPulse	1153	Covered	T6,T7,T8
TransmitWait->AcquireStart	1314	Covered	T43,T44
TransmitWait->Idle	1312	Covered	T43,T44
TransmitWait->StretchTx	1144	Covered	T6,T7,T8
TransmitWait->TransmitSetup	1146	Covered	T6,T7,T8
WaitForStop->AcquireStart	1314	Covered	T6,T7,T8
WaitForStop->Idle	1312	Covered	T6,T7,T8

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_fsm

	Line No.	Total	Covered	Percent
Branches		258	247	95.74
IF	154	14	13	92.86
IF	180	2	2	100.00
IF	193	5	5	100.00
IF	209	4	4	100.00
IF	222	4	4	100.00
IF	233	3	3	100.00
IF	240	4	4	100.00
IF	253	2	2	100.00
IF	267	5	5	100.00
IF	279	5	4	80.00
IF	301	5	5	100.00
IF	322	5	5	100.00
IF	333	4	4	100.00
IF	410	4	4	100.00
IF	433	3	3	100.00
CASE	475	73	67	91.78
IF	795	3	3	100.00
CASE	838	105	103	98.10
IF	1303	4	3	75.00
IF	1322	2	2	100.00
IF	1331	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	154	if (load_tcount)
-2-:	155	case (tcount_sel)
-3-:	169	if (((stretch_idle_cnt == '0) || target_enable_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	tSetupStart	-	Covered	T2,T3,T9
1	tHoldStart	-	Covered	T2,T3,T9
1	tSetupData	-	Covered	T6,T7,T8
1	tClockStart	-	Covered	T2,T3,T6
1	tClockLow	-	Covered	T2,T3,T9
1	tClockPulse	-	Covered	T2,T3,T9
1	tHoldBit	-	Covered	T2,T3,T9
1	tClockStop	-	Covered	T2,T3,T9
1	tSetupStop	-	Covered	T2,T3,T9
1	tHoldStop	-	Covered	T2,T3,T9
1	tNoDelay	-	Covered	T2,T3,T9
1	default	-	Not Covered
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T2,T3,T9

	LineNo.	Expression
-1-:	180	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	193	if ((!rst_ni))
-2-:	195	if (((stretch_en && scl_d) && (!scl_i)))
-3-:	197	if (((!target_idle_o) && event_host_timeout_o))
-4-:	200	if (((!target_idle_o) && scl_i))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T3,T9
0	0	1	-	Covered	T15,T22,T23
0	0	0	1	Covered	T6,T7,T8
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	209	if ((!rst_ni))
-2-:	211	if (bit_clr)
-3-:	213	if (bit_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T9
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	222	if ((!rst_ni))
-2-:	224	if (read_byte_clr)
-3-:	226	if (shift_data_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T10
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	233	if ((!fmt_flag_read_bytes_i))
-2-:	234	if ((fmt_byte_i == '0))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T24,T25,T26
0	0	Covered	T2,T3,T10

	LineNo.	Expression
-1-:	240	if ((!rst_ni))
-2-:	242	if (byte_clr)
-3-:	244	if (byte_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T10
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	267	if ((!rst_ni))
-2-:	269	if ((trans_started && (!host_enable_i)))
-3-:	271	if (log_start)
-4-:	273	if (log_stop)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T27,T28,T29
0	0	1	-	Covered	T2,T3,T9
0	0	0	1	Covered	T2,T3,T9
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	279	if ((!rst_ni))
-2-:	281	if ((pend_restart && (!host_enable_i)))
-3-:	283	if (req_restart)
-4-:	285	if (log_start)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Covered	T3,T30,T31
0	0	0	1	Covered	T2,T3,T9
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	301	if ((!rst_ni))
-2-:	303	if (start_det)
-3-:	305	if ((scl_i_q && (!scl_i)))
-4-:	308	if ((input_byte_clr || bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T6,T7,T8
0	0	1	1	Covered	T2,T3,T6
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	322	if ((!rst_ni))
-2-:	324	if (input_byte_clr)
-3-:	326	if (((!scl_i_q) && scl_i))
-4-:	327	if ((!bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T6,T7,T8
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T2,T3,T6
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	333	if ((!rst_ni))
-2-:	335	if (((!scl_i_q) && scl_i))
-3-:	336	if (bit_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T2,T3,T6
0	1	0	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	410	if ((!rst_ni))
-2-:	412	if (((!en_sda_interf_det) && (|sda_rise_cnt)))
-3-:	417	if ((en_sda_interf_det && (sda_rise_cnt < sda_rise_latency)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T9
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	433	if ((!rst_ni))
-2-:	435	if ((bit_ack && address_match))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	case (state_q)
-2-:	481	if ((host_enable_i && trans_started))
-3-:	494	if (log_start)
-4-:	510	if (pend_restart)
-5-:	523	if ((scl_i_q && (!scl_i)))
-6-:	524	if ((sda_i_q != sda_i))
-7-:	543	if (((((!scl_i_q) && scl_i) && sda_i) && (!fmt_flag_nak_ok_i)))
-8-:	545	if ((scl_i_q && (!scl_i)))
-9-:	546	if ((sda_i_q != sda_i))
-10-:	565	if ((scl_i_q && (!scl_i)))
-11-:	566	if ((sda_i_q != sda_i))
-12-:	572	if (((bit_index == '0) && (tcount_q == 20'b1)))
-13-:	584	if (fmt_flag_read_continue_i)
-14-:	585	if ((byte_index == 9'b1))
-15-:	591	if (fmt_flag_read_continue_i)
-16-:	592	if ((byte_index == 9'b1))
-17-:	596	if ((scl_i_q && (!scl_i)))
-18-:	597	if ((sda_i_q != sda_i))
-19-:	602	if (fmt_flag_read_continue_i)
-20-:	603	if ((byte_index == 9'b1))
-21-:	639	if (fmt_flag_stop_after_i)
-22-:	672	if ((tcount_q == 20'b1))
-23-:	707	if ((!scl_i))
-24-:	741	if ((tcount_q == 20'b1))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
Idle	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SetupStart	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
SetupStart	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
HoldStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
ClockStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
ClockLow	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T30,T31
ClockLow	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
ClockPulse	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClockPulse	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
ClockPulse	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T30
ClockPulse	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
ClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
ClockPulseAck	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T27,T36
ClockPulseAck	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
ClockPulseAck	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClockPulseAck	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
ClockPulseAck	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
ClockPulseAck	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
ReadClockLow	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
ReadClockPulse	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadClockPulse	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
ReadClockPulse	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
ReadClockPulse	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T30,T31
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T3,T30,T31
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T3,T10
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T30,T31
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T3,T10
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T3,T30,T31
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T2,T3,T10
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	Covered	T2,T3,T10
ClockStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T2,T3,T9
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T2,T3,T9
AcquireStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrRead	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AddrAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T6,T7,T8
AddrAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T6,T7,T8
TransmitWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
TransmitSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
TransmitPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
TransmitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T6,T7,T8
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T6,T7,T8
WaitForStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T7,T8
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T6,T7,T8
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T20,T45
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
StretchTxSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T20,T45
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	795	if ((start_det || stop_det))
-2-:	798	(start_det) ? 

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	838	case (state_q)
-2-:	841	if (((!host_enable_i) && (!target_enable_i)))
-3-:	842	if (host_enable_i)
-4-:	843	if (fmt_fifo_rvalid_i)
-5-:	849	if ((tcount_q == 20'b1))
-6-:	858	if ((tcount_q == 20'b1))
-7-:	866	if ((tcount_q == 20'b1))
-8-:	875	if ((tcount_q == 20'b1))
-9-:	877	if (pend_restart)
-10-:	890	if ((tcount_q == 20'b1))
-11-:	899	if ((tcount_q == 20'b1))
-12-:	903	if ((bit_index == '0))
-13-:	915	if ((tcount_q == 20'b1))
-14-:	923	if ((tcount_q == 20'b1))
-15-:	931	if ((tcount_q == 20'b1))
-16-:	932	if (fmt_flag_stop_after_i)
-17-:	945	if ((tcount_q == 20'b1))
-18-:	953	if ((tcount_q == 20'b1))
-19-:	962	if ((tcount_q == 20'b1))
-20-:	965	if ((bit_index == '0))
-21-:	979	if ((tcount_q == 20'b1))
-22-:	988	if ((tcount_q == 20'b1))
-23-:	997	if ((tcount_q == 20'b1))
-24-:	999	if ((byte_index == 9'b1))
-25-:	1000	if (fmt_flag_stop_after_i)
-26-:	1020	if ((tcount_q == 20'b1))
-27-:	1028	if ((tcount_q == 20'b1))
-28-:	1038	if ((tcount_q == 20'b1))
-29-:	1040	if ((!host_enable_i))
-30-:	1054	if (fmt_flag_read_bytes_i)
-31-:	1059	if ((fmt_flag_start_before_i && (!trans_started)))
-32-:	1073	if ((!host_enable_i))
-33-:	1077	if ((fmt_fifo_depth_i == 7'b1))
-34-:	1090	if ((scl_i_q && (!scl_i)))
-35-:	1099	if ((bit_ack && address_match))
-36-:	1103	if ((bit_ack && (!address_match)))
-37-:	1110	if (((tcount_q == 20'b1) && (!scl_i)))
-38-:	1116	if (scl_i)
-39-:	1120	if ((!scl_i))
-40-:	1128	if ((tcount_q == 20'b1))
-41-:	1132	if (stretch_addr)
-42-:	1134	if (rw_bit_q)
-43-:	1136	if ((!rw_bit_q))
-44-:	1143	if (stretch_tx)
-45-:	1153	if (scl_i)
-46-:	1157	if ((!scl_i))
-47-:	1165	if ((tcount_q == 20'b1))
-48-:	1166	if (bit_ack)
-49-:	1178	if (scl_i)
-50-:	1186	if ((!scl_i))
-51-:	1188	if (host_ack)
-52-:	1206	if (bit_ack)
-53-:	1215	if (((tcount_q == 20'b1) && (!scl_i)))
-54-:	1221	if (scl_i)
-55-:	1225	if ((!scl_i))
-56-:	1233	if ((tcount_q == 20'b1))
-57-:	1236	(acq_fifo_wready) ? 
-58-:	1242	if ((!stretch_addr))
-59-:	1248	(rw_bit_q) ? 
-60-:	1255	if ((!stretch_tx))
-61-:	1271	if ((tcount_q == 20'b1))
-62-:	1279	if (acq_fifo_wready)

Branches:

Branch	Status	Tests
(1.Idle )->(2)	Covered	T1,T2,T3
(1.Idle )->(!2)->(3)->(4)	Covered	T2,T3,T9
(1.Idle )->(!2)->(3)->(!4)	Covered	T1,T2,T3
(1.Idle )->(!2)->(!3)	Covered	T6,T7,T8
(1.SetupStart )->(5)	Covered	T2,T3,T9
(1.SetupStart )->(!5)	Covered	T2,T3,T9
(1.HoldStart )->(6)	Covered	T2,T3,T9
(1.HoldStart )->(!6)	Covered	T2,T3,T9
(1.ClockStart )->(7)	Covered	T2,T3,T9
(1.ClockStart )->(!7)	Covered	T2,T9,T21
(1.ClockLow )->(8)->(9)	Covered	T3,T30,T31
(1.ClockLow )->(8)->(!9)	Covered	T2,T3,T9
(1.ClockLow )->(!8)	Covered	T2,T3,T9
(1.ClockPulse )->(10)	Covered	T2,T3,T9
(1.ClockPulse )->(!10)	Covered	T2,T3,T9
(1.HoldBit )->(11)->(12)	Covered	T2,T3,T9
(1.HoldBit )->(11)->(!12)	Covered	T2,T3,T9
(1.HoldBit )->(!11)	Covered	T2,T3,T9
(1.ClockLowAck )->(13)	Covered	T2,T3,T9
(1.ClockLowAck )->(!13)	Covered	T2,T3,T9
(1.ClockPulseAck )->(14)	Covered	T2,T3,T9
(1.ClockPulseAck )->(!14)	Covered	T2,T3,T9
(1.HoldDevAck )->(15)->(16)	Covered	T2,T3,T9
(1.HoldDevAck )->(15)->(!16)	Covered	T2,T3,T9
(1.HoldDevAck )->(!15)	Covered	T2,T3,T9
(1.ReadClockLow )->(17)	Covered	T2,T3,T10
(1.ReadClockLow )->(!17)	Covered	T2,T3,T10
(1.ReadClockPulse )->(18)	Covered	T2,T3,T10
(1.ReadClockPulse )->(!18)	Covered	T2,T3,T10
(1.ReadHoldBit )->(19)->(20)	Covered	T2,T3,T10
(1.ReadHoldBit )->(19)->(!20)	Covered	T2,T3,T10
(1.ReadHoldBit )->(!19)	Covered	T2,T3,T10
(1.HostClockLowAck )->(21)	Covered	T2,T3,T10
(1.HostClockLowAck )->(!21)	Covered	T2,T3,T10
(1.HostClockPulseAck )->(22)	Covered	T2,T3,T10
(1.HostClockPulseAck )->(!22)	Covered	T2,T3,T10
(1.HostHoldBitAck )->(23)->(24)->(25)	Covered	T2,T3,T10
(1.HostHoldBitAck )->(23)->(24)->(!25)	Covered	T3,T30,T31
(1.HostHoldBitAck )->(23)->(!24)	Covered	T2,T3,T10
(1.HostHoldBitAck )->(!23)	Covered	T2,T3,T10
(1.ClockStop )->(26)	Covered	T2,T3,T9
(1.ClockStop )->(!26)	Covered	T2,T3,T9
(1.SetupStop )->(27)	Covered	T2,T3,T9
(1.SetupStop )->(!27)	Covered	T2,T3,T9
(1.HoldStop )->(28)->(29)	Covered	T14,T56,T27
(1.HoldStop )->(28)->(!29)	Covered	T2,T3,T9
(1.HoldStop )->(!28)	Covered	T2,T3,T9
(1.Active )->(30)	Covered	T2,T3,T10
(1.Active )->(!30)->(31)	Covered	T2,T3,T9
(1.Active )->(!30)->(!31)	Covered	T2,T3,T9
(1.PopFmtFifo )->(32)	Covered	T14,T56,T27
(1.PopFmtFifo )->(!32)->(33)	Covered	T2,T3,T9
(1.PopFmtFifo )->(!32)->(!33)	Covered	T2,T3,T9
(1.AcquireStart )->(34)	Covered	T6,T7,T8
(1.AcquireStart )->(!34)	Covered	T6,T7,T8
(1.AddrRead )->(35)	Covered	T6,T7,T8
(1.AddrRead )->(!35)->(36)	Covered	T7,T32,T33
(1.AddrRead )->(!35)->(!36)	Covered	T6,T7,T8
(1.AddrAckWait )->(37)	Covered	T6,T7,T8
(1.AddrAckWait )->(!37)	Covered	T6,T7,T8
(1.AddrAckSetup )->(38)	Covered	T6,T7,T8
(1.AddrAckSetup )->(!38)	Covered	T6,T7,T8
(1.AddrAckPulse )->(39)	Covered	T6,T7,T8
(1.AddrAckPulse )->(!39)	Covered	T6,T7,T8
(1.AddrAckHold )->(40)->(41)	Covered	T6,T20,T45
(1.AddrAckHold )->(40)->(!41)->(42)	Covered	T6,T7,T8
(1.AddrAckHold )->(40)->(!41)->(!42)->(43)	Covered	T6,T7,T8
(1.AddrAckHold )->(40)->(!41)->(!42)->(!43)	Not Covered
(1.AddrAckHold )->(!40)	Covered	T6,T7,T8
(1.TransmitWait )->(44)	Covered	T6,T7,T8
(1.TransmitWait )->(!44)	Covered	T6,T7,T8
(1.TransmitSetup )->(45)	Covered	T6,T7,T8
(1.TransmitSetup )->(!45)	Covered	T6,T7,T8
(1.TransmitPulse )->(46)	Covered	T6,T7,T8
(1.TransmitPulse )->(!46)	Covered	T6,T7,T8
(1.TransmitHold )->(47)->(48)	Covered	T6,T7,T8
(1.TransmitHold )->(47)->(!48)	Covered	T6,T7,T8
(1.TransmitHold )->(!47)	Covered	T6,T7,T8
(1.TransmitAck )->(49)	Covered	T6,T7,T8
(1.TransmitAck )->(!49)	Covered	T6,T7,T8
(1.TransmitAckPulse )->(50)->(51)	Covered	T6,T7,T8
(1.TransmitAckPulse )->(50)->(!51)	Covered	T6,T7,T8
(1.TransmitAckPulse )->(!50)	Covered	T6,T7,T8
(1.WaitForStop )	Covered	T6,T7,T8
(1.AcquireByte )->(52)	Covered	T6,T7,T8
(1.AcquireByte )->(!52)	Covered	T6,T7,T8
(1.AcquireAckWait )->(53)	Covered	T6,T7,T8
(1.AcquireAckWait )->(!53)	Covered	T6,T7,T8
(1.AcquireAckSetup )->(54)	Covered	T6,T7,T8
(1.AcquireAckSetup )->(!54)	Covered	T6,T7,T8
(1.AcquireAckPulse )->(55)	Covered	T6,T7,T8
(1.AcquireAckPulse )->(!55)	Covered	T6,T7,T8
(1.AcquireAckHold )->(56)->(57)	Covered	T6,T7,T8
(1.AcquireAckHold )->(56)->(!57)	Covered	T6,T20,T45
(1.AcquireAckHold )->(!56)	Covered	T6,T7,T8
(1.StretchAddr )->(58)->(59)	Covered	T46,T47,T48
(1.StretchAddr )->(58)->(!59)	Covered	T6,T20,T45
(1.StretchAddr )->(!58)	Covered	T6,T20,T45
(1.StretchTx )->(60)	Covered	T6,T7,T8
(1.StretchTx )->(!60)	Covered	T6,T7,T8
(1.StretchTxSetup )->(61)	Covered	T6,T7,T8
(1.StretchTxSetup )->(!61)	Covered	T6,T7,T8
(1.StretchAcqFull )->(62)	Covered	T6,T20,T45
(1.StretchAcqFull )->(!62)	Covered	T6,T20,T45
(1.default)	Not Covered

	LineNo.	Expression
-1-:	1303	if (((!target_idle) && (!target_enable_i)))
-2-:	1313	if (start_det)
-3-:	1315	if (stop_det)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T6,T7,T8
0	0	1	Covered	T6,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1322	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1331	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AcqDepthRdCheck_A	519564966	4049790	0	0
SclInputGlitch_A	498147910	11028579	0	0
SclOutputGlitch_A	519564966	5659414	0	0
SclSdaChangeNotSimultaneous_A	519564966	519382236	0	0

AcqDepthRdCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519564966	4049790	0	0
T6	172101	4334	0	0
T7	104575	52	0	0
T8	68004	442	0	0
T9	21395	0	0	0
T10	47643	0	0	0
T11	467049	0	0	0
T15	0	36042	0	0
T18	248389	8573	0	0
T19	0	23180	0	0
T20	289854	0	0	0
T21	25418	0	0	0
T22	0	706	0	0
T45	558402	0	0	0
T59	0	276	0	0
T60	0	569	0	0
T61	0	213	0	0

SclInputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498147910	11028579	0	0
T1	1018	2	0	0
T2	98933	3382	0	0
T3	324859	20702	0	0
T6	172101	23375	0	0
T7	104575	3229	0	0
T8	68004	2764	0	0
T9	21395	802	0	0
T10	47643	1722	0	0
T20	289854	3332	0	0
T21	25418	910	0	0

SclOutputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519564966	5659414	0	0
T2	98933	3382	0	0
T3	324859	20702	0	0
T6	172101	701	0	0
T7	104575	7	0	0
T8	68004	19	0	0
T9	21395	802	0	0
T10	47643	1722	0	0
T18	248389	68	0	0
T20	289854	310	0	0
T21	25418	910	0	0

SclSdaChangeNotSimultaneous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519564966	519382236	0	0
T1	1018	932	0	0
T2	98933	98877	0	0
T3	324859	324795	0	0
T6	172101	172085	0	0
T7	104575	104488	0	0
T8	68004	67923	0	0
T9	21395	21296	0	0
T10	47643	47572	0	0
T20	289854	289846	0	0
T21	25418	25345	0	0