Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	520162721	12177	0	0
ctrl_rd_A	520162721	1463	0	0
fifo_ctrl_rd_A	520162721	4759	0	0
host_timeout_ctrl_rd_A	520162721	1112	0	0
intr_enable_rd_A	520162721	4355	0	0
ovrd_rd_A	520162721	2414	0	0
target_id_rd_A	520162721	1667	0	0
timeout_ctrl_rd_A	520162721	1458	0	0
timing0_rd_A	520162721	1434	0	0
timing1_rd_A	520162721	1345	0	0
timing2_rd_A	520162721	1351	0	0
timing3_rd_A	520162721	1309	0	0
timing4_rd_A	520162721	1390	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520162721	12177	0	0
T75	4331	4	0	0
T76	2352	10	0	0
T77	6328	3	0	0
T78	11176	594	0	0
T79	2872	50	0	0
T80	6617	5	0	0
T81	3682	956	0	0
T85	13120	862	0	0
T91	8260	398	0	0
T97	4601	769	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520162721	1463	0	0
T76	2352	2	0	0
T78	11176	12	0	0
T80	6617	31	0	0
T85	13120	16	0	0
T91	8260	12	0	0
T117	2433	10	0	0
T118	2451	10	0	0
T128	3064	41	0	0
T129	2889	18	0	0
T135	1915	13	0	0

fifo_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520162721	4759	0	0
T12	640330	0	0	0
T14	204959	0	0	0
T33	79543	0	0	0
T38	0	148	0	0
T74	383662	76	0	0
T136	0	113	0	0
T137	0	130	0	0
T138	0	125	0	0
T139	0	113	0	0
T140	0	66	0	0
T141	0	161	0	0
T142	0	139	0	0
T143	0	66	0	0
T144	795148	0	0	0
T145	35129	0	0	0
T146	277678	0	0	0
T147	168645	0	0	0
T148	107923	0	0	0
T149	131899	0	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520162721	1112	0	0
T76	2352	2	0	0
T78	11176	7	0	0
T80	6617	24	0	0
T85	13120	20	0	0
T91	8260	25	0	0
T117	2433	2	0	0
T118	2451	8	0	0
T128	3064	8	0	0
T129	2889	25	0	0
T135	1915	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520162721	4355	0	0
T47	466911	0	0	0
T76	0	5	0	0
T80	0	242	0	0
T142	0	9	0	0
T150	685276	31	0	0
T151	0	34	0	0
T152	0	19	0	0
T153	0	64	0	0
T154	0	22	0	0
T155	0	14	0	0
T156	0	9	0	0
T157	601510	0	0	0
T158	179461	0	0	0
T159	95114	0	0	0
T160	22220	0	0	0
T161	103310	0	0	0
T162	52587	0	0	0
T163	131054	0	0	0
T164	71831	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520162721	2414	0	0
T5	1134	50	0	0
T24	245124	0	0	0
T56	286692	0	0	0
T165	1360	67	0	0
T166	0	59	0	0
T167	0	26	0	0
T168	0	59	0	0
T169	0	48	0	0
T170	0	44	0	0
T171	0	91	0	0
T172	0	33	0	0
T173	0	98	0	0
T174	25754	0	0	0
T175	3028	0	0	0
T176	96610	0	0	0
T177	244286	0	0	0
T178	523535	0	0	0
T179	82859	0	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520162721	1667	0	0
T78	11176	16	0	0
T80	6617	70	0	0
T85	13120	15	0	0
T91	8260	7	0	0
T117	2433	22	0	0
T118	2451	31	0	0
T120	40982	436	0	0
T128	3064	27	0	0
T129	2889	22	0	0
T180	4555	59	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520162721	1458	0	0
T78	11176	4	0	0
T80	6617	42	0	0
T85	13120	24	0	0
T91	8260	23	0	0
T117	2433	13	0	0
T118	2451	9	0	0
T128	3064	25	0	0
T129	2889	5	0	0
T135	1915	8	0	0
T180	4555	56	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520162721	1434	0	0
T76	2352	10	0	0
T78	11176	16	0	0
T80	6617	57	0	0
T85	13120	5	0	0
T91	8260	14	0	0
T117	2433	8	0	0
T118	2451	11	0	0
T129	2889	7	0	0
T135	1915	10	0	0
T180	4555	68	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520162721	1345	0	0
T76	2352	9	0	0
T78	11176	16	0	0
T80	6617	76	0	0
T85	13120	31	0	0
T91	8260	3	0	0
T117	2433	20	0	0
T118	2451	7	0	0
T128	3064	8	0	0
T129	2889	5	0	0
T135	1915	9	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520162721	1351	0	0
T78	11176	8	0	0
T80	6617	58	0	0
T85	13120	14	0	0
T91	8260	17	0	0
T117	2433	6	0	0
T118	2451	5	0	0
T128	3064	11	0	0
T129	2889	6	0	0
T135	1915	1	0	0
T180	4555	39	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520162721	1309	0	0
T76	2352	8	0	0
T78	11176	15	0	0
T80	6617	57	0	0
T85	13120	9	0	0
T91	8260	15	0	0
T117	2433	3	0	0
T118	2451	12	0	0
T128	3064	18	0	0
T129	2889	22	0	0
T135	1915	1	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520162721	1390	0	0
T76	2352	5	0	0
T78	11176	2	0	0
T80	6617	61	0	0
T85	13120	12	0	0
T91	8260	17	0	0
T117	2433	15	0	0
T118	2451	22	0	0
T128	3064	2	0	0
T129	2889	4	0	0
T135	1915	6	0	0