Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}
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Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
93.67 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 19 0 19 100.00
Crosses 60 5 55 91.67


Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 15 0 15 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_cg_cc 60 5 55 91.67 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 6702005 1 T1 2 T2 5204 T3 22701
all_values[1] 6702005 1 T1 2 T2 5204 T3 22701
all_values[2] 6702005 1 T1 2 T2 5204 T3 22701
all_values[3] 6702005 1 T1 2 T2 5204 T3 22701
all_values[4] 6702005 1 T1 2 T2 5204 T3 22701
all_values[5] 6702005 1 T1 2 T2 5204 T3 22701
all_values[6] 6702005 1 T1 2 T2 5204 T3 22701
all_values[7] 6702005 1 T1 2 T2 5204 T3 22701
all_values[8] 6702005 1 T1 2 T2 5204 T3 22701
all_values[9] 6702005 1 T1 2 T2 5204 T3 22701
all_values[10] 6702005 1 T1 2 T2 5204 T3 22701
all_values[11] 6702005 1 T1 2 T2 5204 T3 22701
all_values[12] 6702005 1 T1 2 T2 5204 T3 22701
all_values[13] 6702005 1 T1 2 T2 5204 T3 22701
all_values[14] 6702005 1 T1 2 T2 5204 T3 22701



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 95001308 1 T1 30 T2 71086 T3 338737
auto[1] 5528767 1 T2 6974 T3 1778 T11 4



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 94180835 1 T1 30 T2 78060 T3 340515
auto[1] 6349240 1 T26 66704 T61 162725 T59 67637



Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 60 5 55 91.67 5


Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins
cp_intrcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[2] , all_values[3]] [auto[1]] [auto[0]] -- -- 2
[all_values[5]] [auto[1]] [auto[0]] 0 1 1
[all_values[12]] [auto[1]] [auto[0]] 0 1 1
[all_values[14]] [auto[1]] [auto[0]] 0 1 1


Covered bins
cp_intrcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] 5596181 1 T1 2 T2 5204 T3 22692
all_values[0] auto[0] auto[1] 250345 1 T61 8220 T59 4503 T60 42236
all_values[0] auto[1] auto[0] 775369 1 T3 9 T9 1 T10 7
all_values[0] auto[1] auto[1] 80110 1 T61 5341 T59 7 T60 24
all_values[1] auto[0] auto[0] 5653147 1 T1 2 T2 5204 T3 22607
all_values[1] auto[0] auto[1] 431171 1 T26 5128 T61 11994 T59 4413
all_values[1] auto[1] auto[0] 556277 1 T3 94 T11 1 T9 13
all_values[1] auto[1] auto[1] 61410 1 T26 2 T61 1567 T59 97
all_values[2] auto[0] auto[0] 6194941 1 T1 2 T2 5204 T3 22701
all_values[2] auto[0] auto[1] 506847 1 T26 5130 T61 13559 T59 4505
all_values[2] auto[1] auto[1] 217 1 T26 1 T61 2 T59 3
all_values[3] auto[0] auto[0] 6200756 1 T1 2 T2 5204 T3 22701
all_values[3] auto[0] auto[1] 501054 1 T26 5132 T59 4507 T60 42258
all_values[3] auto[1] auto[1] 195 1 T59 3 T60 2 T130 1
all_values[4] auto[0] auto[0] 6406773 1 T1 2 T2 5204 T3 22701
all_values[4] auto[0] auto[1] 295001 1 T26 5128 T59 4508 T60 42259
all_values[4] auto[1] auto[0] 41 1 T38 41 - - - -
all_values[4] auto[1] auto[1] 190 1 T26 3 T60 1 T130 2
all_values[5] auto[0] auto[0] 6413085 1 T1 2 T2 5204 T3 22701
all_values[5] auto[0] auto[1] 288718 1 T26 5130 T61 13559 T59 4507
all_values[5] auto[1] auto[1] 202 1 T26 2 T61 2 T59 3
all_values[6] auto[0] auto[0] 5443911 1 T1 2 T2 5204 T3 22666
all_values[6] auto[0] auto[1] 352942 1 T26 5129 T61 7519 T59 4474
all_values[6] auto[1] auto[0] 809978 1 T3 35 T11 1 T9 10
all_values[6] auto[1] auto[1] 95174 1 T26 3 T61 6041 T59 36
all_values[7] auto[0] auto[0] 5905276 1 T1 2 T2 5204 T3 21325
all_values[7] auto[0] auto[1] 469566 1 T26 4746 T61 11568 T59 3921
all_values[7] auto[1] auto[0] 301696 1 T3 1376 T9 59 T10 1992
all_values[7] auto[1] auto[1] 25467 1 T26 386 T61 1992 T59 585
all_values[8] auto[0] auto[0] 5411808 1 T1 2 T2 5204 T3 22463
all_values[8] auto[0] auto[1] 206538 1 T61 6954 T59 4269 T60 41565
all_values[8] auto[1] auto[0] 994209 1 T3 238 T11 1 T9 2
all_values[8] auto[1] auto[1] 89450 1 T61 6605 T59 241 T60 694
all_values[9] auto[0] auto[0] 5226812 1 T1 2 T2 4062 T3 22675
all_values[9] auto[0] auto[1] 388375 1 T26 5127 T59 4479 T60 42193
all_values[9] auto[1] auto[0] 993732 1 T2 1142 T3 26 T11 1
all_values[9] auto[1] auto[1] 93086 1 T26 4 T59 30 T60 67
all_values[10] auto[0] auto[0] 6009594 1 T1 2 T2 3958 T3 22701
all_values[10] auto[0] auto[1] 526831 1 T26 5129 T61 13558 T59 4506
all_values[10] auto[1] auto[0] 165395 1 T2 1246 T16 2210 T17 2521
all_values[10] auto[1] auto[1] 185 1 T26 2 T61 1 T59 4
all_values[11] auto[0] auto[0] 5907716 1 T1 2 T2 618 T3 22701
all_values[11] auto[0] auto[1] 308545 1 T26 5128 T61 13560 T59 4505
all_values[11] auto[1] auto[0] 485542 1 T2 4586 T16 3805 T17 5245
all_values[11] auto[1] auto[1] 202 1 T26 4 T61 1 T59 4
all_values[12] auto[0] auto[0] 6174978 1 T1 2 T2 5204 T3 22701
all_values[12] auto[0] auto[1] 526840 1 T26 5129 T61 13558 T59 4505
all_values[12] auto[1] auto[1] 187 1 T26 1 T61 2 T59 2
all_values[13] auto[0] auto[0] 6187159 1 T1 2 T2 5204 T3 22701
all_values[13] auto[0] auto[1] 514619 1 T26 5128 T61 13559 T59 4506
all_values[13] auto[1] auto[0] 13 1 T206 1 T194 1 T195 1
all_values[13] auto[1] auto[1] 214 1 T26 2 T61 2 T59 4
all_values[14] auto[0] auto[0] 6366446 1 T1 2 T2 5204 T3 22701
all_values[14] auto[0] auto[1] 335333 1 T26 5128 T61 13557 T59 4506
all_values[14] auto[1] auto[1] 226 1 T26 2 T61 4 T59 4

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