Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6702005	1			T1	2		T2	5204		T3	22701
all_pins[1]	6702005	1			T1	2		T2	5204		T3	22701
all_pins[2]	6702005	1			T1	2		T2	5204		T3	22701
all_pins[3]	6702005	1			T1	2		T2	5204		T3	22701
all_pins[4]	6702005	1			T1	2		T2	5204		T3	22701
all_pins[5]	6702005	1			T1	2		T2	5204		T3	22701
all_pins[6]	6702005	1			T1	2		T2	5204		T3	22701
all_pins[7]	6702005	1			T1	2		T2	5204		T3	22701
all_pins[8]	6702005	1			T1	2		T2	5204		T3	22701
all_pins[9]	6702005	1			T1	2		T2	5204		T3	22701
all_pins[10]	6702005	1			T1	2		T2	5204		T3	22701
all_pins[11]	6702005	1			T1	2		T2	5204		T3	22701
all_pins[12]	6702005	1			T1	2		T2	5204		T3	22701
all_pins[13]	6702005	1			T1	2		T2	5204		T3	22701
all_pins[14]	6702005	1			T1	2		T2	5204		T3	22701

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	94926707	1			T1	30		T2	71081		T3	338488
values[0x1]	5603368	1			T2	6979		T3	2027		T11	4
transitions[0x0=>0x1]	3796671	1			T2	5419		T3	2010		T11	3
transitions[0x1=>0x0]	3796684	1			T2	5419		T3	2010		T11	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	5846325	1			T1	2		T2	5204		T3	22691
all_pins[0]	values[0x1]	855680	1			T3	10		T9	1		T10	9
all_pins[0]	transitions[0x0=>0x1]	262401	1			T3	10		T9	1		T10	9
all_pins[0]	transitions[0x1=>0x0]	26774	1			T3	109		T11	1		T9	13
all_pins[1]	values[0x0]	6081952	1			T1	2		T2	5204		T3	22592
all_pins[1]	values[0x1]	620053	1			T3	109		T11	1		T9	13
all_pins[1]	transitions[0x0=>0x1]	620016	1			T3	109		T11	1		T9	13
all_pins[1]	transitions[0x1=>0x0]	74	1			T26	1		T59	3		T130	1
all_pins[2]	values[0x0]	6701894	1			T1	2		T2	5204		T3	22701
all_pins[2]	values[0x1]	111	1			T26	1		T59	3		T60	1
all_pins[2]	transitions[0x0=>0x1]	85	1			T26	1		T59	3		T60	1
all_pins[2]	transitions[0x1=>0x0]	80	1			T59	1		T140	2		T146	1
all_pins[3]	values[0x0]	6701899	1			T1	2		T2	5204		T3	22701
all_pins[3]	values[0x1]	106	1			T59	1		T140	3		T146	1
all_pins[3]	transitions[0x0=>0x1]	78	1			T59	1		T140	3		T146	1
all_pins[3]	transitions[0x1=>0x0]	120	1			T26	3		T60	1		T130	2
all_pins[4]	values[0x0]	6701857	1			T1	2		T2	5204		T3	22701
all_pins[4]	values[0x1]	148	1			T26	3		T60	1		T130	2
all_pins[4]	transitions[0x0=>0x1]	126	1			T26	2		T60	1		T130	2
all_pins[4]	transitions[0x1=>0x0]	72	1			T26	1		T61	2		T59	2
all_pins[5]	values[0x0]	6701911	1			T1	2		T2	5204		T3	22701
all_pins[5]	values[0x1]	94	1			T26	2		T61	2		T59	2
all_pins[5]	transitions[0x0=>0x1]	76	1			T61	1		T59	2		T130	1
all_pins[5]	transitions[0x1=>0x0]	908705	1			T3	39		T11	1		T9	10
all_pins[6]	values[0x0]	5793282	1			T1	2		T2	5204		T3	22662
all_pins[6]	values[0x1]	908723	1			T3	39		T11	1		T9	10
all_pins[6]	transitions[0x0=>0x1]	887571	1			T3	37		T11	1		T9	10
all_pins[6]	transitions[0x1=>0x0]	347521	1			T3	1560		T9	59		T10	2278
all_pins[7]	values[0x0]	6333332	1			T1	2		T2	5204		T3	21139
all_pins[7]	values[0x1]	368673	1			T3	1562		T9	59		T10	2279
all_pins[7]	transitions[0x0=>0x1]	303045	1			T3	1547		T9	57		T10	2179
all_pins[7]	transitions[0x1=>0x0]	1044549	1			T3	260		T11	1		T10	1041
all_pins[8]	values[0x0]	5591828	1			T1	2		T2	5204		T3	22426
all_pins[8]	values[0x1]	1110177	1			T3	275		T11	1		T9	2
all_pins[8]	transitions[0x0=>0x1]	239592	1			T3	275		T9	2		T10	1141
all_pins[8]	transitions[0x1=>0x0]	217221	1			T2	1143		T3	32		T9	3
all_pins[9]	values[0x0]	5614199	1			T1	2		T2	4061		T3	22669
all_pins[9]	values[0x1]	1087806	1			T2	1143		T3	32		T11	1
all_pins[9]	transitions[0x0=>0x1]	994125	1			T2	833		T3	32		T11	1
all_pins[9]	transitions[0x1=>0x0]	72159	1			T2	940		T26	1		T16	827
all_pins[10]	values[0x0]	6536165	1			T1	2		T2	3954		T3	22701
all_pins[10]	values[0x1]	165840	1			T2	1250		T26	2		T16	2218
all_pins[10]	transitions[0x0=>0x1]	3693	1			T16	190		T17	39		T224	4
all_pins[10]	transitions[0x1=>0x0]	323493	1			T2	3336		T26	2		T16	1777
all_pins[11]	values[0x0]	6216365	1			T1	2		T2	618		T3	22701
all_pins[11]	values[0x1]	485640	1			T2	4586		T26	4		T16	3805
all_pins[11]	transitions[0x0=>0x1]	485619	1			T2	4586		T26	4		T16	3805
all_pins[11]	transitions[0x1=>0x0]	72	1			T61	1		T60	1		T130	3
all_pins[12]	values[0x0]	6701912	1			T1	2		T2	5204		T3	22701
all_pins[12]	values[0x1]	93	1			T61	1		T60	2		T130	3
all_pins[12]	transitions[0x0=>0x1]	75	1			T60	1		T130	3		T138	1
all_pins[12]	transitions[0x1=>0x0]	100	1			T61	1		T206	1		T59	2
all_pins[13]	values[0x0]	6701887	1			T1	2		T2	5204		T3	22701
all_pins[13]	values[0x1]	118	1			T61	2		T206	1		T59	2
all_pins[13]	transitions[0x0=>0x1]	96	1			T206	1		T59	2		T194	1
all_pins[13]	transitions[0x1=>0x0]	84	1			T26	2		T60	1		T130	5
all_pins[14]	values[0x0]	6701899	1			T1	2		T2	5204		T3	22701
all_pins[14]	values[0x1]	106	1			T26	2		T61	2		T60	1
all_pins[14]	transitions[0x0=>0x1]	73	1			T26	2		T61	1		T60	1
all_pins[14]	transitions[0x1=>0x0]	855660	1			T3	10		T9	1		T10	9