Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	445	1			T26	4		T61	4		T59	7
all_values[1]	445	1			T26	4		T61	4		T59	7
all_values[2]	445	1			T26	4		T61	4		T59	7
all_values[3]	445	1			T26	4		T61	4		T59	7
all_values[4]	445	1			T26	4		T61	4		T59	7
all_values[5]	445	1			T26	4		T61	4		T59	7
all_values[6]	445	1			T26	4		T61	4		T59	7
all_values[7]	445	1			T26	4		T61	4		T59	7
all_values[8]	445	1			T26	4		T61	4		T59	7
all_values[9]	445	1			T26	4		T61	4		T59	7
all_values[10]	445	1			T26	4		T61	4		T59	7
all_values[11]	445	1			T26	4		T61	4		T59	7
all_values[12]	445	1			T26	4		T61	4		T59	7
all_values[13]	445	1			T26	4		T61	4		T59	7
all_values[14]	445	1			T26	4		T61	4		T59	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3625

1

T26

34

T61

27

T59

62

auto[1]

3050

1

T26

26

T61

33

T59

43

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1177

1

T26

20

T61

19

T59

13

auto[1]

5498

1

T26

40

T61

41

T59

92

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3995

1

T26

39

T61

36

T59

57

auto[1]

2680

1

T26

21

T61

24

T59

48

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	36	1			T26	4		T130	1		T140	2
all_values[0]	auto[0]	auto[0]	auto[1]	116	1			T61	1		T59	2		T60	2
all_values[0]	auto[0]	auto[1]	auto[0]	19	1			T225	1		T212	4		T149	1
all_values[0]	auto[0]	auto[1]	auto[1]	82	1			T59	1		T60	2		T140	2
all_values[0]	auto[1]	auto[0]	auto[1]	108	1			T59	1		T60	1		T130	4
all_values[0]	auto[1]	auto[1]	auto[1]	84	1			T61	3		T59	3		T60	2
all_values[1]	auto[0]	auto[0]	auto[0]	50	1			T26	2		T130	1		T140	1
all_values[1]	auto[0]	auto[0]	auto[1]	97	1			T26	1		T61	1		T59	2
all_values[1]	auto[0]	auto[1]	auto[0]	31	1			T140	2		T146	1		T147	1
all_values[1]	auto[0]	auto[1]	auto[1]	85	1			T61	1		T59	1		T60	1
all_values[1]	auto[1]	auto[0]	auto[1]	93	1			T26	1		T59	4		T60	2
all_values[1]	auto[1]	auto[1]	auto[1]	89	1			T61	2		T60	3		T130	3
all_values[2]	auto[0]	auto[0]	auto[0]	57	1			T26	1		T59	2		T130	2
all_values[2]	auto[0]	auto[0]	auto[1]	87	1			T61	1		T59	1		T60	1
all_values[2]	auto[0]	auto[1]	auto[0]	24	1			T212	1		T226	1		T227	1
all_values[2]	auto[0]	auto[1]	auto[1]	96	1			T26	1		T61	1		T59	3
all_values[2]	auto[1]	auto[0]	auto[1]	103	1			T26	1		T61	2		T59	1
all_values[2]	auto[1]	auto[1]	auto[1]	78	1			T26	1		T60	1		T146	1
all_values[3]	auto[0]	auto[0]	auto[0]	42	1			T61	2		T130	2		T215	2
all_values[3]	auto[0]	auto[0]	auto[1]	103	1			T26	1		T59	5		T60	2
all_values[3]	auto[0]	auto[1]	auto[0]	41	1			T61	2		T215	2		T212	1
all_values[3]	auto[0]	auto[1]	auto[1]	81	1			T26	1		T60	2		T130	3
all_values[3]	auto[1]	auto[0]	auto[1]	82	1			T26	1		T59	1		T60	2
all_values[3]	auto[1]	auto[1]	auto[1]	96	1			T26	1		T59	1		T60	1
all_values[4]	auto[0]	auto[0]	auto[0]	52	1			T26	1		T61	4		T59	1
all_values[4]	auto[0]	auto[0]	auto[1]	92	1			T60	2		T130	1		T138	2
all_values[4]	auto[0]	auto[1]	auto[0]	36	1			T59	1		T226	3		T148	1
all_values[4]	auto[0]	auto[1]	auto[1]	94	1			T26	2		T59	2		T60	2
all_values[4]	auto[1]	auto[0]	auto[1]	94	1			T59	1		T60	1		T130	4
all_values[4]	auto[1]	auto[1]	auto[1]	77	1			T26	1		T59	2		T60	2
all_values[5]	auto[0]	auto[0]	auto[0]	38	1			T60	1		T130	1		T138	2
all_values[5]	auto[0]	auto[0]	auto[1]	100	1			T61	1		T59	2		T60	1
all_values[5]	auto[0]	auto[1]	auto[0]	34	1			T60	1		T140	1		T147	1
all_values[5]	auto[0]	auto[1]	auto[1]	87	1			T26	2		T61	1		T59	1
all_values[5]	auto[1]	auto[0]	auto[1]	108	1			T26	1		T59	1		T60	2
all_values[5]	auto[1]	auto[1]	auto[1]	78	1			T26	1		T61	2		T59	3
all_values[6]	auto[0]	auto[0]	auto[0]	60	1			T61	1		T130	5		T215	1
all_values[6]	auto[0]	auto[0]	auto[1]	96	1			T59	2		T60	1		T138	1
all_values[6]	auto[0]	auto[1]	auto[0]	38	1			T130	2		T138	1		T140	1
all_values[6]	auto[0]	auto[1]	auto[1]	85	1			T26	1		T61	2		T59	2
all_values[6]	auto[1]	auto[0]	auto[1]	95	1			T26	1		T61	1		T59	3
all_values[6]	auto[1]	auto[1]	auto[1]	71	1			T26	2		T60	1		T130	2
all_values[7]	auto[0]	auto[0]	auto[0]	50	1			T59	1		T130	1		T138	1
all_values[7]	auto[0]	auto[0]	auto[1]	86	1			T59	1		T60	2		T130	1
all_values[7]	auto[0]	auto[1]	auto[0]	26	1			T61	1		T59	3		T138	3
all_values[7]	auto[0]	auto[1]	auto[1]	100	1			T26	2		T61	1		T59	1
all_values[7]	auto[1]	auto[0]	auto[1]	95	1			T26	2		T60	3		T130	3
all_values[7]	auto[1]	auto[1]	auto[1]	88	1			T61	2		T59	1		T60	1
all_values[8]	auto[0]	auto[0]	auto[0]	53	1			T26	4		T61	2		T60	1
all_values[8]	auto[0]	auto[0]	auto[1]	91	1			T59	2		T60	1		T130	6
all_values[8]	auto[0]	auto[1]	auto[0]	29	1			T138	1		T140	2		T212	2
all_values[8]	auto[0]	auto[1]	auto[1]	96	1			T61	1		T59	1		T60	1
all_values[8]	auto[1]	auto[0]	auto[1]	94	1			T61	1		T59	2		T60	2
all_values[8]	auto[1]	auto[1]	auto[1]	82	1			T59	2		T60	2		T130	1
all_values[9]	auto[0]	auto[0]	auto[0]	58	1			T26	1		T61	2		T59	1
all_values[9]	auto[0]	auto[0]	auto[1]	91	1			T59	2		T60	1		T130	5
all_values[9]	auto[0]	auto[1]	auto[0]	30	1			T61	2		T138	3		T140	1
all_values[9]	auto[0]	auto[1]	auto[1]	102	1			T26	2		T60	5		T140	3
all_values[9]	auto[1]	auto[0]	auto[1]	98	1			T59	3		T60	1		T130	5
all_values[9]	auto[1]	auto[1]	auto[1]	66	1			T26	1		T59	1		T140	1
all_values[10]	auto[0]	auto[0]	auto[0]	48	1			T26	1		T61	2		T140	1
all_values[10]	auto[0]	auto[0]	auto[1]	81	1			T61	1		T59	1		T60	2
all_values[10]	auto[0]	auto[1]	auto[0]	32	1			T138	2		T140	2		T226	2
all_values[10]	auto[0]	auto[1]	auto[1]	99	1			T26	1		T59	2		T60	2
all_values[10]	auto[1]	auto[0]	auto[1]	88	1			T26	1		T61	1		T59	4
all_values[10]	auto[1]	auto[1]	auto[1]	97	1			T26	1		T60	2		T130	2
all_values[11]	auto[0]	auto[0]	auto[0]	64	1			T59	1		T130	1		T138	1
all_values[11]	auto[0]	auto[0]	auto[1]	102	1			T59	1		T60	1		T130	4
all_values[11]	auto[0]	auto[1]	auto[0]	22	1			T147	1		T215	1		T228	1
all_values[11]	auto[0]	auto[1]	auto[1]	93	1			T26	2		T61	2		T60	2
all_values[11]	auto[1]	auto[0]	auto[1]	99	1			T26	1		T61	1		T59	3
all_values[11]	auto[1]	auto[1]	auto[1]	65	1			T26	1		T61	1		T59	2
all_values[12]	auto[0]	auto[0]	auto[0]	51	1			T26	2		T59	1		T146	1
all_values[12]	auto[0]	auto[0]	auto[1]	101	1			T26	1		T61	1		T59	2
all_values[12]	auto[0]	auto[1]	auto[0]	19	1			T61	1		T59	2		T229	3
all_values[12]	auto[0]	auto[1]	auto[1]	87	1			T60	2		T130	3		T138	1
all_values[12]	auto[1]	auto[0]	auto[1]	100	1			T59	1		T60	2		T130	4
all_values[12]	auto[1]	auto[1]	auto[1]	87	1			T26	1		T61	2		T59	1
all_values[13]	auto[0]	auto[0]	auto[0]	45	1			T26	2		T147	1		T215	2
all_values[13]	auto[0]	auto[0]	auto[1]	101	1			T26	1		T61	1		T59	1
all_values[13]	auto[0]	auto[1]	auto[0]	16	1			T215	2		T225	1		T226	1
all_values[13]	auto[0]	auto[1]	auto[1]	89	1			T59	1		T60	2		T130	3
all_values[13]	auto[1]	auto[0]	auto[1]	100	1			T26	1		T59	2		T60	3
all_values[13]	auto[1]	auto[1]	auto[1]	94	1			T61	3		T59	3		T60	1
all_values[14]	auto[0]	auto[0]	auto[0]	41	1			T26	2		T130	1		T215	1
all_values[14]	auto[0]	auto[0]	auto[1]	95	1			T61	1		T59	3		T60	2
all_values[14]	auto[0]	auto[1]	auto[0]	35	1			T146	2		T147	1		T212	1
all_values[14]	auto[0]	auto[1]	auto[1]	103	1			T26	1		T59	2		T60	1
all_values[14]	auto[1]	auto[0]	auto[1]	84	1			T59	1		T60	3		T130	3
all_values[14]	auto[1]	auto[1]	auto[1]	87	1			T26	1		T61	3		T59	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal