Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.67	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	5	55	91.67

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	5	55	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6803894	1			T1	1		T2	3		T3	2
all_values[1]	6803894	1			T1	1		T2	3		T3	2
all_values[2]	6803894	1			T1	1		T2	3		T3	2
all_values[3]	6803894	1			T1	1		T2	3		T3	2
all_values[4]	6803894	1			T1	1		T2	3		T3	2
all_values[5]	6803894	1			T1	1		T2	3		T3	2
all_values[6]	6803894	1			T1	1		T2	3		T3	2
all_values[7]	6803894	1			T1	1		T2	3		T3	2
all_values[8]	6803894	1			T1	1		T2	3		T3	2
all_values[9]	6803894	1			T1	1		T2	3		T3	2
all_values[10]	6803894	1			T1	1		T2	3		T3	2
all_values[11]	6803894	1			T1	1		T2	3		T3	2
all_values[12]	6803894	1			T1	1		T2	3		T3	2
all_values[13]	6803894	1			T1	1		T2	3		T3	2
all_values[14]	6803894	1			T1	1		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97415136

1

T1

15

T2

43

T3

30

auto[1]

4643274

1

T2

2

T8

6

T6

1

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

91992700

1

T1

15

T2

45

T3

30

auto[1]

10065710

1

T10

164767

T21

768620

T57

73

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	5	55	91.67	5

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	5564805	1			T1	1		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	558779	1			T10	88966		T21	49091		T57	5
all_values[0]	auto[1]	auto[0]	563035	1			T2	1		T8	1		T9	10
all_values[0]	auto[1]	auto[1]	117275	1			T10	20880		T21	2148		T57	1
all_values[1]	auto[0]	auto[0]	5696967	1			T1	1		T2	3		T3	2
all_values[1]	auto[0]	auto[1]	616644	1			T10	96943		T21	50019		T57	4
all_values[1]	auto[1]	auto[0]	428258	1			T8	1		T9	53		T53	30
all_values[1]	auto[1]	auto[1]	62025	1			T10	12903		T21	1222		T22	1451
all_values[2]	auto[0]	auto[0]	6144906	1			T1	1		T2	3		T3	2
all_values[2]	auto[0]	auto[1]	658764	1			T10	109836		T21	51240		T22	96293
all_values[2]	auto[1]	auto[1]	224	1			T10	5		T21	3		T22	1
all_values[3]	auto[0]	auto[0]	6141518	1			T1	1		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	662179	1			T10	109840		T21	51238		T57	4
all_values[3]	auto[1]	auto[1]	197	1			T10	6		T21	3		T57	2
all_values[4]	auto[0]	auto[0]	6125794	1			T1	1		T2	3		T3	2
all_values[4]	auto[0]	auto[1]	677783	1			T10	109840		T21	51236		T22	96292
all_values[4]	auto[1]	auto[0]	98	1			T34	28		T35	48		T193	22
all_values[4]	auto[1]	auto[1]	219	1			T10	4		T21	4		T22	2
all_values[5]	auto[0]	auto[0]	6127798	1			T1	1		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	675867	1			T10	109840		T21	51241		T57	4
all_values[5]	auto[1]	auto[1]	229	1			T10	5		T21	2		T57	2
all_values[6]	auto[0]	auto[0]	5509695	1			T1	1		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	556676	1			T10	87542		T21	48974		T57	5
all_values[6]	auto[1]	auto[0]	615534	1			T2	1		T8	1		T9	44
all_values[6]	auto[1]	auto[1]	121989	1			T10	22302		T21	2266		T57	1
all_values[7]	auto[0]	auto[0]	5831705	1			T1	1		T2	3		T3	2
all_values[7]	auto[0]	auto[1]	659877	1			T10	107542		T21	50979		T57	2
all_values[7]	auto[1]	auto[0]	296105	1			T8	1		T9	696		T53	879
all_values[7]	auto[1]	auto[1]	16207	1			T10	2304		T21	263		T57	4
all_values[8]	auto[0]	auto[0]	5370333	1			T1	1		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	534536	1			T10	87535		T21	48783		T57	4
all_values[8]	auto[1]	auto[0]	770496	1			T8	1		T9	312		T53	329
all_values[8]	auto[1]	auto[1]	128529	1			T10	22310		T21	2460		T57	2
all_values[9]	auto[0]	auto[0]	5369524	1			T1	1		T2	3		T3	2
all_values[9]	auto[0]	auto[1]	537623	1			T10	89486		T21	48817		T57	2
all_values[9]	auto[1]	auto[0]	775376	1			T8	1		T6	1		T9	23
all_values[9]	auto[1]	auto[1]	121371	1			T10	20359		T21	2426		T57	3
all_values[10]	auto[0]	auto[0]	5968571	1			T1	1		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	678487	1			T10	109838		T21	51241		T57	4
all_values[10]	auto[1]	auto[0]	156639	1			T14	1979		T15	851		T19	2141
all_values[10]	auto[1]	auto[1]	197	1			T10	6		T21	2		T57	1
all_values[11]	auto[0]	auto[0]	5675810	1			T1	1		T2	3		T3	2
all_values[11]	auto[0]	auto[1]	659454	1			T10	109841		T21	51239		T57	2
all_values[11]	auto[1]	auto[0]	468426	1			T13	1647		T14	3771		T15	5160
all_values[11]	auto[1]	auto[1]	204	1			T10	5		T21	4		T57	4
all_values[12]	auto[0]	auto[0]	6125218	1			T1	1		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	678474	1			T10	109845		T21	51238		T57	4
all_values[12]	auto[1]	auto[1]	202	1			T10	1		T21	3		T57	1
all_values[13]	auto[0]	auto[0]	6140846	1			T1	1		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	662816	1			T10	109841		T21	51238		T57	4
all_values[13]	auto[1]	auto[0]	13	1			T187	1		T180	1		T194	1
all_values[13]	auto[1]	auto[1]	219	1			T10	4		T57	2		T22	2
all_values[14]	auto[0]	auto[0]	6125230	1			T1	1		T2	3		T3	2
all_values[14]	auto[0]	auto[1]	678457	1			T10	109839		T21	51240		T57	4
all_values[14]	auto[1]	auto[1]	207	1			T10	5		T57	2		T22	6