Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fifo_reset_cg

Group : i2c_env_pkg::i2c_fifo_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.82	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

---

Summary for Group i2c_env_pkg::i2c_fifo_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	2	18	90.00
Crosses	24	6	18	75.00

Variables for Group i2c_env_pkg::i2c_fifo_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acq_overflow	2	0	2	100.00	100	1	1	2
cp_acqrst	2	0	2	100.00	100	1	1	2
cp_fmt_overflow	2	1	1	50.00	100	1	1	2
cp_fmt_threshold	2	0	2	100.00	100	1	1	2
cp_fmtrst	2	0	2	100.00	100	1	1	2
cp_rx_overflow	2	1	1	50.00	100	1	1	2
cp_rx_threshold	2	0	2	100.00	100	1	1	2
cp_rxrst	2	0	2	100.00	100	1	1	2
cp_tx_overflow	2	0	2	100.00	100	1	1	2
cp_txrst	2	0	2	100.00	100	1	1	2

Crosses for Group i2c_env_pkg::i2c_fifo_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fmt_threshold_cross	4	0	4	100.00	100	1	1	0
cp_rx_threshold_cross	4	0	4	100.00	100	1	1	0
cp_fmt_overflow_cross	4	2	2	50.00	100	1	1	0
cp_rx_overflow_cross	4	2	2	50.00	100	1	1	0
cp_acq_overflow_cross	4	1	3	75.00	100	1	1	0
cp_tx_overflow_cross	4	1	3	75.00	100	1	1	0

Summary for Variable cp_acq_overflow

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acq_overflow

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31798

1

T1

1

T2

19

T3

15

auto[1]

215

1

T44

3

T179

3

T139

2

---

Summary for Variable cp_acqrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acqrst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29299

1

T2

18

T3

14

T8

34

auto[1]

2714

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_fmt_overflow

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_fmt_overflow

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32013

1

T1

1

T2

19

T3

15

---

Summary for Variable cp_fmt_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmt_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26485

1

T1

1

T2

4

T3

15

auto[1]

5528

1

T2

15

T8

34

T10

35

---

Summary for Variable cp_fmtrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmtrst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29162

1

T2

9

T3

14

T8

34

auto[1]

2851

1

T1

1

T2

10

T3

1

---

Summary for Variable cp_rx_overflow

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_rx_overflow

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32013

1

T1

1

T2

19

T3

15

---

Summary for Variable cp_rx_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rx_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28439

1

T1

1

T2

19

T3

15

auto[1]

3574

1

T8

33

T10

23

T21

8

---

Summary for Variable cp_rxrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxrst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29519

1

T2

18

T3

14

T8

34

auto[1]

2494

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_tx_overflow

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_tx_overflow

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31983

1

T1

1

T2

19

T3

15

auto[1]

30

1

T180

2

T181

3

T182

1

---

Summary for Variable cp_txrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_txrst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29299

1

T2

18

T3

14

T8

34

auto[1]

2714

1

T1

1

T2

1

T3

1

---

Summary for Cross cp_fmt_threshold_cross

Samples crossed: cp_fmt_threshold cp_fmtrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_fmt_threshold_cross

Bins

cp_fmt_threshold

cp_fmtrst

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23954

1

T2

1

T3

14

T6

5

auto[0]

auto[1]

2531

1

T1

1

T2

3

T3

1

auto[1]

auto[0]

5208

1

T2

8

T8

34

T10

35

auto[1]

auto[1]

320

1

T2

7

T38

5

T39

1

---

Summary for Cross cp_rx_threshold_cross

Samples crossed: cp_rx_threshold cp_rxrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_rx_threshold_cross

Bins

cp_rx_threshold

cp_rxrst

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

25967

1

T2

18

T3

14

T8

1

auto[0]

auto[1]

2472

1

T1

1

T2

1

T3

1

auto[1]

auto[0]

3552

1

T8

33

T10

23

T21

8

auto[1]

auto[1]

22

1

T183

1

T184

1

T152

1

---

Summary for Cross cp_fmt_overflow_cross

Samples crossed: cp_fmt_overflow cp_fmtrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for cp_fmt_overflow_cross

Element holes

cp_fmt_overflow	cp_fmtrst	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	*	--	--	2

Covered bins

cp_fmt_overflow

cp_fmtrst

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

29162

1

T2

9

T3

14

T8

34

auto[0]

auto[1]

2851

1

T1

1

T2

10

T3

1

---

Summary for Cross cp_rx_overflow_cross

Samples crossed: cp_rx_overflow cp_rxrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for cp_rx_overflow_cross

Element holes

cp_rx_overflow	cp_rxrst	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	*	--	--	2

Covered bins

cp_rx_overflow

cp_rxrst

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

29519

1

T2

18

T3

14

T8

34

auto[0]

auto[1]

2494

1

T1

1

T2

1

T3

1

---

Summary for Cross cp_acq_overflow_cross

Samples crossed: cp_acq_overflow cp_acqrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	1	3	75.00	1

Automatically Generated Cross Bins for cp_acq_overflow_cross

Uncovered bins

cp_acq_overflow	cp_acqrst	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_acq_overflow

cp_acqrst

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

29084

1

T2

18

T3

14

T8

34

auto[0]

auto[1]

2714

1

T1

1

T2

1

T3

1

auto[1]

auto[0]

215

1

T44

3

T179

3

T139

2

---

Summary for Cross cp_tx_overflow_cross

Samples crossed: cp_tx_overflow cp_txrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	1	3	75.00	1

Automatically Generated Cross Bins for cp_tx_overflow_cross

Uncovered bins

cp_tx_overflow	cp_txrst	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_tx_overflow

cp_txrst

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

29269

1

T2

18

T3

14

T8

34

auto[0]

auto[1]

2714

1

T1

1

T2

1

T3

1

auto[1]

auto[0]

30

1

T180

2

T181

3

T182

1