Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6803894	1			T1	1		T2	3		T3	2
all_pins[1]	6803894	1			T1	1		T2	3		T3	2
all_pins[2]	6803894	1			T1	1		T2	3		T3	2
all_pins[3]	6803894	1			T1	1		T2	3		T3	2
all_pins[4]	6803894	1			T1	1		T2	3		T3	2
all_pins[5]	6803894	1			T1	1		T2	3		T3	2
all_pins[6]	6803894	1			T1	1		T2	3		T3	2
all_pins[7]	6803894	1			T1	1		T2	3		T3	2
all_pins[8]	6803894	1			T1	1		T2	3		T3	2
all_pins[9]	6803894	1			T1	1		T2	3		T3	2
all_pins[10]	6803894	1			T1	1		T2	3		T3	2
all_pins[11]	6803894	1			T1	1		T2	3		T3	2
all_pins[12]	6803894	1			T1	1		T2	3		T3	2
all_pins[13]	6803894	1			T1	1		T2	3		T3	2
all_pins[14]	6803894	1			T1	1		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	97348813	1			T1	15		T2	43		T3	30
values[0x1]	4709597	1			T2	2		T8	6		T6	1
transitions[0x0=>0x1]	3223929	1			T2	2		T8	2		T6	1
transitions[0x1=>0x0]	3223941	1			T2	2		T8	2		T6	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	6123353	1			T1	1		T2	2		T3	2
all_pins[0]	values[0x1]	680541	1			T2	1		T8	1		T9	12
all_pins[0]	transitions[0x0=>0x1]	211010	1			T2	1		T9	12		T10	7982
all_pins[0]	transitions[0x1=>0x0]	23122	1			T9	62		T10	1		T53	33
all_pins[1]	values[0x0]	6311241	1			T1	1		T2	3		T3	2
all_pins[1]	values[0x1]	492653	1			T8	1		T9	62		T10	12898
all_pins[1]	transitions[0x0=>0x1]	492631	1			T8	1		T9	62		T10	12898
all_pins[1]	transitions[0x1=>0x0]	93	1			T10	1		T21	1		T176	3
all_pins[2]	values[0x0]	6803779	1			T1	1		T2	3		T3	2
all_pins[2]	values[0x1]	115	1			T10	1		T21	1		T176	3
all_pins[2]	transitions[0x0=>0x1]	88	1			T10	1		T21	1		T176	3
all_pins[2]	transitions[0x1=>0x0]	68	1			T10	5		T57	1		T176	2
all_pins[3]	values[0x0]	6803799	1			T1	1		T2	3		T3	2
all_pins[3]	values[0x1]	95	1			T10	5		T57	1		T176	2
all_pins[3]	transitions[0x0=>0x1]	69	1			T10	3		T57	1		T176	1
all_pins[3]	transitions[0x1=>0x0]	204	1			T10	1		T21	1		T22	1
all_pins[4]	values[0x0]	6803664	1			T1	1		T2	3		T3	2
all_pins[4]	values[0x1]	230	1			T10	3		T21	1		T22	1
all_pins[4]	transitions[0x0=>0x1]	200	1			T10	3		T21	1		T176	3
all_pins[4]	transitions[0x1=>0x0]	74	1			T10	2		T21	1		T57	1
all_pins[5]	values[0x0]	6803790	1			T1	1		T2	3		T3	2
all_pins[5]	values[0x1]	104	1			T10	2		T21	1		T57	1
all_pins[5]	transitions[0x0=>0x1]	76	1			T10	1		T21	1		T57	1
all_pins[5]	transitions[0x1=>0x0]	740933	1			T2	1		T8	1		T9	55
all_pins[6]	values[0x0]	6062933	1			T1	1		T2	2		T3	2
all_pins[6]	values[0x1]	740961	1			T2	1		T8	1		T9	55
all_pins[6]	transitions[0x0=>0x1]	723466	1			T2	1		T9	49		T10	22059
all_pins[6]	transitions[0x1=>0x0]	331566	1			T9	811		T10	2463		T53	1013
all_pins[7]	values[0x0]	6454833	1			T1	1		T2	3		T3	2
all_pins[7]	values[0x1]	349061	1			T8	1		T9	817		T10	2705
all_pins[7]	transitions[0x0=>0x1]	287972	1			T9	806		T10	2462		T53	991
all_pins[7]	transitions[0x1=>0x0]	861230	1			T9	368		T10	22064		T53	367
all_pins[8]	values[0x0]	5881575	1			T1	1		T2	3		T3	2
all_pins[8]	values[0x1]	922319	1			T8	1		T9	379		T10	22307
all_pins[8]	transitions[0x0=>0x1]	217651	1			T9	379		T10	1956		T53	389
all_pins[8]	transitions[0x1=>0x0]	192975	1			T6	1		T9	28		T18	1
all_pins[9]	values[0x0]	5906251	1			T1	1		T2	3		T3	2
all_pins[9]	values[0x1]	897643	1			T8	1		T6	1		T9	28
all_pins[9]	transitions[0x0=>0x1]	818785	1			T8	1		T6	1		T9	28
all_pins[9]	transitions[0x1=>0x0]	78174	1			T10	2		T14	634		T15	584
all_pins[10]	values[0x0]	6646862	1			T1	1		T2	3		T3	2
all_pins[10]	values[0x1]	157032	1			T10	2		T14	1982		T15	854
all_pins[10]	transitions[0x0=>0x1]	3250	1			T10	2		T14	122		T15	22
all_pins[10]	transitions[0x1=>0x0]	314740	1			T10	2		T13	1647		T14	1911
all_pins[11]	values[0x0]	6335372	1			T1	1		T2	3		T3	2
all_pins[11]	values[0x1]	468522	1			T10	2		T13	1647		T14	3771
all_pins[11]	transitions[0x0=>0x1]	468501	1			T10	2		T13	1647		T14	3771
all_pins[11]	transitions[0x1=>0x0]	64	1			T10	1		T22	1		T176	1
all_pins[12]	values[0x0]	6803809	1			T1	1		T2	3		T3	2
all_pins[12]	values[0x1]	85	1			T10	1		T21	1		T22	1
all_pins[12]	transitions[0x0=>0x1]	60	1			T10	1		T21	1		T22	1
all_pins[12]	transitions[0x1=>0x0]	112	1			T10	1		T57	1		T22	1
all_pins[13]	values[0x0]	6803757	1			T1	1		T2	3		T3	2
all_pins[13]	values[0x1]	137	1			T10	1		T57	1		T22	1
all_pins[13]	transitions[0x0=>0x1]	103	1			T10	1		T187	1		T180	1
all_pins[13]	transitions[0x1=>0x0]	65	1			T10	3		T22	1		T36	3
all_pins[14]	values[0x0]	6803795	1			T1	1		T2	3		T3	2
all_pins[14]	values[0x1]	99	1			T10	3		T57	1		T22	2
all_pins[14]	transitions[0x0=>0x1]	67	1			T10	2		T57	1		T36	4
all_pins[14]	transitions[0x1=>0x0]	680521	1			T2	1		T8	1		T9	12